particular slave MCU has been addressed it will receive the following data frames as normal while theother slave MCUs will ignore the received frames until another address frame is received
21101 Using MPCMnFor an MCU to act as a master MCU it can use a 9-bit character frame format (UCSZ1=7) The ninth bit(TXB8) must be set when an address frame (TXB8=1) or cleared when a data frame (TXB=0) is beingtransmitted The slave MCUs must in this case be set to use a 9-bit character frame format
The following procedure should be used to exchange data in Multi-Processor Communication Mode
1 All Slave MCUs are in Multi-Processor Communication mode (MPCM in UCSRnA is set)2 The Master MCU sends an address frame and all slaves receive and read this frame In the Slave
MCUs the RXC Flag in UCSRnA will be set as normal3 Each Slave MCU reads the UDRn Register and determines if it has been selected If so it clears
the MPCM bit in UCSRnA otherwise it waits for the next address byte and keeps the MPCMsetting
4 The addressed MCU will receive all data frames until a new address frame is received The otherSlave MCUs which still have the MPCM bit set will ignore the data frames
5 When the last data frame is received by the addressed MCU the addressed MCU sets the MPCMbit and waits for a new address frame from master The process then repeats from step 2
Using any of the 5- to 8-bit character frame formats is possible but impractical since the Receiver mustchange between using n and n+1 character frame formats This makes full-duplex operation difficult sincethe Transmitter and Receiver uses the same character size setting If 5- to 8-bit character frames areused the Transmitter must be set to use two stop bit (USBS = 1) since the first stop bit is used forindicating the frame type
Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCM bit The MPCM bitshares the same IO location as the TXC Flag and this might accidentally be cleared when using SBI orCBI instructions
2111 Examples of Baud Rate SettingFor standard crystal and resonator frequencies the most commonly used baud rates for asynchronousoperation can be generated by using the UBRRn settings as listed in the table below
UBRRn values which yield an actual baud rate differing less than 05 from the target baud rate are boldin the table Higher error ratings are acceptable but the Receiver will have less noise resistance when theerror ratings are high especially for large serial frames (see also section Asynchronous OperationalRange) The error values are calculated using the following equation
= BaudRateClosest MatchBaudRate minus 1 2 100Table 21-4 Examples of UBRRn Settings for Commonly Used Oscillator Frequencies
BaudRate[bps]
fosc = 10000MHz fosc = 18432MHz fosc = 20000MHz
U2X = 0 U2X = 1 U2X = 0 U2X = 1 U2X = 0 U2X = 1
UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error
9600 6 -70 12 02 11 00 23 00 12 02 25 02
144k 3 85 8 -35 7 00 15 00 8 -35 16 21
192k 2 85 6 -70 5 00 11 00 6 -70 12 02
288k 1 85 3 85 3 00 7 00 3 85 8 -35
384k 1 -186 2 85 2 00 5 00 2 85 6 -70
576k 0 85 1 85 1 00 3 00 1 85 3 85
768k ndash ndash 1 -186 1 -250 2 00 1 -186 2 85
1152k ndash ndash 0 85 0 00 1 00 0 85 1 85
2304k ndash ndash ndash ndash ndash ndash 0 00 ndash ndash ndash ndash
250k ndash ndash ndash ndash ndash ndash ndash ndash ndash ndash 0 00
Max(1) 625kbps 125kbps 1152kbps 2304kbps 125kbps 250kbps
Note 1 UBRRn = 0 Error = 00
Table 21-5 Examples of UBRRn Settings for Commonly Used Oscillator Frequencies
Baud Rate[bps]
fosc = 36864MHz fosc = 40000MHz fosc = 73728MHz
U2X = 0 U2X = 1 U2X = 0 U2X = 1 U2X = 0 U2X = 1
UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error
2400 95 00 191 00 103 02 207 02 191 00 383 00
4800 47 00 95 00 51 02 103 02 95 00 191 00
9600 23 00 47 00 25 02 51 02 47 00 95 00
144k 15 00 31 00 16 21 34 -08 31 00 63 00
192k 11 00 23 00 12 02 25 02 23 00 47 00
288k 7 00 15 00 8 -35 16 21 15 00 31 00
384k 5 00 11 00 6 -70 12 02 11 00 23 00
576k 3 00 7 00 3 85 8 -35 7 00 15 00
768k 2 00 5 00 2 85 6 -70 5 00 11 00
1152k 1 00 3 00 1 85 3 85 3 00 7 00
2304k 0 00 1 00 0 85 1 85 1 00 3 00
250k 0 -78 1 -78 0 00 1 00 1 -78 3 -78
05M ndash ndash 0 -78 ndash ndash 0 00 0 -78 1 -78
Atmel ATmega164PA [DATASHEET]Atmel-42713C-ATmega164PA_Datasheet_Complete-102016
243
Baud Rate[bps]
fosc = 36864MHz fosc = 40000MHz fosc = 73728MHz
U2X = 0 U2X = 1 U2X = 0 U2X = 1 U2X = 0 U2X = 1
UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error
1M ndash ndash ndash ndash ndash ndash ndash ndash ndash ndash 0 -78
Max(1) 2304kbps 4608kbps 250kbps 05Mbps 4608kbps 9216kbps
(1) UBRRn = 0 Error = 00
Table 21-6 Examples of UBRRn Settings for Commonly Used Oscillator Frequencies
Baud Rate[bps]
fosc = 80000MHz fosc = 110592MHz fosc = 147456MHz
U2X = 0 U2X = 1 U2X = 0 U2X = 1 U2X = 0 U2X = 1
UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error
2400 207 02 416 -01 287 00 575 00 383 00 767 00
4800 103 02 207 02 143 00 287 00 191 00 383 00
9600 51 02 103 02 71 00 143 00 95 00 191 00
144k 34 -08 68 06 47 00 95 00 63 00 127 00
192k 25 02 51 02 35 00 71 00 47 00 95 00
288k 16 21 34 -08 23 00 47 00 31 00 63 00
384k 12 02 25 02 17 00 35 00 23 00 47 00
576k 8 -35 16 21 11 00 23 00 15 00 31 00
768k 6 -70 12 02 8 00 17 00 11 00 23 00
1152k 3 85 8 -35 5 00 11 00 7 00 15 00
2304k 1 85 3 85 2 00 5 00 3 00 7 00
250k 1 00 3 00 2 -78 5 -78 3 -78 6 53
05M 0 00 1 00 ndash ndash 2 -78 1 -78 3 -78
1M ndash ndash 0 00 ndash ndash ndash ndash 0 -78 1 -78
Max(1) 05Mbps 1Mbps 6912kbps 13824Mbps 9216kbps 18432Mbps
(1) UBRRn = 0 Error = 00
Table 21-7 Examples of UBRRn Settings for Commonly Used Oscillator Frequencies
Baud Rate[bps]
fosc = 160000MHz fosc = 184320MHz fosc = 200000MHz
U2X = 0 U2X = 1 U2X = 0 U2X = 1 U2X = 0 U2X = 1
UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error
2400 416 -01 832 00 479 00 959 00 520 00 1041 00
4800 207 02 416 -01 239 00 479 00 259 02 520 00
Atmel ATmega164PA [DATASHEET]Atmel-42713C-ATmega164PA_Datasheet_Complete-102016
244
Baud Rate[bps]
fosc = 160000MHz fosc = 184320MHz fosc = 200000MHz
U2X = 0 U2X = 1 U2X = 0 U2X = 1 U2X = 0 U2X = 1
UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error
9600 103 02 207 02 119 00 239 00 129 02 259 02
144k 68 06 138 -01 79 00 159 00 86 -02 173 -02
192k 51 02 103 02 59 00 119 00 64 02 129 02
288k 34 -08 68 06 39 00 79 00 42 09 86 -02
384k 25 02 51 02 29 00 59 00 32 -14 64 02
576k 16 21 34 -08 19 00 39 00 21 -14 42 09
768k 12 02 25 02 14 00 29 00 15 17 32 -14
1152k 8 -35 16 21 9 00 19 00 10 -14 21 -14
2304k 3 85 8 -35 4 00 9 00 4 85 10 -14
250k 3 00 7 00 4 -78 8 24 4 00 9 00
05M 1 00 3 00 ndash ndash 4 -78 ndash ndash 4 00
1M 0 00 1 00 ndash ndash ndash ndash ndash ndash ndash ndash
Max(1) 1Mbps 2Mbps 1152Mbps 2304Mbps 125Mbps 25Mbps
(1) UBRRn = 0 Error = 00
Related LinksAsynchronous Operational Range on page 240
2112 Register Description
Atmel ATmega164PA [DATASHEET]Atmel-42713C-ATmega164PA_Datasheet_Complete-102016
245
21121 USART IO Data Register nThe USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the sameIO address referred to as USART Data Register or UDRn The Transmit Data Buffer Register (TXB) willbe the destination for data written to the UDR1 Register location Reading the UDRn Register location willreturn the contents of the Receive Data Buffer Register (RXB)
For 5- 6- or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to zero bythe Receiver
The transmit buffer can only be written when the UDRE Flag in the UCSRnA Register is set Data writtento UDRn when the UCSRnAUDRE Flag is not set will be ignored by the USART Transmitter n Whendata is written to the transmit buffer and the Transmitter is enabled the Transmitter will load the data intothe Transmit Shift Register when the Shift Register is empty Then the data will be serially transmitted onthe TxDn pin
The receive buffer consists of a two level FIFO The FIFO will change its state whenever the receivebuffer is accessed Due to this behavior of the receive buffer do not use Read-Modify-Write instructions(SBI and CBI) on this location Be careful when using bit test instructions (SBIC and SBIS) since thesealso will change the state of the FIFO
Name UDRnOffset 0xC6 + n0x08 [n=01]Reset 0x00Property
-
Bit 7 6 5 4 3 2 1 0 TXB RXB[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash TXB RXB[70] USART Transmit Receive Data Buffer
Atmel ATmega164PA [DATASHEET]Atmel-42713C-ATmega164PA_Datasheet_Complete-102016
246
21122 USART Control and Status Register n A
Name UCSR0A UCSR1AOffset 0xC0 + n0x08 [n=01]Reset 0x20Property
-
Bit 7 6 5 4 3 2 1 0 RXC TXC UDRE FE DOR UPE U2X MPCM
Access R RW R R R R RW RW Reset 0 0 1 0 0 0 0 0
Bit 7 ndash RXC USART Receive CompleteThis flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer isempty (ie does not contain any unread data) If the Receiver is disabled the receive buffer will beflushed and consequently the RXC bit will become zero The RXC Flag can be used to generate aReceive Complete interrupt (see description of the RXCIE bit)
Bit 6 ndash TXC USART Transmit CompleteThis flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and there areno new data currently present in the transmit buffer (UDRn) The TXC Flag bit is automatically clearedwhen a transmit complete interrupt is executed or it can be cleared by writing a one to its bit location TheTXC Flag can generate a Transmit Complete interrupt (see description of the TXCIE bit)
Bit 5 ndash UDRE USART Data Register EmptyThe UDRE Flag indicates if the transmit buffer (UDRn) is ready to receive new data If UDRE is one thebuffer is empty and therefore ready to be written The UDRE Flag can generate a Data Register Emptyinterrupt (see description of the UDRIE bit) UDRE is set after a reset to indicate that the Transmitter isready
Bit 4 ndash FE Frame ErrorThis bit is set if the next character in the receive buffer had a Frame Error when received Ie when thefirst stop bit of the next character in the receive buffer is zero This bit is valid until the receive buffer(UDRn) is read The FEn bit is zero when the stop bit of received data is one Always set this bit to zerowhen writing to UCSRnA
This bit is reserved in Master SPI Mode (MSPIM)
Bit 3 ndash DOR Data OverRunThis bit is set if a Data OverRun condition is detected A Data OverRun occurs when the receive buffer isfull (two characters) it is a new character waiting in the Receive Shift Register and a new start bit isdetected This bit is valid until the receive buffer (UDRn) is read Always set this bit to zero when writingto UCSRnA
This bit is reserved in Master SPI Mode (MSPIM)
Bit 2 ndash UPE USART Parity ErrorThis bit is set if the next character in the receive buffer had a Parity Error when received and the ParityChecking was enabled at that point (UCSRnCUPM1 = 1) This bit is valid until the receive buffer (UDRn)is read Always set this bit to zero when writing to UCSRnA
This bit is reserved in Master SPI Mode (MSPIM)
Atmel ATmega164PA [DATASHEET]Atmel-42713C-ATmega164PA_Datasheet_Complete-102016
247
Bit 1 ndash U2X Double the USART Transmission SpeedThis bit only has effect for the asynchronous operation Write this bit to zero when using synchronousoperation
Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling thetransfer rate for asynchronous communication
This bit is reserved in Master SPI Mode (MSPIM)
Bit 0 ndash MPCM Multi-processor Communication ModeThis bit enables the Multi-processor Communication mode When the MPCM bit is written to one all theincoming frames received by the USART Receiver n that do not contain address information will beignored The Transmitter is unaffected by the MPCM setting Refer to Multi-Processor CommunicationMode for details
This bit is reserved in Master SPI Mode (MSPIM)
Atmel ATmega164PA [DATASHEET]Atmel-42713C-ATmega164PA_Datasheet_Complete-102016
248
21123 USART Control and Status Register n B
Name UCSR0B UCSR1BOffset 0xC1 + n0x08 [n=01]Reset 0x00Property
-
Bit 7 6 5 4 3 2 1 0 RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8
Access RW RW RW RW RW RW R RW Reset 0 0 0 0 0 0 0 0
Bit 7 ndash RXCIE RX Complete Interrupt EnableWriting this bit to one enables interrupt on the UCSRnARXC Flag A USART Receive Complete interruptwill be generated only if the RXCIE bit is written to one the Global Interrupt Flag in SREG is written toone and the RXC bit in UCSRnA is set
Bit 6 ndash TXCIE TX Complete Interrupt EnableWriting this bit to one enables interrupt on the TXC Flag A USART Transmit Complete interrupt will begenerated only if the TXCIE bit is written to one the Global Interrupt Flag in SREG is written to one andthe TXC bit in UCSRnA is set
Bit 5 ndash UDRIE USART Data Register Empty Interrupt EnableWriting this bit to one enables interrupt on the UDRE Flag A Data Register Empty interrupt will begenerated only if the UDRIE bit is written to one the Global Interrupt Flag in SREG is written to one andthe UDRE bit in UCSRnA is set
Bit 4 ndash RXEN Receiver EnableWriting this bit to one enables the USART Receiver The Receiver will override normal port operation forthe RxDn pin when enabled Disabling the Receiver will flush the receive buffer invalidating the FE DORand UPE Flags
Bit 3 ndash TXEN Transmitter EnableWriting this bit to one enables the USART Transmitter The Transmitter will override normal port operationfor the TxDn pin when enabled The disabling of the Transmitter (writing TXEN to zero) will not becomeeffective until ongoing and pending transmissions are completed ie when the Transmit Shift Registerand Transmit Buffer Register do not contain data to be transmitted When disabled the Transmitter will nolonger override the TxDn port
Bit 2 ndash UCSZ2 Character SizeThe UCSZ2 bits combined with the UCSZ[10] bit in UCSRnC sets the number of data bits (CharacterSize) in a frame the Receiver and Transmitter use
This bit is reserved in Master SPI Mode (MSPIM)
Bit 1 ndash RXB8 Receive Data Bit 8RXB8 is the ninth data bit of the received character when operating with serial frames with nine data bitsMust be read before reading the low bits from UDRn
This bit is reserved in Master SPI Mode (MSPIM)
Atmel ATmega164PA [DATASHEET]Atmel-42713C-ATmega164PA_Datasheet_Complete-102016
249