Introduction and Motivation - Hiroshima U

Mattausch, CMOS Design, H20/4/11 1

Introduction and MotivationGeneral InformationSchedule in 2008Semiconductor Market/Technology TrendsProcessor-Chip DevelopmentDesign ChallengesDesign MethodologiesSystem-on-Chip Design

CMOS Logic Circuit Designhttp://www.rcns.hiroshima-u.ac.jp

Link（リンク）: センター教官講義ノートの下 CMOS論理回路設計


Lecturer and Teaching Assistant

LecturerHans Jürgen Mattausch

Email: [email protected]: Campus Number 6268 ，内線６２６８Office: Research Center for Nanodevices and Systems

Room 304ナノデバイス・システム研究センター，室３０４

Teaching Assistant (TA)Naomi Nagaoka （永岡奈緒美）

Email: [email protected]: Campus Number 3045 ，内線３０４５Office: Research Center for Nanodevices and Systems

Room 301ナノデバイス・システム研究センター，室３０１


General information about this lecturePlace, Time a) Lecture Room 103b) H20 summer semester, Fridays 16:20-17:50

16 lecture days (1 opening, 13 lectures, 1 intermediate exercise/examination, 1 finalexamination)

Keywords of lecture contentsCMOS、論理回路、レイアウト、動的な回路、タイミング

Aims of lectureThis course teaches the methods of CMOS integrated circuit design in greater detail to students who have already learned the basics of integrated circuits.

Lecture notesWill be made available on the Internet as pdf-files at:http://www.rcns.hiroshima-u.ac.jpLink（リンク）: センター教官講義ノートの下

CMOS論理回路設計」講義ノート

Practical experience and exercisesVisits to the CMOS circuit research facilities of the Research Center for Nanodevices and Systems will be offered to interested Students in June/July.Exercise hours will be offered during the semester.

Lecture creditsa) Attendance of all lecture days is necessary for admittance to final examination. Attendance is documented by short tests during each lecture.b) Homework/Test problems: If answers are exactly the same, they are assumed to be copied. All identical solutions will receive only an equal fraction of the total point number. This means that each of the N copies of a solution with Ssol points will receive Ssol/N points.c) Final written examination

Main reference books for the lecturea) Principles of CMOS VLSI Design, A System Perspective; N. H. E. Weste, K. Eshraghian; ISBN 0-201-53376-6b) Digital Integrated Circuits, A Design Persepctive; J. M. Rabaey, A. Chandrakasan and B. Nikolic; ISBN 0-13-120764-4


Preliminary schedule of this lecture

4/11 Opening and Introduction

4/18 Short Repetition of Integrated-Circuit Basics

4/25 Static and Dynamic CMOS Design

5/2 Special -Purpose Digital Circuits

5/9 CMOS Layout

5/16 Combinational and SequentialCMOS Circuits

5/23 Logic Design for Speed (LogicalEffort)

5/30 Exercise and Intermediate Test

6/6 Arithmetic Modules I

6/13 Arithmetic Modules II

6/20 Memory Circuits I

6/27 Memory Circuits II

7/4 Interconnects

7/11 Clock and Timing

7/18 Design for Testability

7/25 Final examination

Practical Experience and Exercise:-Visit possibilities to the CMOS circuit research laboratories at RCNS in June and/or July.

-Exercise hours for lecture content if necessary.


Semiconductor Market Trends

0%

10%

20%

30%

40%

50%

60%

1982 1988 1994 2000 2003 2004 2005

America Europe Rest of World (RWO) Japan

0.0

10.0

20.0

30.0

40.0

50.0

60.0

70.0

2000 2003 2004 2005

America Japan China

Bill

ions

of D

olla

rs

Worldwide IC Sales byCompany Headquarters

In 2005 China Became the Largest IC Market of the World


Semiconductor Market Size and Growth in 2006

Data from


Semiconductor Market Growth by Category(Data from )

MOS Logic is the largest and second faster growing LSI product. Flash EEPROM is the fastest growing LSI product.


Semiconductor Technology Trends

Data from ITRS-2003

(International Technology Roadmap for Semiconductors)

572572572572572ASIC maximum

chip size (mm2)

12,9586,4793,2391,620810ASIC maximum

transistors

(million)

310310310310310MPU chip size

(mm2)

7,0223,5111,756878439Transistors per

MPU chip

(million)

1014202845Physical Gate

Length (nm)

1420284065Printed Gate

Length (nm)

30426085120MPU/ASIC

Metal1 ½ Pitch

(nm)

25355070100DRAM ½ Pitch

(nm)

20152012200920062003Year of Production


50nm

インフルエンザウィルスナノトランジスタ

Nanodevices, Dream of Miniaturized Technology

Realization of Transistors with a few Nanometers in Size

Planar integrated memory with these ➔ １cm2 can store 200 booksSugar-cube-sized 3d integrated circuit can store Japanese national library

Nano-Transistor Influenza Virus


Technology Improvement from 1978 to 2005

Source: Intel (G. Moore, 2003)


Comparison of First and Today’s Processor Chips

Intel 4004 (first Microprocessor)(shipped from 1971, ~2,000 Transistors)

Intel Pentium 4(shipped from 2000, ~40,000,000 Transistors)


18.1mm

12.2mm

Cell Processor Chip Presented at ISSCC’2005(IBM, Sony and Toshiba, 90nm Technology, 9 Processor Cores, 234 Million Transistors)

Appeared in workstations in 2006 and in game equipment in 2007


Integrated Circuit Design Challenges

Design-Productivity Crisis• Chip-Complexity Increase: 58%/Year• Design-Productivity Increase: 21%/Year

Design Effortsfor

MIPS-ProcessorGenerations

>3536>1006.801996R 10000

2024551.401991R 4000

1515200.101985R 2000

Verification (Effort in %)

Design Time (Month)

Design Team

(Persons)

Transistors (Million)

Production Year

MIPSProcessor


University Education and Industry Needs

University Education Capacity(Thesis Research Subject)

Semiconductor IndustryEmployee Needs

Re-Education

after joining Industry

Big gap between education profile of employees needed by industry and education capacity of universities. ⇨ Bigger design crisis.

DeviceProcessMaterial

80%

LSIDesign

20%

LSIDesign80%

DeviceProcessMaterial

20%


Design Methodology 1

Full-Custom Design Flow Semi-Custom Design Flow

HighLevel

LowLevel


Design Methodology 2

HDL(VERILOG) Program Semi-Custom Design Synthesis

LogicSynthesis

LayoutSynthesis

+


System on Chip (SoC) Design

Chip-Configuration PossibilitiesSoC Design Example (Voice Engine)

Introduction and Motivation - Hiroshima U

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