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8-bit AVR Microcontrollers
ATmega328/P
DATASHEET COMPLETE
Introduction
The Atmel® picoPower® ATmega328/P is a low-power CMOS
8-bitmicrocontroller based on the AVR® enhanced RISC architecture.
Byexecuting powerful instructions in a single clock cycle, the
ATmega328/Pachieves throughputs close to 1MIPS per MHz. This
empowers systemdesigner to optimize the device for power
consumption versus processingspeed.
Feature
High Performance, Low Power Atmel®AVR® 8-Bit Microcontroller
Family• Advanced RISC Architecture
– 131 Powerful Instructions– Most Single Clock Cycle Execution–
32 x 8 General Purpose Working Registers– Fully Static Operation–
Up to 20 MIPS Throughput at 20MHz– On-chip 2-cycle Multiplier
• High Endurance Non-volatile Memory Segments– 32KBytes of
In-System Self-Programmable Flash program
Memory– 1KBytes EEPROM– 2KBytes Internal SRAM– Write/Erase
Cycles: 10,000 Flash/100,000 EEPROM– Data Retention: 20 years at
85°C/100 years at 25°C(1)
– Optional Boot Code Section with Independent Lock Bits•
In-System Programming by On-chip Boot Program• True
Read-While-Write Operation
– Programming Lock for Software Security• Atmel® QTouch® Library
Support
– Capacitive Touch Buttons, Sliders and Wheels– QTouch and
QMatrix® Acquisition– Up to 64 sense channels
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• Peripheral Features– Two 8-bit Timer/Counters with Separate
Prescaler and Compare Mode– One 16-bit Timer/Counter with Separate
Prescaler, Compare Mode, and Capture Mode– Real Time Counter with
Separate Oscillator– Six PWM Channels– 8-channel 10-bit ADC in TQFP
and QFN/MLF package
• Temperature Measurement– 6-channel 10-bit ADC in PDIP
Package
• Temperature Measurement– Two Master/Slave SPI Serial
Interface– One Programmable Serial USART– One Byte-oriented 2-wire
Serial Interface (Philips I2C compatible)– Programmable Watchdog
Timer with Separate On-chip Oscillator– One On-chip Analog
Comparator– Interrupt and Wake-up on Pin Change
• Special Microcontroller Features– Power-on Reset and
Programmable Brown-out Detection– Internal Calibrated Oscillator–
External and Internal Interrupt Sources– Six Sleep Modes: Idle, ADC
Noise Reduction, Power-save, Power-down, Standby, and
Extended Standby• I/O and Packages
– 23 Programmable I/O Lines– 28-pin PDIP, 32-lead TQFP, 28-pad
QFN/MLF and 32-pad QFN/MLF
• Operating Voltage:– 1.8 - 5.5V
• Temperature Range:– -40°C to 105°C
• Speed Grade:– 0 - 4MHz @ 1.8 - 5.5V– 0 - 10MHz @ 2.7 - 5.5V– 0
- 20MHz @ 4.5 - 5.5V
• Power Consumption at 1MHz, 1.8V, 25°C– Active Mode: 0.2mA–
Power-down Mode: 0.1μA– Power-save Mode: 0.75μA (Including 32kHz
RTC)
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Table of Contents
Introduction......................................................................................................................1
Feature............................................................................................................................
1
1.
Description.................................................................................................................9
2. Configuration
Summary...........................................................................................10
3. Ordering Information
...............................................................................................
113.1. ATmega328
...............................................................................................................................
113.2. ATmega328P
.............................................................................................................................12
4. Block
Diagram.........................................................................................................
13
5. Pin
Configurations...................................................................................................
145.1.
Pin-out........................................................................................................................................
145.2. Pin
Descriptions..........................................................................................................................17
6. I/O
Multiplexing........................................................................................................19
7.
Resources................................................................................................................21
8. Data
Retention.........................................................................................................22
9. About Code
Examples.............................................................................................23
10. Capacitive Touch
Sensing.......................................................................................
2410.1. QTouch
Library...........................................................................................................................
24
11. AVR CPU
Core........................................................................................................
2511.1.
Overview.....................................................................................................................................2511.2.
ALU – Arithmetic Logic
Unit........................................................................................................2611.3.
Status
Register...........................................................................................................................2611.4.
General Purpose Register
File...................................................................................................
2811.5. Stack
Pointer..............................................................................................................................
2911.6. Instruction Execution
Timing......................................................................................................
3111.7. Reset and Interrupt
Handling.....................................................................................................
32
12. AVR
Memories.........................................................................................................3412.1.
Overview.....................................................................................................................................3412.2.
In-System Reprogrammable Flash Program
Memory................................................................3412.3.
SRAM Data
Memory...................................................................................................................3512.4.
EEPROM Data
Memory.............................................................................................................
3612.5. I/O
Memory.................................................................................................................................3712.6.
Register
Description...................................................................................................................
38
13. System Clock and Clock
Options............................................................................
48
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13.1. Clock Systems and Their
Distribution.........................................................................................4813.2.
Clock
Sources............................................................................................................................
4913.3. Low Power Crystal
Oscillator......................................................................................................5113.4.
Full Swing Crystal
Oscillator.......................................................................................................5213.5.
Low Frequency Crystal
Oscillator...............................................................................................5313.6.
Calibrated Internal RC
Oscillator................................................................................................5413.7.
128kHz Internal
Oscillator..........................................................................................................
5513.8. External
Clock............................................................................................................................
5613.9. Timer/Counter
Oscillator.............................................................................................................5713.10.
Clock Output
Buffer....................................................................................................................5713.11.
System Clock
Prescaler.............................................................................................................
5713.12. Register
Description...................................................................................................................58
14. PM - Power Management and Sleep
Modes...........................................................6214.1.
Overview.....................................................................................................................................6214.2.
Sleep
Modes...............................................................................................................................6214.3.
BOD
Disable...............................................................................................................................6314.4.
Idle
Mode....................................................................................................................................6314.5.
ADC Noise Reduction
Mode.......................................................................................................6314.6.
Power-Down
Mode.....................................................................................................................6414.7.
Power-save
Mode.......................................................................................................................6414.8.
Standby
Mode............................................................................................................................
6514.9. Extended Standby
Mode............................................................................................................
6514.10. Power Reduction
Register.........................................................................................................
6514.11. Minimizing Power
Consumption.................................................................................................
6514.12. Register
Description...................................................................................................................67
15. SCRST - System Control and
Reset.......................................................................
7215.1. Resetting the
AVR......................................................................................................................
7215.2. Reset
Sources............................................................................................................................7215.3.
Power-on
Reset..........................................................................................................................7315.4.
External
Reset............................................................................................................................7415.5.
Brown-out
Detection...................................................................................................................7415.6.
Watchdog System
Reset............................................................................................................
7515.7. Internal Voltage
Reference.........................................................................................................7515.8.
Watchdog
Timer.........................................................................................................................
7615.9. Register
Description...................................................................................................................
78
16.
Interrupts.................................................................................................................
8216.1. Interrupt Vectors in
ATmega328/P..............................................................................................8216.2.
Register
Description...................................................................................................................
84
17. EXINT - External
Interrupts.....................................................................................
8717.1. Pin Change Interrupt
Timing.......................................................................................................8717.2.
Register
Description...................................................................................................................
88
18.
I/O-Ports..................................................................................................................
9718.1.
Overview.....................................................................................................................................9718.2.
Ports as General Digital
I/O........................................................................................................98
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18.3. Alternate Port
Functions...........................................................................................................10118.4.
Register
Description.................................................................................................................
113
19. TC0 - 8-bit Timer/Counter0 with
PWM...................................................................12519.1.
Features...................................................................................................................................
12519.2.
Overview...................................................................................................................................12519.3.
Timer/Counter Clock
Sources..................................................................................................
12719.4. Counter
Unit.............................................................................................................................
12719.5. Output Compare
Unit................................................................................................................12819.6.
Compare Match Output
Unit.....................................................................................................13019.7.
Modes of
Operation..................................................................................................................13119.8.
Timer/Counter Timing
Diagrams...............................................................................................13519.9.
Register
Description.................................................................................................................
137
20. TC1 - 16-bit Timer/Counter1 with
PWM.................................................................14920.1.
Overview...................................................................................................................................14920.2.
Features...................................................................................................................................
14920.3. Block
Diagram..........................................................................................................................
14920.4.
Definitions.................................................................................................................................15020.5.
Registers..................................................................................................................................
15120.6. Accessing 16-bit
Registers.......................................................................................................15120.7.
Timer/Counter Clock
Sources..................................................................................................
15420.8. Counter
Unit.............................................................................................................................
15420.9. Input Capture
Unit....................................................................................................................
15520.10. Output Compare
Units.............................................................................................................
15720.11. Compare Match Output
Unit.....................................................................................................15920.12.
Modes of
Operation..................................................................................................................16020.13.
Timer/Counter Timing
Diagrams..............................................................................................
16820.14. Register
Description.................................................................................................................169
21. Timer/Counter 0, 1
Prescalers...............................................................................18621.1.
Internal Clock
Source...............................................................................................................
18621.2. Prescaler
Reset........................................................................................................................18621.3.
External Clock
Source..............................................................................................................18621.4.
Register
Description.................................................................................................................
187
22. TC2 - 8-bit Timer/Counter2 with PWM and Asynchronous
Operation................... 18922.1.
Features...................................................................................................................................
18922.2.
Overview...................................................................................................................................18922.3.
Timer/Counter Clock
Sources..................................................................................................
19122.4. Counter
Unit.............................................................................................................................
19122.5. Output Compare
Unit................................................................................................................19222.6.
Compare Match Output
Unit.....................................................................................................19422.7.
Modes of
Operation..................................................................................................................19522.8.
Timer/Counter Timing
Diagrams...............................................................................................19922.9.
Asynchronous Operation of
Timer/Counter2............................................................................
20022.10. Timer/Counter
Prescaler..........................................................................................................
20222.11. Register
Description.................................................................................................................
202
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23. SPI – Serial Peripheral
Interface...........................................................................
21523.1.
Features...................................................................................................................................
21523.2.
Overview...................................................................................................................................21523.3.
SS Pin
Functionality.................................................................................................................
21923.4. Data
Modes..............................................................................................................................
21923.5. Register
Description.................................................................................................................
220
24. USART - Universal Synchronous Asynchronous Receiver
Transceiver................22524.1.
Features...................................................................................................................................
22524.2.
Overview...................................................................................................................................22524.3.
Block
Diagram..........................................................................................................................
22524.4. Clock
Generation......................................................................................................................22624.5.
Frame
Formats.........................................................................................................................22924.6.
USART
Initialization..................................................................................................................23024.7.
Data Transmission – The USART
Transmitter.........................................................................
23124.8. Data Reception – The USART
Receiver..................................................................................
23324.9. Asynchronous Data
Reception.................................................................................................23724.10.
Multi-Processor Communication
Mode....................................................................................
23924.11. Examples of Baud Rate
Setting...............................................................................................
24024.12. Register
Description.................................................................................................................243
25. USARTSPI - USART in SPI
Mode.........................................................................25425.1.
Features...................................................................................................................................
25425.2.
Overview...................................................................................................................................25425.3.
Clock
Generation......................................................................................................................25425.4.
SPI Data Modes and
Timing.....................................................................................................25525.5.
Frame
Formats.........................................................................................................................25525.6.
Data
Transfer............................................................................................................................25725.7.
AVR USART MSPIM vs. AVR
SPI............................................................................................25825.8.
Register
Description.................................................................................................................
259
26. TWI - 2-wire Serial
Interface..................................................................................26026.1.
Features...................................................................................................................................
26026.2. Two-Wire Serial Interface Bus
Definition..................................................................................26026.3.
Data Transfer and Frame
Format.............................................................................................26126.4.
Multi-master Bus Systems, Arbitration and
Synchronization....................................................26426.5.
Overview of the TWI
Module....................................................................................................
26626.6. Using the
TWI...........................................................................................................................26826.7.
Transmission
Modes................................................................................................................
27126.8. Multi-master Systems and
Arbitration.......................................................................................28926.9.
Register
Description.................................................................................................................
291
27. AC - Analog
Comparator.......................................................................................
29927.1.
Overview...................................................................................................................................29927.2.
Analog Comparator Multiplexed
Input......................................................................................
29927.3. Register
Description.................................................................................................................
300
28. ADC - Analog to Digital
Converter.........................................................................305
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28.1.
Features...................................................................................................................................
30528.2.
Overview...................................................................................................................................30528.3.
Starting a
Conversion...............................................................................................................30728.4.
Prescaling and Conversion
Timing...........................................................................................30828.5.
Changing Channel or Reference
Selection..............................................................................
31028.6. ADC Noise
Canceler................................................................................................................
31228.7. ADC Conversion
Result............................................................................................................31528.8.
Temperature
Measurement......................................................................................................
31628.9. Register
Description.................................................................................................................
316
29. DBG - debugWIRE On-chip Debug
System..........................................................
32729.1.
Features...................................................................................................................................
32729.2.
Overview...................................................................................................................................32729.3.
Physical
Interface.....................................................................................................................
32729.4. Software Break
Points..............................................................................................................32829.5.
Limitations of
debugWIRE........................................................................................................32829.6.
Register
Description.................................................................................................................
328
30. BTLDR - Boot Loader Support – Read-While-Write
Self-Programming................ 33030.1.
Features...................................................................................................................................
33030.2.
Overview...................................................................................................................................33030.3.
Application and Boot Loader Flash
Sections............................................................................33030.4.
Read-While-Write and No Read-While-Write Flash
Sections...................................................33130.5.
Boot Loader Lock
Bits..............................................................................................................
33330.6. Entering the Boot Loader
Program...........................................................................................33430.7.
Addressing the Flash During
Self-Programming......................................................................
33530.8. Self-Programming the
Flash.....................................................................................................33630.9.
Register
Description.................................................................................................................
344
31. MEMPROG- Memory
Programming......................................................................34731.1.
Program And Data Memory Lock
Bits......................................................................................
34731.2. Fuse
Bits...................................................................................................................................34831.3.
Signature
Bytes........................................................................................................................
35031.4. Calibration
Byte........................................................................................................................
35131.5. Page
Size.................................................................................................................................
35131.6. Parallel Programming Parameters, Pin Mapping, and
Commands..........................................35131.7. Parallel
Programming...............................................................................................................35331.8.
Serial
Downloading...................................................................................................................360
32. Electrical
Characteristics.......................................................................................
36532.1. Absolute Maximum
Ratings......................................................................................................36532.2.
Common DC
Characteristics....................................................................................................36532.3.
Speed
Grades..........................................................................................................................
36832.4. Clock
Characteristics................................................................................................................36932.5.
System and Reset
Characteristics...........................................................................................
37032.6. SPI Timing
Characteristics.......................................................................................................
37132.7. Two-wire Serial Interface
Characteristics.................................................................................
37232.8. ADC
Characteristics.................................................................................................................
37432.9. Parallel Programming
Characteristics......................................................................................
375
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33. Typical Characteristics (TA = -40°C to
85°C).........................................................37833.1.
ATmega328 Typical
Characteristics.........................................................................................
378
34. Typical Characteristics (TA = -40°C to
105°C).......................................................40334.1.
ATmega328P Typical
Characteristics.......................................................................................403
35. Register
Summary.................................................................................................42835.1.
Note..........................................................................................................................................430
36. Instruction Set
Summary.......................................................................................
432
37. Packaging
Information...........................................................................................43637.1.
32-pin
32A................................................................................................................................
43637.2. 32-pin
32M1-A..........................................................................................................................43737.3.
28-pin
28M1..............................................................................................................................43837.4.
28-pin
28P3..............................................................................................................................
439
38.
Errata.....................................................................................................................44038.1.
Errata
ATmega328/P................................................................................................................440
39. Datasheet Revision
History...................................................................................
44139.1. Rev. B –
11/2016......................................................................................................................
44139.2. Rev. A –
06/2016......................................................................................................................441
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1. DescriptionThe Atmel AVR® core combines a rich instruction
set with 32 general purpose working registers. All the32 registers
are directly connected to the Arithmetic Logic Unit (ALU), allowing
two independent registersto be accessed in a single instruction
executed in one clock cycle. The resulting architecture is more
codeefficient while achieving throughputs up to ten times faster
than conventional CISC microcontrollers.
The ATmega328/P provides the following features: 32Kbytes of
In-System Programmable Flash withRead-While-Write capabilities,
1Kbytes EEPROM, 2Kbytes SRAM, 23 general purpose I/O lines,
32general purpose working registers, Real Time Counter (RTC), three
flexible Timer/Counters with comparemodes and PWM, 1 serial
programmable USARTs , 1 byte-oriented 2-wire Serial Interface
(I2C), a 6-channel 10-bit ADC (8 channels in TQFP and QFN/MLF
packages) , a programmable Watchdog Timerwith internal Oscillator,
an SPI serial port, and six software selectable power saving modes.
The Idlemode stops the CPU while allowing the SRAM, Timer/Counters,
SPI port, and interrupt system tocontinue functioning. The
Power-down mode saves the register contents but freezes the
Oscillator,disabling all other chip functions until the next
interrupt or hardware reset. In Power-save mode, theasynchronous
timer continues to run, allowing the user to maintain a timer base
while the rest of thedevice is sleeping. The ADC Noise Reduction
mode stops the CPU and all I/O modules exceptasynchronous timer and
ADC to minimize switching noise during ADC conversions. In Standby
mode, thecrystal/resonator oscillator is running while the rest of
the device is sleeping. This allows very fast start-upcombined with
low power consumption. In Extended Standby mode, both the main
oscillator and theasynchronous timer continue to run.
Atmel offers the QTouch® library for embedding capacitive touch
buttons, sliders and wheels functionalityinto AVR microcontrollers.
The patented charge-transfer signal acquisition offers robust
sensing andincludes fully debounced reporting of touch keys and
includes Adjacent Key Suppression® (AKS™)technology for unambiguous
detection of key events. The easy-to-use QTouch Suite toolchain
allows youto explore, develop and debug your own touch
applications.
The device is manufactured using Atmel’s high density
non-volatile memory technology. The On-chip ISPFlash allows the
program memory to be reprogrammed In-System through an SPI serial
interface, by aconventional nonvolatile memory programmer, or by an
On-chip Boot program running on the AVR core.The Boot program can
use any interface to download the application program in the
Application Flashmemory. Software in the Boot Flash section will
continue to run while the Application Flash section isupdated,
providing true Read-While-Write operation. By combining an 8-bit
RISC CPU with In-SystemSelf-Programmable Flash on a monolithic
chip, the Atmel ATmega328/P is a powerful microcontroller
thatprovides a highly flexible and cost effective solution to many
embedded control applications.
The ATmega328/P is supported with a full suite of program and
system development tools including: CCompilers, Macro Assemblers,
Program Debugger/Simulators, In-Circuit Emulators, and Evaluation
kits.
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2. Configuration SummaryFeatures ATmega328/P
Pin Count 28/32
Flash (Bytes) 32K
SRAM (Bytes) 2K
EEPROM (Bytes) 1K
General Purpose I/O Lines 23
SPI 2
TWI (I2C) 1
USART 1
ADC 10-bit 15kSPS
ADC Channels 8
8-bit Timer/Counters 2
16-bit Timer/Counters 1
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3. Ordering Information
3.1. ATmega328
Speed [MHz](3) Power Supply [V] Ordering Code(2) Package(1)
Operational Range
20 1.8 - 5.5
ATmega328-AUATmega328-AUR(5)ATmega328-MMH(4)ATmega328-MMHR(4)(5)ATmega328-MUATmega328-MUR(5)ATmega328-PU
32A32A28M128M132M1-A32M1-A28P3
Industrial(-40°C to 85°C)
Note: 1. This device can also be supplied in wafer form. Please
contact your local Atmel sales office for
detailed ordering information and minimum quantities.2. Pb-free
packaging, complies to the European Directive for Restriction of
Hazardous Substances
(RoHS directive). Also Halide free and fully Green.3. Please
refer to Speed Grades for Speed vs. VCC4. Tape & Reel.5. NiPdAu
Lead Finish.
Package Type
28M1 28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45mm Quad Flat
No-Lead/Micro Lead Frame Package (QFN/MLF)
28P3 28-lead, 0.300” Wide, Plastic Dual Inline Package
(PDIP)
32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50mm Quad Flat
No-Lead/Micro Lead Frame Package (QFN/MLF)
32A 32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)
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3.2. ATmega328P
Speed [MHz](3) Power Supply [V] Ordering Code(2) Package(1)
Operational Range
20 1.8 - 5.5
ATmega328P-AUATmega328P-AUR(5)ATmega328P-MMH(4)ATmega328P-MMHR(4)(5)ATmega328P-MUATmega328P-MUR(5)ATmega328P-PU
32A32A28M128M132M1-A32M1-A28P3
Industrial(-40°C to 85°C)
ATmega328P-ANATmega328P-ANR(5)ATmega328P-MNATmega328P-MNR(5)ATmega328P-PN
32A32A32M1-A32M1-A28P3
Industrial(-40°C to 105°C)
Note: 1. This device can also be supplied in wafer form. Please
contact your local Atmel sales office for
detailed ordering information and minimum quantities.2. Pb-free
packaging, complies to the European Directive for Restriction of
Hazardous Substances
(RoHS directive). Also Halide free and fully Green.3. Please
refer to Speed Grades for Speed vs. VCC4. Tape & Reel.5. NiPdAu
Lead Finish.
Package Type
28M1 28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45mm Quad Flat
No-Lead/Micro Lead Frame Package (QFN/MLF)
28P3 28-lead, 0.300” Wide, Plastic Dual Inline Package
(PDIP)
32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50mm Quad Flat
No-Lead/Micro Lead Frame Package (QFN/MLF)
32A 32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)
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4. Block DiagramFigure 4-1. Block Diagram
CPU
USART 0
ADCADC[7:0]AREF
RxD0TxD0XCK0
I/OPORTS
DATABUS
GPIOR[2:0]
SRAM
OCD
EXTINT
FLASHNVM
programming
debugWire
IN/OUT
DATABUS
TC 0(8-bit)
SPI 0
ACAIN0AIN1
ADCMUX
EEPROM
EEPROMIF
TC 1(16-bit)
OC1A/BT1
ICP1
TC 2(8-bit async)
TWI 0 SDA0SCL0
InternalReference
Watchdog Timer
Power management
and clock control
VCC
GND
Clock generation8MHz
Calib RC
128kHz int osc
32.768kHz XOSC
External clock
Power SupervisionPOR/BOD &
RESET
XTAL2 / TOSC2
RESET
XTAL1 /TOSC1
16MHz LP XOSC
PCINT[23:0]INT[1:0]
T0OC0AOC0B
MISO0MOSI0SCK0SS0
OC2AOC2B
PB[7:0]PC[6:0]PD[7:0]
ADC6,ADC7,PC[5:0]AREF
PD[7:0], PC[6:0], PB[7:0]PD3, PD2
PB1, PB2PD5PB0
PB3PD3
PD4PD6PD5
PB4PB3PB5PB2
PD6PD7
ADC6, ADC7PC[5:0]
PD0PD1PD4
PC4PC5
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5. Pin Configurations
5.1. Pin-outFigure 5-1. 28-pin PDIP
Power
Ground
Programming/debug
Digital
Analog
Crystal/Osc
(PCINT14/RESET) PC6
(PCINT16/RXD) PD0
(PCINT17/TXD) PD1
(PCINT18/INT0) PD2
(PCINT19/OC2B/INT1) PD3
(PCINT20/XCK/T0) PD4
VCC
GND
(PCINT6/XTAL1/TOSC1) PB6
(PCINT7/XTAL2/TOSC2) PB7
(PCINT21/OC0B/T1) PD5
(PCINT22/OC0A/AIN0) PD6
(PCINT23/AIN1) PD7
(PCINT0/CLKO/ICP1) PB0
PC5 (ADC5/SCL/PCINT13)
PC4 (ADC4/SDA/PCINT12)
PC3 (ADC3/PCINT11)
PC2 (ADC2/PCINT10)
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
GND
AREF
AVCC
PB5 (SCK/PCINT5)
PB4 (MISO/PCINT4)
PB3 (MOSI/OC2A/PCINT3)
PB2 (SS/OC1B/PCINT2)
PB1 (OC1A/PCINT1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
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Figure 5-2. 28-pin MLF Top View
1
2
3
4
5
6
7
8 9 10 11 12 13 14
PD2
(INT0
/PC
INT1
8)
PD1
(TXD
/PC
INT1
7)
PD0
(RXD
/PC
INT1
6)
PC6
(RES
ET/P
CIN
T14)
PC5
(AD
C5/
SCL/
PCIN
T13)
PC4
(AD
C4/
SDA/
PCIN
T12)
PC3
(AD
C3/
PCIN
T11)
PC2 (ADC2/PCINT10)
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
GND
AREF
AVCC
PB5 (SCK/PCINT5)
(PCI
NT2
2/O
C0A
/AIN
0) P
D6
(PCI
NT2
3/A
IN1)
PD
7
(PCI
NT0
/CLK
O/IC
P1) P
B0
(PCI
NT1
/OC1
A) P
B1
(PCI
NT2
/SS/
OC1
B) P
B2
(PCI
NT3
/OC2
A/M
OSI
) PB3
(PCI
NT4
/MIS
O) P
B4
(PCINT19/OC2B/INT1) PD3
(PCINT20/XCK/T0) PD4
VCC
GND
(PCINT6/XTAL1/TOSC1) PB6
(PCINT7/XTAL2/TOSC2) PB7
(PCINT21/OC0B/T1) PD5
Bottom pad should be soldered to ground
Power
Ground
Programming/debug
Digital
Analog
Crystal/CLK
21
20
19
18
17
16
15
28 27 26 25 24 23 22
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Figure 5-3. 32-pin TQFP Top View
1
2
3
432 31 30 29 28 27 26
5
6
7
8
24
23
22
21
20
19
18
17
25
9 10 11 12 13 14 15 16
Power
Ground
Programming/debug
Digital
Analog
Crystal/CLK
(PCINT19/OC2B/INT1) PD3
(PCINT20/XCK/T0) PD4
GND
VCC
GND
VCC
(PCINT6/XTAL1/TOSC1) PB6
(PCINT7/XTAL2/TOSC2) PB7
PD2
(INT0
/PCI
NT18
)
PD1
(TXD
/PCI
NT17
)
PD0
(RXD
/PCI
NT16
)
PC6
(RES
ET/P
CINT
14)
PC5
(ADC
5/SC
L/PC
INT1
3)
PC4
(ADC
4/SD
A/PC
INT1
2)
PC3
(ADC
3/PC
INT1
1)
PC2
(ADC
2/PC
INT1
0)
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
ADC7
GND
AREF
ADC6
AVCC
PB5 (SCK/PCINT5)
(PC
INT2
1/O
C0B
/T1)
PD
5
(PC
INT2
2/O
C0A
/AIN
0) P
D6
(PC
INT2
3/AI
N1)
PD
7
(PC
INT0
/CLK
O/IC
P1) P
B0
(PC
INT1
/OC
1A) P
B1
(PC
INT2
/SS/
OC
1B) P
B2
(PC
INT3
/OC
2A/M
OSI
) PB3
(PC
INT4
/MIS
O) P
B4
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Figure 5-4. 32-pin MLF Top View
1
2
3
432 31 30 29 28 27 26
5
6
7
8
24
23
22
21
20
19
18
17
25
9 10 11 12 13 14 15 16
PD2
(INT0
/PC
INT1
8)
PD1
(TXD
/PC
INT1
7)
PD0
(RXD
/PC
INT1
6)
PC6
(RES
ET/P
CIN
T14)
PC5
(AD
C5/
SCL/
PCIN
T13)
PC4
(AD
C4/
SDA/
PCIN
T12)
PC3
(AD
C3/
PCIN
T11)
PC2
(AD
C2/
PCIN
T10)
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
ADC7
GND
AREF
ADC6
AVCC
PB5 (SCK/PCINT5)
(PCI
NT2
1/O
C0B/
T1) P
D5
(PCI
NT2
2/O
C0A
/AIN
0) P
D6
(PCI
NT2
3/A
IN1)
PD
7
(PCI
NT0
/CLK
O/IC
P1) P
B0
(PCI
NT1
/OC1
A) P
B1
(PCI
NT2
/SS/
OC1
B) P
B2
(PCI
NT3
/OC2
A/M
OSI
) PB3
(PCI
NT4
/MIS
O) P
B4
(PCINT19/OC2B/INT1) PD3
(PCINT20/XCK/T0) PD4
GND
VCC
GND
VCC
(PCINT6/XTAL1/TOSC1) PB6
(PCINT7/XTAL2/TOSC2) PB7
Bottom pad should be soldered to ground
Power
Ground
Programming/debug
Digital
Analog
Crystal/CLK
5.2. Pin Descriptions
5.2.1. VCCDigital supply voltage.
5.2.2. GNDGround.
5.2.3. Port B (PB[7:0]) XTAL1/XTAL2/TOSC1/TOSC2Port B is an
8-bit bi-directional I/O port with internal pull-up resistors
(selected for each bit). The Port Boutput buffers have symmetrical
drive characteristics with both high sink and source capability. As
inputs,Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. The PortB pins are
tri-stated when a reset condition becomes active, even if the clock
is not running.
Depending on the clock selection fuse settings, PB6 can be used
as input to the inverting Oscillatoramplifier and input to the
internal clock operating circuit.
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Depending on the clock selection fuse settings, PB7 can be used
as output from the inverting Oscillatoramplifier.
If the Internal Calibrated RC Oscillator is used as chip clock
source, PB[7:6] is used as TOSC[2:1] inputfor the Asynchronous
Timer/Counter2 if the AS2 bit in ASSR is set.
5.2.4. Port C (PC[5:0])Port C is a 7-bit bi-directional I/O port
with internal pull-up resistors (selected for each bit). The
PC[5:0]output buffers have symmetrical drive characteristics with
both high sink and source capability. As inputs,Port C pins that
are externally pulled low will source current if the pull-up
resistors are activated. The PortC pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
5.2.5. PC6/RESETIf the RSTDISBL Fuse is programmed, PC6 is used
as an I/O pin. Note that the electrical characteristicsof PC6
differ from those of the other pins of Port C.
If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset
input. A low level on this pin for longerthan the minimum pulse
length will generate a Reset, even if the clock is not running.
Shorter pulses arenot guaranteed to generate a Reset.
The various special features of Port C are elaborated in the
Alternate Functions of Port C section.
5.2.6. Port D (PD[7:0])Port D is an 8-bit bi-directional I/O
port with internal pull-up resistors (selected for each bit). The
Port Doutput buffers have symmetrical drive characteristics with
both high sink and source capability. As inputs,Port D pins that
are externally pulled low will source current if the pull-up
resistors are activated. The PortD pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
5.2.7. AVCCAVCC is the supply voltage pin for the A/D Converter,
PC[3:0], and PE[3:2]. It should be externallyconnected to VCC, even
if the ADC is not used. If the ADC is used, it should be connected
to VCC througha low-pass filter. Note that PC[6:4] use digital
supply voltage, VCC.
5.2.8. AREFAREF is the analog reference pin for the A/D
Converter.
5.2.9. ADC[7:6] (TQFP and VFQFN Package Only)In the TQFP and
VFQFN package, ADC[7:6] serve as analog inputs to the A/D
converter. These pins arepowered from the analog supply and serve
as 10-bit ADC channels.
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6. I/O MultiplexingEach pin is by default controlled by the PORT
as a general purpose I/O and alternatively it can beassigned to one
of the peripheral functions.
The following table describes the peripheral signals multiplexed
to the PORT I/O pins.
Table 6-1. PORT Function Multiplexing
(32-pinMLF/TQFP)Pin#
(28-pinMLF) Pin#
(28-pinPIPD) Pin#
PAD EXTINT PCINT ADC/AC OSC T/C #0 T/C#1
USART 0 I2C 0 SPI 0
1 1 5 PD[3] INT1 PCINT19 OC2B
2 2 6 PD[4] PCINT20 T0 XCK0
4 3 7 VCC
3 4 8 GND
6 - - VCC
5 - - GND
7 5 9 PB[6] PCINT6 XTAL1/TOSC1
8 6 10 PB[7] PCINT7 XTAL2/TOSC2
9 7 11 PD[5] PCINT21 OC0B T1
10 8 12 PD[6] PCINT22 AIN0 OC0A
11 9 13 PD[7] PCINT23 AIN1
12 10 14 PB[0] PCINT0 CLKO ICP1
13 11 15 PB[1] PCINT1 OC1A
14 12 16 PB[2] PCINT2 OC1B SS0
15 13 17 PB[3] PCINT3 OC2A MOSI0
16 14 18 PB[4] PCINT4 MISO0
17 15 19 PB[5] PCINT5 SCK0
18 16 20 AVCC
19 - - ADC6 ADC6
20 17 21 AREF
21 18 22 GND
22 - - ADC7 ADC7
23 19 13 PC[0] PCINT8 ADC0
24 20 24 PC[1] PCINT9 ADC1
25 21 25 PC[2] PCINT10 ADC2
26 22 26 PC[3] PCINT11 ADC3
27 23 27 PC[4] PCINT12 ADC4 SDA0
28 24 28 PC[5] PCINT13 ADC5 SCL0
29 25 1 PC[6]/RESET
PCINT14
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(32-pinMLF/TQFP)Pin#
(28-pinMLF) Pin#
(28-pinPIPD) Pin#
PAD EXTINT PCINT ADC/AC OSC T/C #0 T/C#1
USART 0 I2C 0 SPI 0
30 26 2 PD[0] PCINT16 RXD0
31 27 3 PD[1] PCINT17 TXD0
32 28 4 PD[2] INT0 PCINT18
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7. ResourcesA comprehensive set of development tools,
application notes, and datasheets are available for downloadon
http://www.atmel.com/avr.
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http://www.atmel.com/avr
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8. Data RetentionReliability Qualification results show that the
projected data retention failure rate is much less than 1 PPMover
20 years at 85°C or 100 years at 25°C.
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9. About Code ExamplesThis documentation contains simple code
examples that briefly show how to use various parts of thedevice.
These code examples assume that the part specific header file is
included before compilation. Beaware that not all C compiler
vendors include bit definitions in the header files and interrupt
handling in Cis compiler dependent. Confirm with the C compiler
documentation for more details.
For I/O Registers located in extended I/O map, “IN”, “OUT”,
“SBIS”, “SBIC”, “CBI”, and “SBI” instructionsmust be replaced with
instructions that allow access to extended I/O. Typically “LDS” and
“STS”combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
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10. Capacitive Touch Sensing
10.1. QTouch LibraryThe Atmel® QTouch® Library provides a simple
to use solution to realize touch sensitive interfaces onmost Atmel
AVR® microcontrollers. The QTouch Library includes support for the
Atmel QTouch and AtmelQMatrix® acquisition methods.
Touch sensing can be added to any application by linking the
appropriate Atmel QTouch Library for theAVR Microcontroller. This
is done by using a simple set of APIs to define the touch channels
and sensors,and then calling the touch sensing API’s to retrieve
the channel information and determine the touchsensor states.
The QTouch Library is FREE and downloadable from the Atmel
website at the following location:
http://www.atmel.com/technologies/touch/. For implementation
details and other information, refer to the AtmelQTouch Library
User Guide - also available for download from the Atmel
website.
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http://www.atmel.com/technologies/touch/http://www.atmel.com/technologies/touch/http://www.atmel.com/dyn/resources/prod_documents/doc8207.pdfhttp://www.atmel.com/dyn/resources/prod_documents/doc8207.pdf
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11. AVR CPU Core
11.1. OverviewThis section discusses the AVR core architecture
in general. The main function of the CPU core is toensure correct
program execution. The CPU must therefore be able to access
memories, performcalculations, control peripherals, and handle
interrupts.
Figure 11-1. Block Diagram of the AVR Architecture
Register file
Flash program memory
Program counter
Instruction register
Instruction decode
Data memory
ALUStatus register
R0R1R2R3R4R5R6R7R8R9
R10R11R12R13R14R15R16R17R18R19R20R21R22R23R24R25
R26 (XL)R27 (XH)R28 (YL)R29 (YH)R30 (ZL)R31 (ZH)
Stack pointer
In order to maximize performance and parallelism, the AVR uses a
Harvard architecture – with separatememories and buses for program
and data. Instructions in the program memory are executed with
asingle level pipelining. While one instruction is being executed,
the next instruction is pre-fetched from theprogram memory. This
concept enables instructions to be executed in every clock cycle.
The programmemory is In-System Reprogrammable Flash memory.
The fast-access Register File contains 32 x 8-bit general
purpose working registers with a single clockcycle access time.
This allows single-cycle Arithmetic Logic Unit (ALU) operation. In
a typical ALUoperation, two operands are output from the Register
File, the operation is executed, and the result isstored back in
the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect
address register pointers for Data Spaceaddressing – enabling
efficient address calculations. One of the these address pointers
can also be usedas an address pointer for look up tables in Flash
program memory. These added function registers arethe 16-bit X-,
Y-, and Z-register, described later in this section.
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The ALU supports arithmetic and logic operations between
registers or between a constant and aregister. Single register
operations can also be executed in the ALU. After an arithmetic
operation, theStatus Register is updated to reflect information
about the result of the operation.
Program flow is provided by conditional and unconditional jump
and call instructions, able to directlyaddress the whole address
space. Most AVR instructions have a single 16-bit word format.
Everyprogram memory address contains a 16- or 32-bit
instruction.
Program Flash memory space is divided in two sections, the Boot
Program section and the ApplicationProgram section. Both sections
have dedicated Lock bits for write and read/write protection. The
SPMinstruction that writes into the Application Flash memory
section must reside in the Boot Program section.
During interrupts and subroutine calls, the return address
Program Counter (PC) is stored on the Stack.The Stack is
effectively allocated in the general data SRAM, and consequently
the Stack size is onlylimited by the total SRAM size and the usage
of the SRAM. All user programs must initialize the SP in theReset
routine (before subroutines or interrupts are executed). The Stack
Pointer (SP) is read/writeaccessible in the I/O space. The data
SRAM can easily be accessed through the five different
addressingmodes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and
regular memory maps.
A flexible interrupt module has its control registers in the I/O
space with an additional Global InterruptEnable bit in the Status
Register. All interrupts have a separate Interrupt Vector in the
Interrupt Vectortable. The interrupts have priority in accordance
with their Interrupt Vector position. The lower theInterrupt Vector
address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral
functions as Control Registers, SPI,and other I/O functions. The
I/O Memory can be accessed directly, or as the Data Space
locationsfollowing those of the Register File, 0x20 - 0x5F. In
addition, this device has Extended I/O space from0x60 - 0xFF in
SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be
used.
11.2. ALU – Arithmetic Logic UnitThe high-performance AVR ALU
operates in direct connection with all the 32 general purpose
workingregisters. Within a single clock cycle, arithmetic
operations between general purpose registers or betweena register
and an immediate are executed. The ALU operations are divided into
three main categories –arithmetic, logical, and bit-functions. Some
implementations of the architecture also provide a
powerfulmultiplier supporting both signed/unsigned multiplication
and fractional format. See Instruction SetSummary section for a
detailed description.
Related LinksInstruction Set Summary on page 432
11.3. Status RegisterThe Status Register contains information
about the result of the most recently executed
arithmeticinstruction. This information can be used for altering
program flow in order to perform conditionaloperations. The Status
Register is updated after all ALU operations, as specified in the
Instruction SetReference. This will in many cases remove the need
for using the dedicated compare instructions,resulting in faster
and more compact code.
The Status Register is not automatically stored when entering an
interrupt routine and restored whenreturning from an interrupt.
This must be handled by software.
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11.3.1. Status RegisterWhen addressing I/O Registers as data
space using LD and ST instructions, the provided offset must
beused. When using the I/O specific commands IN and OUT, the offset
is reduced by 0x20, resulting in anI/O address offset within 0x00 -
0x3F.
Name: SREGOffset: 0x5FReset: 0x00Property:
When addressing as I/O Register: address offset is 0x3F
Bit 7 6 5 4 3 2 1 0 I T H S V N Z C
Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bit 7 – I: Global Interrupt EnableThe Global Interrupt Enable
bit must be set for the interrupts to be enabled. The individual
interruptenable control is then performed in separate control
registers. If the Global Interrupt Enable Register iscleared, none
of the interrupts are enabled independent of the individual
interrupt enable settings. The I-bit is cleared by hardware after
an interrupt has occurred, and is set by the RETI instruction to
enablesubsequent interrupts. The I-bit can also be set and cleared
by the application with the SEI and CLIinstructions, as described
in the instruction set reference.
Bit 6 – T: Copy StorageThe Bit Copy instructions BLD (Bit LoaD)
and BST (Bit STore) use the T-bit as source or destination forthe
operated bit. A bit from a register in the Register File can be
copied into T by the BST instruction, anda bit in T can be copied
into a bit in a register in the Register File by the BLD
instruction.
Bit 5 – H: Half Carry FlagThe Half Carry Flag H indicates a Half
Carry in some arithmetic operations. Half Carry Flag is useful
inBCD arithmetic. See the Instruction Set Description for detailed
information.
Bit 4 – S: Sign Flag, S = N ㊉ V
The S-bit is always an exclusive or between the Negative Flag N
and the Two’s Complement OverflowFlag V. See the Instruction Set
Description for detailed information.
Bit 3 – V: Two’s Complement Overflow FlagThe Two’s Complement
Overflow Flag V supports two’s complement arithmetic. See the
Instruction SetDescription for detailed information.
Bit 2 – N: Negative FlagThe Negative Flag N indicates a negative
result in an arithmetic or logic operation. See the Instruction
SetDescription for detailed information.
Bit 1 – Z: Zero FlagThe Zero Flag Z indicates a zero result in
an arithmetic or logic operation. See the Instruction
SetDescription for detailed information.
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Bit 0 – C: Carry FlagThe Carry Flag C indicates a carry in an
arithmetic or logic operation. See the Instruction Set
Descriptionfor detailed information.
11.4. General Purpose Register FileThe Register File is
optimized for the AVR Enhanced RISC instruction set. In order to
achieve therequired performance and flexibility, the following
input/output schemes are supported by the RegisterFile:
• One 8-bit output operand and one 8-bit result input• Two 8-bit
output operands and one 8-bit result input• Two 8-bit output
operands and one 16-bit result input• One 16-bit output operand and
one 16-bit result input
Figure 11-2. AVR CPU General Purpose Working Registers7 0
Addr.
R0 0x00
R1 0x01
R2 0x02
…
R13 0x0D
Genera l R14 0x0E
Purpose R15 0x0F
Working R16 0x10
Regis ters R17 0x11
…
R26 0x1A X-regis te r Low Byte
R27 0x1B X-regis te r High Byte
R28 0x1C Y-regis te r Low Byte
R29 0x1D Y-regis te r High Byte
R30 0x1E Z-regis te r Low Byte
R31 0x1F Z-regis te r High Byte
Most of the instructions operating on the Register File have
direct access to all registers, and most ofthem are single cycle
instructions. As shown in the figure, each register is also
assigned a data memoryaddress, mapping them directly into the first
32 locations of the user Data Space. Although not beingphysically
implemented as SRAM locations, this memory organization provides
great flexibility in accessof the registers, as the X-, Y-, and
Z-pointer registers can be set to index any register in the
file.
11.4.1. The X-register, Y-register, and Z-registerThe registers
R26...R31 have some added functions to their general purpose usage.
These registers are16-bit address pointers for indirect addressing
of the data space. The three indirect address registers X,Y, and Z
are defined as described in the figure.
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Figure 11-3. The X-, Y-, and Z-registers15 XH XL 0
X-register 7 0 7 0
R27 R26
15 YH YL 0
Y-register 7 0 7 0
R29 R28
15 ZH ZL 0
Z-register 7 0 7 0
R31 R30
In the different addressing modes these address registers have
functions as fixed displacement,automatic increment, and automatic
decrement (see the instruction set reference for details).
Related LinksInstruction Set Summary on page 432
11.5. Stack PointerThe Stack is mainly used for storing
temporary data, for storing local variables and for storing
returnaddresses after interrupts and subroutine calls. The Stack is
implemented as growing from higher tolower memory locations. The
Stack Pointer Register always points to the top of the Stack.
The Stack Pointer points to the data SRAM Stack area where the
Subroutine and Interrupt Stacks arelocated. A Stack PUSH command
will decrease the Stack Pointer. The Stack in the data SRAM must
bedefined by the program before any subroutine calls are executed
or interrupts are enabled. Initial StackPointer value equals the
last address of the internal SRAM and the Stack Pointer must be set
to pointabove start of the SRAM. See the table for Stack Pointer
details.
Table 11-1. Stack Pointer Instructions
Instruction Stack pointer Description
PUSH Decremented by 1 Data is pushed onto the stack
CALL
ICALL
RCALL
Decremented by 2 Return address is pushed onto the stack with a
subroutine call orinterrupt
POP Incremented by 1 Data is popped from the stack
RET
RETI
Incremented by 2 Return address is popped from the stack with
return from subroutine orreturn from interrupt
The AVR Stack Pointer is implemented as two 8-bit registers in
the I/O space. The number of bits actuallyused is implementation
dependent. Note that the data space in some implementations of the
AVRarchitecture is so small that only SPL is needed. In this case,
the SPH Register will not be present.
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11.5.1. Stack Pointer Register High byteWhen using the I/O
specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be
used. Whenaddressing I/O Registers as data space using LD and ST
instructions, 0x20 must be added to these offsetaddresses.
Name: SPHOffset: 0x5EReset: RAMENDProperty:
When addressing I/O Registers as data space the offset address
is 0x3E
Bit 7 6 5 4 3 2 1 0 (SP[10:8]) SPH
Access RW RW RW Reset 0 0 0
Bits 2:0 – (SP[10:8]) SPH: Stack Pointer RegisterSPH and SPL are
combined into SP. It means SPH[2:0] is SP[10:8].
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11.5.2. Stack Pointer Register Low byteWhen using the I/O
specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be
used. Whenaddressing I/O Registers as data space using LD and ST
instructions, 0x20 must be added to these offsetaddresses.
Name: SPLOffset: 0x5DReset: 0x11111111Property:
When addressing I/O Registers as data space the offset address
is 0x3D
Bit 7 6 5 4 3 2 1 0 (SP[7:0]) SPL
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 1
Bits 7:0 – (SP[7:0]) SPL: Stack Pointer RegisterSPH and SPL are
combined into SP. It means SPL[7:0] is SP[7:0].
11.6. Instruction Execution TimingThis section describes the
general access timing concepts for instruction execution. The AVR
CPU isdriven by the CPU clock clkCPU, directly generated from the
selected clock source for the chip. No internalclock division is
used. The Figure below shows the parallel instruction fetches and
instruction executionsenabled by the Harvard architecture and the
fast-access Register File concept. This is the basic
pipeliningconcept to obtain up to 1 MIPS per MHz with the
corresponding unique results for functions per cost,functions per
clocks, and functions per power-unit.
Figure 11-4. The Parallel Instruction Fetches and Instruction
Executions
clk
1st Instruction Fetch1st Instruction Execute
2nd Instruction Fetch2nd Instruction Execute
3rd Instruction Fetch3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
CPU
The following Figure shows the internal timing concept for the
Register File. In a single clock cycle anALU operation using two
register operands is executed, and the result is stored back to the
destinationregister.
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Figure 11-5. Single Cycle ALU Operation
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
clkCPU
11.7. Reset and Interrupt HandlingThe AVR provides several
different interrupt sources. These interrupts and the separate
Reset Vectoreach have a separate program vector in the program
memory space. All interrupts are assigned individualenable bits
which must be written logic one together with the Global Interrupt
Enable bit in the StatusRegister in order to enable the interrupt.
Depending on the Program Counter value, interrupts may
beautomatically disabled when Boot Lock bits BLB02 or BLB12 are
programmed. This feature improvessoftware security.
The lowest addresses in the program memory space are by default
defined as the Reset and InterruptVectors. They have determined
priority levels: The lower the address the higher is the priority
level.RESET has the highest priority, and next is INT0 – the
External Interrupt Request 0. The Interrupt Vectorscan be moved to
the start of the Boot Flash section by setting the IVSEL bit in the
MCU Control Register(MCUCR). The Reset Vector can also be moved to
the start of the Boot Flash section by programmingthe BOOTRST
Fuse.
When an interrupt occurs, the Global Interrupt Enable I-bit is
cleared and all interrupts are disabled. Theuser software can write
logic one to the I-bit to enable nested interrupts. All enabled
interrupts can theninterrupt the current interrupt routine. The
I-bit is automatically set when a Return from Interruptinstruction
– RETI – is executed.
There are basically two types of interrupts:
The first type is triggered by an event that sets the Interrupt
Flag. For these interrupts, the ProgramCounter is vectored to the
actual Interrupt Vector in order to execute the interrupt handling
routine, andhardware clears the corresponding Interrupt Flag.
Interrupt Flags can also be cleared by writing a logicone to the
flag bit position(s) to be cleared. If an interrupt condition
occurs while the correspondinginterrupt enable bit is cleared, the
Interrupt Flag will be set and remembered until the interrupt is
enabled,or the flag is cleared by software. Similarly, if one or
more interrupt conditions occur while the GlobalInterrupt Enable
bit is cleared, the corresponding Interrupt Flag(s) will be set and
remembered until theGlobal Interrupt Enable bit is set, and will
then be executed by order of priority.
The second type of interrupts will trigger as long as the
interrupt condition is present. These interrupts donot necessarily
have Interrupt Flags. If the interrupt condition disappears before
the interrupt is enabled,the interrupt will not be triggered. When
the AVR exits from an interrupt, it will always return to the
mainprogram and execute one more instruction before any pending
interrupt is served.
The Status Register is not automatically stored when entering an
interrupt routine, nor restored whenreturning from an interrupt
routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the
interrupts will be immediately disabled. Nointerrupt will be
executed after the CLI instruction, even if it occurs
simultaneously with the CLI instruction.
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The following example shows how this can be used to avoid
interrupts during the timed EEPROM writesequence.
Assembly Code Example
in r16, SREG ; store SREG valuecli ; disable interrupts during
timed sequencesbi EECR, EEMPE ; start EEPROM writesbi EECR, EEPEout
SREG, r16 ; restore SREG value (I-bit)
C Code Example
char cSREG;cSREG = SREG; /* store SREG value *//* disable
interrupts during timed sequence */_CLI();EECR |= (1
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12. AVR Memories
12.1. OverviewThis section describes the different memory types
in the device. The AVR architecture has two mainmemory spaces, the
Data Memory and the Program Memory space. In addition, the device
features anEEPROM Memory for data storage. All memory spaces are
linear and regular.
12.2. In-System Reprogrammable Flash Program MemoryThe
ATmega328/P contains 32Kbytes On-chip In-System Reprogrammable
Flash memory for programstorage. Since all AVR instructions are 16
or 32 bits wide, the Flash is organized as 16K x 16. Forsoftware
security, the Flash Program memory space is divided into two
sections - Boot Loader Sectionand Application Program Section in
the device .
The Flash memory has an endurance of at least 10,000 write/erase
cycles. The ATmega328/P ProgramCounter (PC) is 14 bits wide, thus
addressing the 16K program memory locations. The operation of
BootProgram section and associated Boot Lock bits for software
protection are described in detail in BootLoader Support –
Read-While-Write Self-Programming. Refer to Memory Programming for
the descriptionon Flash data serial downloading using the SPI
pins.
Constant tables can be allocated within the entire program
memory address space, using the LoadProgram Memory (LPM)
instruction.
Timing diagrams for instruction fetch and execution are
presented in Instruction Exectution Timing.
Figure 12-1. Program Memory Map ATmega328/P
0x0000
0x3FFF
Program Memory
Application Flash Section
Boot Flash Section
Related LinksBTLDR - Boot Loader Support – Read-While-Write
Self-Programming on page 330MEMPROG- Memory Programming on page
347Instruction Execution Timing on page 31
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12.3. SRAM Data MemoryThe following figure shows how the device
SRAM Memory is organized.
The device is a complex microcontroller with more peripheral
units than can be supported within the 64locations reserved in the
Opcode for the IN and OUT instructions. For the Extended I/O space
from 0x60- 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD
instructions can be used.
The lower 2303 data memory locations address both the Register
File, the I/O memory, Extended I/Omemory, and the internal data
SRAM. The first 32 locations address the Register File, the next
64location the standard I/O memory, then 160 locations of Extended
I/O memory, and the next 2K locationsaddress the internal data
SRAM.
The five different addressing modes for the data memory cover:•
Direct
– The direct addressing reaches the entire data space.• Indirect
with Displacement
– The Indirect with Displacement mode reaches 63 address
locations from the base addressgiven by the Y- or Z-register.
• Indirect– In the Register File, registers R26 to R31 feature
the indirect addressing pointer registers.
• Indirect with Pre-decrement– The address registers X, Y, and Z
are decremented.
• Indirect with Post-increment– The address registers X, Y, and
Z are incremented.
The 32 general purpose working registers, 64 I/O Registers, 160
Extended I/O Registers, and the 2Kbytes of internal data SRAM in
the device are all accessible through all these addressing
modes.
Figure 12-2. Data Memory Map with 2048 byte internal data
SRAM
(2048x8)
0x08FF12.3.1. Data Memory Access Times
The internal data SRAM access is performed in two clkCPU cycles
as described in the following Figure.
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Figure 12-3. On-chip Data SRAM Access Cycles
clk
WR
RD
Data
Data
Address Address valid
T1 T2 T3
Compute Address
Rea
dW
rite
CPU
Memory Access Instruction Next Instruction
12.4. EEPROM Data MemoryThe ATmega328/P contains 1K bytes of
data EEPROM memory. It is organized as a separate dataspace, in
which single bytes can be read and written. The EEPROM has an
endurance of at least100,000 write/erase cycles. The access between
the EEPROM and the CPU is described in the following,specifying the
EEPROM Address Registers, the EEPROM Data Register, and the EEPROM
ControlRegister.
See the related links for a detailed description on EEPROM
Programming in SPI or Parallel Programmingmode.
Related LinksMEMPROG- Memory Programming on page 347
12.4.1. EEPROM Read/Write AccessThe EEPROM Access Registers are
accessible in the I/O space.
The write access time for the EEPROM is given in Table 12-2. A
self-timing function, however, lets theuser software detect when
the next byte can be written. If the user code contains
instructions that writethe EEPROM, some precautions must be taken.
In heavily filtered power supplies, VCC is likely to rise orfall
slowly on power-up/down. This causes the device for some period of
time to run at a voltage lowerthan specified as minimum for the
clock frequency used. Please refer to Preventing EEPROM
Corruptionfor details on how to avoid problems in these
situations.
In order to prevent unintentional EEPROM writes, a specific
write procedure must be followed. Refer tothe description of the
EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles
before the next instruction isexecuted. When the EEPROM is written,
the CPU is halted for two clock cycles before the next
instructionis executed.
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12.4.2. Preventing EEPROM CorruptionDuring periods of low VCC,
the EEPROM data can be corrupted because the supply voltage is too
low forthe CPU and the EEPROM to operate properly. These issues are
the same as for board level systemsusing EEPROM, and the same
design solutions should be applied.
An EEPROM data corruption can be caused by two situations when
the voltage is too low. First, a regularwrite sequence to the
EEPROM requires a minimum voltage to operate correctly. Secondly,
the CPU itselfcan execute instructions incorrectly, if the supply
voltage is too low.
EEPROM data corruption can easily be avoided by following this
design recommendation:
Keep the AVR RESET active (low) during periods of insufficient
power supply voltage. This can be doneby enabling the internal
Brown-out Detector (BOD). If the detection level of the internal
BOD does notmatch the needed detection level, an external low VCC
reset Protection circuit can be used. If a resetoccurs while a
write operation is in progress, the write operation will be
completed provided that thepower supply voltage is sufficient.
12.5. I/O MemoryThe I/O space definition of the device is shown
in the Register Summary.
All device I/Os and peripherals are placed in the I/O space. All
I/O locations may be accessed by theLD/LDS/LDD and ST/STS/STD
instructions, transferring data between the 32 general purpose
workingregisters and the I/O space. I/O Registers within the
address range 0x00-0x1F are directly bit-accessibleusing the SBI
and CBI instructions. In these registers, the value of single bits
can be checked by usingthe SBIS and SBIC instructions.
When using the I/O specific commands IN and OUT, the I/O
addresses 0x00-0x3F must be used. Whenaddressing I/O Registers as
data space using LD and ST instructions, 0x20 must be added to
theseaddresses. The device is a complex microcontroller with more
peripheral units than can be supportedwithin the 64 location
reserved in Opcode for the IN and OUT instructions. For the
Extended I/O spacefrom 0x60..0xFF in SRAM, only the ST/STS/STD and
LD/LDS/LDD instructions can be used.
For compatibility with future devices, reserved bits should be
written to zero if accessed. Reserved I/Omemory addresses should
never be written.
Some of the Status Flags are cleared by writing a '1' to them;
this is described in the flag descriptions.Note that, unlike most
other AVRs, the CBI and SBI instructions will only operate on the
specified bit, andcan therefore be used on registers containing
such Status Flags. The CBI and SBI instructions work withregisters
0x00-0x1F only.
The I/O and Peripherals Control Registers are explained in later
sections.
Related LinksMEMPROG- Memory Programming on page 347Register
Summary on page 428Instruction Set Summary on page 432
12.5.1. General Purpose I/O RegistersThe device contains three
General Purpose I/O Registers, General Purpose I/O Register 0/1/2
(GPIOR0/1/2). These registers can be used for storing any
information, and they are particularly useful for storingglobal
variables and Status Flags. General Purpose I/O Registers within
the address range 0x00 - 0x1Fare directly bit-accessible using the
SBI, CBI, SBIS, and SBIC instructions.
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12.6. Register Description
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12.6.1. EEPROM Address Register HighWhen addressing I/O
Registers as data space using LD and ST instructions, the provided
offset must beused. When using the I/O specific commands IN and
OUT, the offset is reduced by 0x20, resulting in anI/O address
offset within 0x00 - 0x3F.
Name: EEARHOffset: 0x42Reset: 0x0XProperty:
When addressing as I/O Register: address offset is 0x22
Bit 7 6 5 4 3 2 1 0 EEAR9 EEAR8
Access R/W R/W Reset x x
Bit 1 – EEAR9: EEPROM Address 9Refer to EEARL.
Bit 0 – EEAR8: EEPROM Address 8Refer to EEARL.
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12.6.2. EEPROM Address Register LowWhen addressing I/O Registers
as data space using LD and ST instructions, the provided offset
must beused. When using the I/O specific commands IN and OUT, the
offset is reduced by 0x20, resulting in anI/O address offset within
0x00 - 0x3F.
Name: EEARLOffset: 0x41Reset: 0xXXProperty:
When addressing as I/O Register: address offset is 0x21
Bit 7 6 5 4 3 2 1 0 EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1
EEAR0
Access R/W R/W R/W R/W R/W R/W R/W R/W Reset x x x x x x x x
Bits 7:0 – EEARn: EEPROM AddressThe EEPROM Address Registers –
EEARH and EEARL specify the EEPROM address in the 1K BytesEEPROM
space. The EEPROM data bytes are addressed linearly between 0 and
255/511/511. The initialvalue of EEAR is undefined. A proper value
must be written before the EEPROM may be accessed.
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12.6.3. EEPROM Data RegisterWhen addressing I/O Registers as
data space using LD and ST instructions, the provided offset must
beused. When using the I/O specific commands IN and OUT, the offset
is reduced by 0x20, resulting in anI/O address offset within 0x00 -
0x3F.
Name: EEDROffset: 0x40Reset: 0x00Property:
When addressing as I/O Register: address offset is 0x20
Bit 7 6 5 4 3 2 1 0 EEDR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bits 7:0 – EEDR[7:0]: EEPROM DataFor the EEPROM write operation,
the EEDR Register contains the data to be written to the EEPROM
inthe address given by the EEAR Register. For the EEPROM read
operation, the EEDR contains the dataread out from the EEPROM at
the address given by EEAR.
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12.6.4. EEPROM Control RegisterWhen addressing I/O Registers as
data space using LD and ST instructions, the provided offset must
beused. When using the I/O specific commands IN and OUT, the offset
is reduced by 0x20, resulting in anI/O address offset within 0x00 -
0x3F.
Name: EECROffset: 0x3FReset: 0x00Property:
When addressing as I/O Register: address offset is 0x1F
Bit 7 6 5 4 3 2 1 0 EEPM1 EEPM0 EERIE EEMPE EEPE EERE
Access R/W R/W R/W R/W R/W R/W Reset x x 0 0 x 0
Bits 5:4 – EEPMn: EEPROM Programming Mode Bits [n = 1:0]The
EEPROM Programming mode bit setting defines which programming
action that will be triggeredwhen writing EEPE. It is possible to
program data in one atomic operation (erase the old value
andprogram the new value) or to split the Erase and Write
operations in two different operations. TheProgramming times for
the different modes are shown in the table below. While EEPE is
set, any write toEEPMn will be ignored. During reset, the EEPMn
bits will be reset to 0b00 unless the EEPROM is
busyprogramming.
Table 12-1. EEPROM Mode Bits
EEPM[1:0] Programming Time Operation
00 3.4ms Erase and Write in one operation (Atomic Operation)
01 1.8ms Erase Only
10 1.8ms Write Only
11 - Reserved for future use
Bit 3 – EERIE: EEPROM Ready Interrupt EnableWriting EERIE to one
enables the EEPROM Ready Interrupt if the I bit in SREG is set.
Writing EERIE tozero disables the interrupt. The EEPROM Ready
interrupt generates a constant interrupt when EEPE iscleared. The
interrupt will not be generated during EEPROM write or SPM.
Bit 2 – EEMPE: EEPROM Master Write EnableThe EEMPE bit
determines whether writing EEPE to '1' causes the EEPROM to be
written.When EEMPE is '1', setting EEPE within four clock cycles
will write data to the EEPROM at the selectedaddress.
If EEMPE is zero, setting EEPE will have no effect. When EEMPE
has been written to '1' by software,hardware clears the bit to zero
after four clock cycles. See the description of the EEPE bit for
anEEPROM write procedure.
Bit 1 – EEPE: EEPROM Write EnableThe EEPROM Write Enable Signal
EEPE is the write strobe to the EEPROM. When address and data
arecorrectly set up, the EEPE bit must be written to '1' to write
the value into the EEPROM. The EEMPE bit
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must be written to '1' before EEPE is written to '1', otherwise
no EEPROM write takes place. The followingprocedure should be
followed when writing the EEPROM (the order of steps 3 and 4 is not
essential):
1. Wait until EEPE becomes zero.2. Wait until SPMEN in SPMCSR
becomes zero.3. Write new EEPROM address to EEAR (optional).4.
Write new EEPROM data to EEDR (optional).5. Write a '1' to the
EEMPE bit while writing a zero to EEPE in EECR.6. Within four clock
cycles after setting EEMPE, write a '1' to EEPE.
The EEPROM can not be pro