Intel StrongARM SA-1110 Microprocessor · SA-1110 Developer’s Manual Information in this document is provided in connection with Intel products. No license, express or implied,

Intel® StrongARM* SA-1110MicroprocessorDeveloper’s Manual

October 2001

Order Number: 278240-004

Notice: Verify with your local Intel sales office that you have the latest technical information beforefinalizing a design.

SA-1110 Developer’s Manual

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectualproperty rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liabilitywhatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating tofitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are notintended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these forfuture definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The SA-1110 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Currentcharacterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

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Copyright © Intel Corporation, 2001

*Other names and brands may be claimed as the property of others.

Contents

1 Introduction

1.1 Intel® StrongARM SA-1110 Microprocessor ..............................................................................211.2 Overview .....................................................................................................................................241.3 Example System .........................................................................................................................251.4 ARM Architecture ........................................................................................................................26

1.4.1 26-Bit Mode ....................................................................................................................261.4.2 Coprocessors .................................................................................................................261.4.3 Memory Management.....................................................................................................261.4.4 Instruction Cache............................................................................................................261.4.5 Data Cache.....................................................................................................................261.4.6 Write Buffer.....................................................................................................................271.4.7 Read Buffer ....................................................................................................................27

2 Functional Description

2.1 Block Diagram.............................................................................................................................292.2 Inputs/Outputs.............................................................................................................................312.3 Signal Description .......................................................................................................................322.4 Memory Map ...............................................................................................................................36

3 ARM Implementation Options

3.1 Big and Little Endian ...................................................................................................................393.2 Exceptions...................................................................................................................................39

3.2.1 Power-Up Reset .............................................................................................................403.2.2 ROM Size Select ............................................................................................................403.2.3 Abort ...............................................................................................................................413.2.4 Vector Summary.............................................................................................................423.2.5 Exception Priorities.........................................................................................................423.2.6 Interrupt Latencies and Enable Timing...........................................................................43

3.3 Coprocessors ..............................................................................................................................43

4 Instruction Set

4.1 Instruction Set .............................................................................................................................454.2 Instruction Timing........................................................................................................................45

5 Caches, Write Buffer, and Read Buffer

5.1 Instruction Cache (Icache) ..........................................................................................................475.1.1 Icache Operation ............................................................................................................475.1.2 Icache Validity ................................................................................................................47

5.1.2.1 Software Icache Flush..................................................................................... 475.1.3 Icache Enable/Disable and Reset ..................................................................................48

5.1.3.1 Enabling the Icache......................................................................................... 485.1.3.2 Disabling the Icache........................................................................................ 48

5.2 Data Caches (Dcaches) ..............................................................................................................485.2.1 Cacheable Bit – C...........................................................................................................49

5.2.1.1 Cacheable Reads – C = 1............................................................................... 49

SA-1110 Developer’s Manual 3

5.2.1.2 Noncacheable Reads – C = 0..........................................................................495.2.2 Bufferable Bit – B ........................................................................................................... 495.2.3 Software Dcache Flush .................................................................................................. 50

5.2.3.1 Doubly Mapped Space.....................................................................................505.2.4 Dcaches Enable/Disable and Reset...............................................................................50

5.2.4.1 Enabling the Dcaches ......................................................................................515.2.4.2 Disabling the Dcaches .....................................................................................51

5.3 Write Buffer (WB)........................................................................................................................ 515.3.1 Bufferable Bit.................................................................................................................. 515.3.2 Write Buffer Operation.................................................................................................... 51

5.3.2.1 Writes to a Bufferable and Cacheable Location (B=1,C=1) .............................515.3.2.2 Writes to a Bufferable and Noncacheable Location (B=1,C=0) .......................525.3.2.3 Unbufferable and Noncacheable Writes (B=0, C=0)........................................525.3.2.4 Writes to a Non-Bufferable and Cacheable Location (B=0, C=1) ....................52

5.3.3 Enabling the Write Buffer ............................................................................................... 525.3.3.1 Disabling the Write Buffer ................................................................................52

5.4 Read Buffer (RB) ........................................................................................................................ 52

6 Coprocessors

6.1 Internal Coprocessor Instructions ............................................................................................... 556.2 Coprocessor 15 Definition........................................................................................................... 56

6.2.1 Register 0 – ID ............................................................................................................... 566.2.2 Register 1 – Control ....................................................................................................... 576.2.3 Register 2 – Translation Table Base .............................................................................. 586.2.4 Register 3 – Domain Access Control ............................................................................. 586.2.5 Register 4 – RESERVED ............................................................................................... 596.2.6 Register 5 – Fault Status................................................................................................ 596.2.7 Register 6 – Fault Address............................................................................................. 596.2.8 Register 7 – Cache Control Operations .........................................................................596.2.9 Register 8 – TLB Operations.......................................................................................... 606.2.10 Register 9 – Read-Buffer Operations ............................................................................. 606.2.11 Registers 10 – 12 RESERVED ......................................................................................616.2.12 Register 13 – Process ID Virtual Address Mapping ....................................................... 616.2.13 Register 14 – Debug Support (Breakpoints) ..................................................................626.2.14 Register 15 – Test, Clock, and Idle Control.................................................................... 63

7 Memory Management Unit (MMU)

7.1 Overview ..................................................................................................................................... 657.1.1 MMU Registers............................................................................................................... 65

7.2 MMU Faults and CPU Aborts...................................................................................................... 657.3 Data Aborts ................................................................................................................................. 65

7.3.1 Cacheable Reads (Linefetches) ..................................................................................... 667.3.2 Buffered Writes............................................................................................................... 66

7.4 Interaction of the MMU, Icache, Dcache, and Write Buffer......................................................... 667.5 Mini Data Cache ......................................................................................................................... 67

8 Clocks

8.1 Intel® StrongARM SA-1110 Crystal Oscillators .......................................................................... 698.2 Core Clock Configuration Register ............................................................................................. 70

8.2.1 Restrictions on Changing the Core Clock Configuration ................................................ 71

4 SA-1110 Developer’s Manual

8.3 Driving Intel® StrongARM SA-1110 Crystal Pins from an External Source ................................718.4 Clocking During Test...................................................................................................................72

9 System Control Module

9.1 General-Purpose I/O...................................................................................................................739.1.1 GPIO Register Definitions ..............................................................................................74

9.1.1.1 GPIO Pin-Level Register (GPLR).................................................................... 759.1.1.2 GPIO Pin Direction Register (GPDR).............................................................. 769.1.1.3 GPIO Pin Output Set Register (GPSR) and Pin Output

Clear Register (GPCR) ................................................................................... 779.1.1.4 GPIO Rising-Edge Detect Register (GRER) and

Falling-Edge Detect Register (GFER)............................................................. 789.1.1.5 GPIO Edge Detect Status Register (GEDR) ................................................... 799.1.1.6 GPIO Alternate Function Register (GAFR) ..................................................... 80

9.1.2 GPIO Alternate Functions...............................................................................................819.1.2.1 3.6864 MHz Option for GP 27 Alternate Output Function............................... 82

9.1.3 GPIO Register Locations................................................................................................829.2 Interrupt Controller ......................................................................................................................83

9.2.1 Interrupt Controller Register Definitions .........................................................................849.2.1.1 Interrupt Controller Pending Register (ICPR).................................................. 849.2.1.2 Interrupt Controller IRQ Pending Register (ICIP) and

FIQ Pending Register (ICFP) .......................................................................... 869.2.1.3 Interrupt Controller Mask Register (ICMR)...................................................... 879.2.1.4 Interrupt Controller Level Register (ICLR)....................................................... 889.2.1.5 Interrupt Controller Control Register (ICCR) ................................................... 89

9.2.2 Interrupt Controller Register Locations...........................................................................909.3 Real-Time Clock..........................................................................................................................90

9.3.1 RTC Counter Register (RCNR) ......................................................................................909.3.2 RTC Alarm Register (RTAR) ..........................................................................................919.3.3 RTC Status Register (RTSR) .........................................................................................919.3.4 RTC Trim Register (RTTR).............................................................................................939.3.5 Trim Procedure...............................................................................................................93

9.3.5.1 Oscillator Frequency Calibration ..................................................................... 939.3.5.2 RTTR Value Calculations................................................................................ 94

9.3.6 Real-Time Clock Register Locations ..............................................................................959.4 Operating System Timer .............................................................................................................95

9.4.1 OS Timer Count Register (OSCR) .................................................................................969.4.2 OS Timer Match Registers 0–3 (OSMR 0, OSMR 1, OSMR 2, OSMR 3)......................969.4.3 OS Timer Watchdog Match Enable Register (OWER) ...................................................969.4.4 OS Timer Status Register (OSSR) .................................................................................979.4.5 OS Timer Interrupt Enable Register (OIER) ...................................................................989.4.6 Watchdog Timer .............................................................................................................989.4.7 OS Timer Register Locations .........................................................................................99

9.5 Power Manager..........................................................................................................................999.5.1 Run Mode.......................................................................................................................999.5.2 Idle Mode........................................................................................................................99

9.5.2.1 Entering Idle Mode........................................................................................ 1009.5.2.2 Exiting Idle Mode........................................................................................... 100

9.5.3 Sleep Mode ..................................................................................................................101


9.5.3.1 CPU Preparation for Sleep Mode ..................................................................1019.5.3.2 Events Causing Entry into Sleep Mode .........................................................1019.5.3.3 The Sleep Shutdown Sequence ....................................................................1019.5.3.4 During Sleep Mode ........................................................................................1029.5.3.5 The Sleep Wake-Up Sequence .....................................................................1039.5.3.6 Booting After Sleep Mode ..............................................................................1039.5.3.7 Reviving the DRAMs from Self-Refresh Mode...............................................104

9.5.4 Notes on Power Supply Sequencing............................................................................ 1049.5.5 Assumed Behavior of an Intel® StrongARM SA-1110 System in Sleep Mode ............ 1049.5.6 Pin Operation in Sleep Mode ....................................................................................... 1069.5.7 Power Manager Registers............................................................................................ 107

9.5.7.1 Power Manager Control Register (PMCR).....................................................1079.5.7.2 Power Manager General Configuration Register (PCFR)..............................1089.5.7.3 Power Manager PLL Configuration Register (PPCR) ....................................1109.5.7.4 Power Manager Wake-Up Enable Register (PWER).....................................1109.5.7.5 Power Manager Sleep Status Register (PSSR).............................................1119.5.7.6 Power Manager Scratch Pad Register (PSPR) .............................................1139.5.7.7 Power Manager GPIO Sleep State Register (PGSR) ....................................1139.5.7.8 Power Manager Oscillator Status Register (POSR) ......................................114

9.5.8 Power Manager Register Locations .............................................................................1149.6 Reset Controller ........................................................................................................................ 115

9.6.1 Reset Controller Registers ........................................................................................... 1159.6.1.1 Reset Controller Software Reset Register (RSRR) .......................................1159.6.1.2 Reset Controller Status Register (RCSR)......................................................116

9.6.2 Reset Controller Register Locations.............................................................................117

10 Memory and PC-Card Control Module

10.1Overview of Operation ..............................................................................................................12010.1.1 Types of Memory Accesses ......................................................................................... 12210.1.2 Reads ........................................................................................................................... 12210.1.3 Writes ........................................................................................................................... 12310.1.4 Transaction Summary .................................................................................................. 12310.1.5 Read-Lock-Write .......................................................................................................... 12310.1.6 Aborts and Nonexistent Memory .................................................................................. 124

10.2Memory Interface Reset and Initialization................................................................................. 12410.2.1 Hardware or Sleep Reset Procedures.......................................................................... 12510.2.2 Software or Watchdog Reset Procedures .................................................................... 126

10.3Memory Configuration Registers .............................................................................................. 12710.3.1 DRAM Configuration Register (MDCNFG)................................................................... 12810.3.2 DRAM Refresh Control Register (MDREFR) ............................................................... 13210.3.3 CAS Waveform Rotate Registers (MDCAS00, MDCAS01, MDCAS02,

MDCAS20, MDCAS21, MDCAS22) .............................................................................13610.3.3.1 MDCAS Registers with Asynchronous DRAM ...............................................13610.3.3.2 MDCAS Registers with SDRAM and SMROM...............................................137

10.3.4 Static Memory Control Registers (MSC2 – 0) .............................................................. 13910.3.5 Expansion Memory (PC-Card) Configuration Register (MECR) .................................. 142

10.4SMROM Configuration Register (SMCNFG) ............................................................................ 14410.4.1 Changing SMROM RAS Latency ................................................................................. 147

10.5Dynamic Interface Operation .................................................................................................... 148


10.5.1 DRAM Overview...........................................................................................................14810.5.2 DRAM Timing ...............................................................................................................15010.5.3 SDRAM Overview.........................................................................................................15210.5.4 SDRAM Commands .....................................................................................................15410.5.5 SDRAM State Machine.................................................................................................15510.5.6 DRAM/SDRAM Refresh ...............................................................................................16010.5.7 DRAM/SDRAM Self-Refresh in Sleep Mode ................................................................161

10.6Static Memory Interface ............................................................................................................16210.6.1 ROM Interface Overview ..............................................................................................16310.6.2 ROM Timing Diagrams and Parameters ......................................................................16310.6.3 SRAM Interface Overview ............................................................................................16710.6.4 SRAM Timing Diagrams and Parameters ....................................................................16710.6.5 Variable Latency I/O Interface Overview......................................................................16910.6.6 Variable Latency I/O Timing Diagrams and Parameters ..............................................16910.6.7 FLASH Memory Interface Overview .............................................................................17210.6.8 FLASH Memory Timing Diagrams and Parameters .....................................................17210.6.9 SMROM Overview........................................................................................................17310.6.10 SMROM Commands ....................................................................................................17310.6.11 SMROM State Machine................................................................................................174

10.7PC-Card Overview ....................................................................................................................17710.7.1 8-, 16-, and 32-Bit Data Bus Operation ........................................................................17910.7.2 External Logic for PC-Card Implementation .................................................................18010.7.3 PC-Card Interface Timing Diagrams and Parameters..................................................183

10.8Alternate Memory Bus Master Mode.........................................................................................18510.9Memory System Examples .......................................................................................................18610.10SA1110 Memory Configuration Tool .......................................................................................190

11 Peripheral Control Module

11.1Read/Write Interface .................................................................................................................20511.2Memory Organization................................................................................................................20611.3Interrupts ...................................................................................................................................20711.4Peripheral Pins..........................................................................................................................20811.5Use of the GPIO Pins for Alternate Functions...........................................................................20911.6DMA Controller..........................................................................................................................210

11.6.1 DMA Register Definitions .............................................................................................21111.6.1.1 DMA Device Address Register (DDARn) ...................................................... 21111.6.1.2 DMA Control/Status Register (DCSRn) ........................................................ 21311.6.1.3 DMA Buffer A Start Address Register (DBSAn)............................................ 21511.6.1.4 DMA Buffer A Transfer Count Register (DBTAn).......................................... 21611.6.1.5 DMA Buffer B Start Address Register (DBSBn)............................................ 21611.6.1.6 DMA Buffer B Transfer Count Register (DBTBn).......................................... 216

11.6.2 DMA Register List.........................................................................................................21711.7LCD Controller ..........................................................................................................................219

11.7.1 LCD Controller Operation .............................................................................................22011.7.1.1 DMA to Memory Interface ............................................................................. 22111.7.1.2 Frame Buffer ................................................................................................. 22111.7.1.3 Input FIFO..................................................................................................... 22611.7.1.4 Lookup Palette .............................................................................................. 22611.7.1.5 Color/Gray-Scale Dithering ........................................................................... 226


11.7.1.6 Output FIFO...................................................................................................22711.7.1.7 LCD Controller Pins .......................................................................................227

11.7.2 LCD Controller Register Definitions .............................................................................22811.7.3 LCD Controller Control Register 0................................................................................ 229

11.7.3.1 LCD Enable (LEN) .........................................................................................22911.7.3.2 Color/Monochrome Select (CMS) ..................................................................22911.7.3.3 Single-/Dual-Panel Select (SDS) ...................................................................22911.7.3.4 LCD Disable Done Interrupt Mask (LDM) ......................................................23111.7.3.5 Base Address Update Interrupt Mask (BAM).................................................23211.7.3.6 Error Interrupt Mask (ERM)............................................................................23211.7.3.7 Passive/Active Display Select (PAS) .............................................................23211.7.3.8 Big/Little Endian Select (BLE)........................................................................23311.7.3.9 Double-Pixel Data (DPD) Pin Mode...............................................................23411.7.3.10Vertical Slant Line Correction (VSC) .............................................................23411.7.3.11Palette DMA Request Delay (PDD)...............................................................234

11.7.4 LCD Controller Control Register 1................................................................................ 23611.7.4.1 Pixels Per Line (PPL).....................................................................................23711.7.4.2 Horizontal Sync Pulse Width (HSW)..............................................................23711.7.4.3 End-of-Line Pixel Clock Wait Count (ELW)....................................................23711.7.4.4 Beginning-of-Line Pixel Clock Wait Count (BLW) ..........................................237

11.7.5 LCD Controller Control Register 2................................................................................ 23811.7.5.1 Lines Per Panel (LPP) ...................................................................................23811.7.5.2 Vertical Sync Pulse Width (VSW) ..................................................................23911.7.5.3 End-of-Frame Line Clock Wait Count (EFW).................................................23911.7.5.4 Beginning-of-Frame Line Clock Wait Count (BFW) .......................................240

11.7.6 LCD Controller Control Register 3................................................................................ 24111.7.6.1 Pixel Clock Divider (PCD) ..............................................................................24211.7.6.2 AC Bias Pin Frequency (ACB) .......................................................................24211.7.6.3 AC Bias Pin Transitions Per Interrupt (API) ...................................................24211.7.6.4 Vertical Sync Polarity (VSP) ..........................................................................24311.7.6.5 Horizontal Sync Polarity (HSP) ......................................................................24311.7.6.6 Pixel Clock Polarity (PCP) .............................................................................24311.7.6.7 Output Enable Polarity (OEP) ........................................................................243

11.7.7 LCD Controller DMA Registers ....................................................................................24511.7.8 DMA Channel 1 Base Address Register ...................................................................... 24511.7.9 DMA Channel 1 Current Address Register .................................................................. 24611.7.10 DMA Channel 2 Base and Current Address Registers ................................................ 24711.7.11 LCD Controller Status Register ....................................................................................248

11.7.11.1 LCD Disable Done Flag (LDD) (read/write, maskable interrupt) ..................24911.7.11.2Base Address Update Flag (BAU) (read-only, maskable interrupt)...............24911.7.11.3 Bus Error Status (BER) (read/write, maskable interrupt) .............................24911.7.11.4 AC Bias Count Status (ABC) (read/write, nonmaskable interrupt) ...............24911.7.11.5 Input FIFO Overrun Lower Panel Status (IOL)

(read/write, maskable interrupt) .....................................................................24911.7.11.6 Input FIFO Underrun Lower Panel Status (IUL)

(read/write, maskable interrupt) .....................................................................25011.7.11.7 Input FIFO Overrun Upper Panel Status (IOU)


(read/write, maskable interrupt) .................................................................... 25011.7.11.8 Input FIFO Underrun Upper Panel Status (IUU)

(read/write, maskable interrupt) .................................................................... 25011.7.11.9 Output FIFO Overrun Lower Panel Status (OOL)

(read/write, maskable interrupt) .................................................................... 25011.7.11.10 Output FIFO Underrun Lower Panel Status (OUL)

(read only, maskable interrupt) ..................................................................... 25011.7.11.11 Output FIFO Overrun Upper Panel Status (OOU)

(read/write, maskable interrupt) .................................................................... 25011.7.11.12Output FIFO Underrun Upper Panel Status (OUU)

(read/write, maskable interrupt) .................................................................... 25111.7.12 LCD Controller Register Locations ...............................................................................25211.7.13 LCD Controller Pin Timing Diagrams ...........................................................................254

11.8Serial Port 0 – USB Device Controller (UDC) ...........................................................................25911.8.1 USB Operation .............................................................................................................261

11.8.1.1 Signalling Levels ........................................................................................... 26111.8.1.2 Connecting the USB to the SA-1110............................................................. 26211.8.1.3 Bit Encoding .................................................................................................. 26311.8.1.4 Field Formats ................................................................................................ 26411.8.1.5 Packet Types ................................................................................................ 26511.8.1.6 Transaction Formats ..................................................................................... 26711.8.1.7 SA-1110 UDC Device-Request Commands ................................................. 26911.8.1.8 Using DMA.................................................................................................... 27111.8.1.9 Software Control of the SA-1110 UDC.......................................................... 27111.8.1.10SA-1110 USB Example Code....................................................................... 278

11.8.2 SA-1110 UDC Register Definitions...............................................................................27811.8.3 UDC Control Register (UDCCR) ..................................................................................279

11.8.3.1 UDC Disable (UDD) ...................................................................................... 28011.8.3.2 UDC Active (UDA)......................................................................................... 28011.8.3.3 Resume Interrupt Mask (RESIM) .................................................................. 28011.8.3.4 Endpoint 0 Interrupt Mask (EIM) ................................................................... 28111.8.3.5 Receive Interrupt Mask (RIM) ....................................................................... 28111.8.3.6 Transmit Interrupt Mask (TIM)....................................................................... 28111.8.3.7 Suspend Interrupt Mask (SUSIM) ................................................................. 28211.8.3.8 Reserved/B5 ................................................................................................. 282

11.8.4 UDC Address Register (UDCAR) .................................................................................28211.8.5 UDC OUT Maximum Packet Register (UDCOMP).......................................................28311.8.6 UDC IN Maximum Packet Register (UDCIMP).............................................................28411.8.7 UDC Endpoint 0 Control/Status Register (UDCCS0) ...................................................284

11.8.7.1 OUT Packet Ready (OPR) ............................................................................ 28511.8.7.2 IN Packet Ready (IPR).................................................................................. 28511.8.7.3 Sent Stall (SST) ............................................................................................ 28611.8.7.4 Force Stall (FST)........................................................................................... 28611.8.7.5 Data End (DE)............................................................................................... 28611.8.7.6 Setup End (SE) ............................................................................................. 28611.8.7.7 Serviced OPR (SO)....................................................................................... 28611.8.7.8 Serviced Setup End (SSE)............................................................................ 286


11.8.8 UDC Endpoint 1 Control/Status Register (UDCCS1) ................................................... 28611.8.8.1 Receive FIFO Service (RFS) .........................................................................28711.8.8.2 Receive Packet Complete (RPC)...................................................................28711.8.8.3 Receive Packet Error (RPE) ..........................................................................28811.8.8.4 Sent Stall (SST) .............................................................................................28811.8.8.5 Force Stall (FST)............................................................................................28811.8.8.6 Receive FIFO Not Empty (RNE) ....................................................................288

11.8.9 UDC Endpoint 2 Control/Status Register (UDCCS2) ................................................... 28811.8.9.1 Transmit FIFO Service (TFS).........................................................................28911.8.9.2 Transmit Packet Complete (TPC) ..................................................................28911.8.9.3 Transmit Packet Error (TPE)..........................................................................28911.8.9.4 Transmit Underrun (TUR) ..............................................................................29011.8.9.5 Sent STALL (SST) .........................................................................................29011.8.9.6 Force STALL (FST)........................................................................................290

11.8.10 UDC Endpoint 0 Data Register (UDCD0)..................................................................... 29011.8.11 UDC Endpoint 0 Write Count Register (UDCWC)........................................................ 29111.8.12 UDC Data Register (UDCDR) ...................................................................................... 29211.8.13 UDC Status/Interrupt Register (UDCSR) ..................................................................... 292

11.8.13.1Endpoint 0 Interrupt Request (EIR) ...............................................................29311.8.13.2Receive Interrupt Request (RIR) ...................................................................29411.8.13.3Transmit Interrupt Request (TIR) ..................................................................29411.8.13.4Suspend Interrupt Request (SUSIR) .............................................................29411.8.13.5Resume Interrupt Request (RESIR)..............................................................29411.8.13.6 Reset Interrupt Request (RSTIR) .................................................................294

11.8.14 SA-1110 UDC Register Locations................................................................................ 29411.9Serial Port 1 – GPCLK/UART ................................................................................................... 295

11.9.1 GPCLK Operation ........................................................................................................ 29511.9.1.1 Simultaneous Use of the UART and GPCLK.................................................296

11.9.2 GPCLK Control Register 0 ........................................................................................... 29611.9.2.1 GPCLK/UART Select (SUS) ..........................................................................29611.9.2.2 Sample Clock Enable (SCE)..........................................................................29611.9.2.3 Sample Clock Direction (SCD).......................................................................296

11.9.3 GPCLK Control Register 1 ........................................................................................... 29711.9.3.1 Transmit Enable (TXE) ..................................................................................297

11.9.4 GPCLK Control Registers 2 and 3 ............................................................................... 29811.9.4.1 Baud Rate Divisor (BRD) ...............................................................................298

11.9.5 UART Register Locations............................................................................................. 29911.9.6 GPCLK Register Locations ..........................................................................................300

11.10 Serial Port 2 – Infrared Communications Port (ICP) .............................................................. 30011.10.1 Low-Speed ICP Operation ........................................................................................... 301

11.10.1.1HP-SIR Modulation........................................................................................30111.10.1.2UART Frame Format.....................................................................................302

11.10.2 High-Speed ICP Operation........................................................................................... 30211.10.2.14PPM Modulation ..........................................................................................30211.10.2.2HSSP Frame Format.....................................................................................30311.10.2.3Address Field ................................................................................................30411.10.2.4Control Field ..................................................................................................304


11.10.2.5Data Field ..................................................................................................... 30411.10.2.6CRC Field ..................................................................................................... 30411.10.2.7Baud Rate Generation.................................................................................. 30511.10.2.8Receive Operation........................................................................................ 30511.10.2.9Transmit Operation....................................................................................... 30611.10.2.10Transmit and Receive FIFOs...................................................................... 30711.10.2.11CPU and DMA Register Access Sizes ....................................................... 308

11.10.3 UART Register Definition .............................................................................................30811.10.4 UART Control Register 4..............................................................................................308

11.10.4.1HP-SIR Enable (HSE) .................................................................................. 30811.10.4.2Low-Power Mode (LPM)............................................................................... 308

11.10.5 HSSP Register Definitions30911.10.6 HSSP Control Register 0..............................................................................................309

11.10.6.1IrDA Transmission Rate (ITR) ...................................................................... 30911.10.6.2Loopback Mode (LBM) ................................................................................. 31011.10.6.3Transmit FIFO Underrun Select (TUS)......................................................... 31011.10.6.4Transmit Enable (TXE) ................................................................................. 31111.10.6.5Receive Enable (RXE).................................................................................. 31111.10.6.6Receive FIFO Interrupt Enable (RIE) ........................................................... 31111.10.6.7Transmit FIFO Interrupt Enable (TIE)........................................................... 31211.10.6.8Address Match Enable (AME) ...................................................................... 312

11.10.7 HSSP Control Register 1.............................................................................................31311.10.7.1Address Match Value (AMV) ........................................................................ 313

11.10.8 HSSP Control Register 2.............................................................................................31411.10.8.1Transmit Pin Polarity Select (TXP) ............................................................... 31411.10.8.2Receive Pin Polarity Select (RXP)................................................................ 315

11.10.9 HSSP Data Register....................................................................................................31611.10.10 HSSP Status Register 0.............................................................................................317

11.10.10.1 End/Error in FIFO Status (EIF) (read-only, nonmaskable interrupt) .......... 31811.10.10.2 Transmit Underrun Status (TUR) (read/write, maskable interrupt)............ 31811.10.10.3 Receiver Abort Status (RAB) (read/write, nonmaskable interrupt) ............ 31811.10.10.4 Transmit FIFO Service Request Flag (TFS)

(read-only, maskable interrupt) ..................................................................... 31811.10.10.5 Receive FIFO Service Request Flag (RFS)

(read-only, maskable interrupt) ..................................................................... 31911.10.10.6 Framing Error Status (FRE) (read/write, nonmaskable interrupt).............. 319

11.10.11 HSSP Status Register 1.............................................................................................32011.10.11.1 Receiver Synchronized Flag (RSY) (read-only, noninterruptible).............. 32111.10.11.2 Transmitter Busy Flag (TBY) (read-only, noninterruptible)........................ 32111.10.11.3 Receive FIFO Not Empty Flag (RNE) (read-only, noninterruptible) .......... 32111.10.11.4 Transmit FIFO Not Full Flag (TNF) (read-only, noninterruptible) .............. 32111.10.11.5 End-of-Frame Flag (EOF) (read-only, noninterruptible) ............................ 32111.10.11.6 CRC Error Flag (CRE) (read-only, noninterruptible).................................. 32111.10.11.7 Receiver Overrun Status (ROR) (read-only, noninterruptible)................... 322

11.10.12 UART Register Locations...........................................................................................32311.10.13 HSSP Register Locations...........................................................................................324

11.11Serial Port 3 – UART...............................................................................................................32511.11.1 UART Operation ...........................................................................................................325


11.11.1.1Frame Format................................................................................................32611.11.1.2Baud Rate Generation...................................................................................32611.11.1.3Receive Operation.........................................................................................32611.11.1.4Transmit Operation........................................................................................32711.11.1.5Transmit and Receive FIFOs ........................................................................32711.11.1.6CPU and DMA Register Access Sizes ..........................................................327

11.11.2 UART Register Definitions ........................................................................................... 32711.11.3 UART Control Register 0.............................................................................................. 328

11.11.3.1Parity Enable (PE).........................................................................................32811.11.3.2Odd/Even Parity Select (OES) ......................................................................32811.11.3.3Stop Bit Select (SBS) ....................................................................................32811.11.3.4Data Size Select (DSS) .................................................................................32911.11.3.5Sample Clock Enable (SCE) .........................................................................32911.11.3.6Receive Clock Edge Select (RCE) ................................................................32911.11.3.7Transmit Clock Edge Select (TCE) ...............................................................329

11.11.4 UART Control Registers 1 and 2.................................................................................. 33011.11.4.1Baud Rate Divisor (BRD) ..............................................................................330

11.11.5 UART Control Register 3.............................................................................................. 33111.11.5.1Receiver Enable (RXE) .................................................................................33211.11.5.2Transmitter Enable (TXE)..............................................................................33211.11.5.3Break (BRK) ..................................................................................................33211.11.5.4Receive FIFO Interrupt Enable (RIE) ............................................................33211.11.5.5Transmit FIFO Interrupt Enable (TIE)............................................................33311.11.5.6Loopback Mode (LBM) ..................................................................................333

11.11.6 UART Data Register..................................................................................................... 33411.11.7 UART Status Register 0 ............................................................................................... 335

11.11.7.1Transmit FIFO Service Request Flag (TFS) (read-only, maskable interrupt)33611.11.7.2Receive FIFO Service Request Flag (RFS) (read-only, maskable interrupt) 33611.11.7.3Receiver Idle Status (RID) (read/write, maskable interrupt)..........................33611.11.7.4Receiver Begin of Break Status (RBB) (read/write, nonmaskable interrupt).33711.11.7.5Receiver End of Break Status (REB) (read/write, nonmaskable interrupt)....33711.11.7.6Error in FIFO Flag (EIF) (read-only, nonmaskable interrupt) ........................337

11.11.8 UART Status Register 1 ............................................................................................... 33911.11.8.1Transmitter Busy Flag (TBY) (read-only, noninterruptible)............................33911.11.8.2Receive FIFO Not Empty Flag (RNE) (read-only, noninterruptible) ..............33911.11.8.3Transmit FIFO Not Full Flag (TNF) (read-only, noninterruptible) ..................33911.11.8.4Parity Error Flag (PRE) (read-only, noninterruptible) ....................................33911.11.8.5Framing Error Flag (FRE) (read-only, noninterruptible) ................................33911.11.8.6Receiver Overrun Flag (ROR) (read-only, noninterruptible)..........................340

11.11.9 UART Register Locations............................................................................................. 34111.12Serial Port 4 – MCP / SSP ...................................................................................................... 342

11.12.1 MCP Operation............................................................................................................. 34311.12.1.1Frame Format................................................................................................34311.12.1.2Audio and Telecom Sample Rates and Data Transfer..................................34511.12.1.3MCP Transmit and Receive FIFO Operation ................................................34611.12.1.4Codec Control Register Data Transfer ..........................................................34711.12.1.5External Clock Operation ..............................................................................348


11.12.1.6Alternate SSP Pin Assignment ..................................................................... 34811.12.1.7CPU and DMA Register Access Sizes ......................................................... 348

11.12.2 MCP Register Definitions .............................................................................................34911.12.3 MCP Control Register 0................................................................................................349

11.12.3.1Audio Sample Rate Divisor (ASD)................................................................ 34911.12.3.2Telecom Sample Rate Divisor (TSD) ........................................................... 35011.12.3.3Multimedia Communications Port Enable (MCE) ......................................... 35111.12.3.4External Clock Select (ECS)......................................................................... 35111.12.3.5A/D Sampling Mode (ADM) .......................................................................... 35211.12.3.6Telecom Transmit FIFO Interrupt Enable (TTE)........................................... 35211.12.3.7Telecom Receive FIFO Interrupt Enable (TRE) ........................................... 35211.12.3.8Audio Transmit FIFO Interrupt Enable (ATE) ............................................... 35211.12.3.9Audio Receive FIFO Interrupt Enable (ARE)................................................ 35311.12.3.10Loopback Mode (LBM) ............................................................................... 35311.12.3.11External Clock Prescaler (ECP) ................................................................. 353

11.12.4 MCP Control Register 1................................................................................................35511.12.4.1Clock Frequency Select (CFS) ..................................................................... 355

11.12.5 MCP Data Registers.....................................................................................................35611.12.5.1MCP Data Register 0.................................................................................... 35611.12.5.2MCP Data Register 1.................................................................................... 35711.12.5.3MCP Data Register 2.................................................................................... 358

11.12.6 MCP Status Register ....................................................................................................36011.12.6.1Audio Transmit FIFO Service Request Flag (ATS)

(read-only, maskable interrupt) ..................................................................... 36011.12.6.2Audio Receive FIFO Service Request Flag (ARS)

(read-only, maskable interrupt) ..................................................................... 36011.12.6.3Telecom Transmit FIFO Service Request Flag (TTS)

(read-only, maskable interrupt) ..................................................................... 36111.12.6.4Telecom Receive FIFO Service Request Flag (TRS)

(read-only, maskable interrupt) ..................................................................... 36111.12.6.5Audio Transmit FIFO Underrun Status (ATU)

(read/write, nonmaskable interrupt) .............................................................. 36111.12.6.6Audio Receive FIFO Overrun Status (ARO)

(read/write, nonmaskable interrupt) .............................................................. 36111.12.6.7Telecom Transmit FIFO Underrun Status (TTU)

(read/write, nonmaskable interrupt) .............................................................. 36211.12.6.8Telecom Receive FIFO Overrun Status (TRO)

(read/write, nonmaskable interrupt) .............................................................. 36211.12.6.9Audio Transmit FIFO Not Full Flag (ANF) (read-only, noninterruptible) ....... 36211.12.6.10Audio Receive FIFO Not Empty Flag (ANE) (read-only, noninterruptible) . 36211.12.6.11Telecom Transmit FIFO Not Full Flag (TNF) (read-only, noninterruptible). 36211.12.6.12Telecom Receive FIFO Not Empty Flag (TNE)

(read-only, noninterruptible) .......................................................................... 36211.12.6.13Codec Write Completed Flag (CWC) (read-only, noninterruptible) ............ 36311.12.6.14Codec Read Completed Flag (CRC) (read-only, noninterruptible)............. 36311.12.6.15Audio Codec Enabled Flag (ACE) (read-only, noninterruptible)................. 36311.12.6.16Telecom Codec Enabled Flag (TCE) (read-only, noninterruptible) ............ 363

11.12.7 SSP Operation..............................................................................................................365


11.12.7.1Frame Format................................................................................................36611.12.7.2Baud Rate Generation...................................................................................37011.12.7.3SSP Transmit and Receive FIFOs ................................................................37011.12.7.4CPU and DMA Register Access Sizes ..........................................................37111.12.7.5Alternate SSP Pin Assignment......................................................................371

11.12.8 SSP Register Definitions .............................................................................................. 37111.12.9 SSP Control Register 0 ................................................................................................ 372

11.12.9.1Data Size Select (DSS) ............................................................................... 37211.12.9.2Frame Format (FRF) .....................................................................................37211.12.9.3Synchronous Serial Port Enable (SSE).........................................................37211.12.9.4Serial Clock Rate (SCR)................................................................................373

11.12.10SSP Control Register 1............................................................................................... 37411.12.10.1Receive FIFO Interrupt Enable (RIE) ..........................................................37411.12.10.2Transmit FIFO Interrupt Enable (TIE)..........................................................37411.12.10.3Loopback Mode (LBM) ................................................................................37511.12.10.4Serial Clock Polarity (SPO) .........................................................................37511.12.10.5Serial Clock Phase (SPH) ...........................................................................37511.12.10.6External Clock Select (ECS) .......................................................................376

11.12.11SSP Data Register...................................................................................................... 37711.12.12SSP Status Register ................................................................................................... 379

11.12.12.1Transmit FIFO Not Full Flag (TNF) (read-only, noninterruptible) ................37911.12.12.2Receive FIFO Not Empty Flag (RNE) (read-only, noninterruptible) ............37911.12.12.3SSP Busy Flag (BSY) (read-only, noninterruptible) ....................................37911.12.12.4Transmit FIFO Service Request Flag (TFS)

(read-only, maskable interrupt) ......................................................................37911.12.12.5Receive FIFO Service Request Flag (RFS)

(read-only, maskable interrupt) ......................................................................38011.12.12.6Receiver Overrun Status (ROR) (read/write, nonmaskable interrupt) .........380

11.12.13MCP Register Locations ............................................................................................. 38111.12.14SSP Register Locations .............................................................................................. 382

11.13Peripheral Pin Controller (PPC) .............................................................................................. 38211.13.1 PPC Operation ............................................................................................................. 38211.13.2 PPC Register Definitions.............................................................................................. 38311.13.3 PPC Pin Direction Register ..........................................................................................38311.13.4 PPC Pin State Register ................................................................................................ 38511.13.5 PPC Pin Assignment Register...................................................................................... 387

11.13.5.1UART Pin Reassignment (UPR) ...................................................................38711.13.5.2SSP Pin Reassignment (SPR) ......................................................................387

11.13.6 PPC Sleep Mode Pin Direction Register ...................................................................... 38811.13.7 PPC Pin Flag Register .................................................................................................39011.13.8 PPC Register Locations ............................................................................................... 392

12 DC Parameters

12.1Absolute Maximum Ratings ...................................................................................................... 39312.2DC Operating Conditions .......................................................................................................... 39412.3Power Supply Voltages and Currents ....................................................................................... 395

13 AC Parameters

13.1Test Conditions ......................................................................................................................... 397


13.2Model Considerations ...............................................................................................................39813.3Memory Bus and PCMCIA Signal Timings ...............................................................................39813.4LCD Controller Signals..............................................................................................................39913.5MCP Signals .............................................................................................................................39913.6Timing Parameters....................................................................................................................401

13.6.1 Asynchronous Signal Timing Descriptions ...................................................................403

14 Package and Pinout

15 Debug Support

15.1Instruction Breakpoint ...............................................................................................................41115.2Data Breakpoint ........................................................................................................................411

16 Boundary-Scan Test Interface

16.1Overview ...................................................................................................................................41316.2Reset.........................................................................................................................................41416.3Pull-Up Resistors ......................................................................................................................41416.4Instruction Register ...................................................................................................................41416.5Public Instructions .....................................................................................................................414

16.5.1 EXTEST (00000) ..........................................................................................................41516.5.2 SAMPLE/PRELOAD (00001) .......................................................................................41516.5.3 CLAMP (00100)............................................................................................................41516.5.4 HIGHZ (00101) .............................................................................................................41616.5.5 IDCODE (00110) ..........................................................................................................41616.5.6 BYPASS (11111)..........................................................................................................416

16.6Test Data Registers ..................................................................................................................41716.6.1 Bypass Register ...........................................................................................................41716.6.2 Intel® StrongARM SA-1110 Device Identification (ID)Code Register41816.6.3 Intel® StrongARM SA-1110 Boundary-Scan (BS) Register .........................................418

16.7Boundary-Scan Interface Signals..............................................................................................419

A Register Summary

B 3.6864–MHz Oscillator SpecificationsB.1 Specifications ............................................................................................................................433

B.1.1 System Specifications ..................................................................................................433B.1.1.1. Parasitic Capacitance Off-chip Between PXTAL and PEXTAL......................434B.1.1.2. Parasitic Capacitance Off-chip Between PXTAL or PEXTAL and VSS .........434B.1.1.3. Parasitic Resistance Between PXTAL and PEXTAL .....................................434B.1.1.4. Parasitic Resistance Between PXTAL or PEXTAL and VSS.........................434

B.1.2 Quartz Crystal Specification .........................................................................................435

C 32.768–KHz Oscillator SpecificationsC.1 Specifications ............................................................................................................................437

C.1.1 System Specifications ..................................................................................................437C.1.1.1. Temperature Range .......................................................................................437C.1.1.2. Current Consumption .....................................................................................437C.1.1.3. Startup Time...................................................................................................437C.1.1.4. Frequency Shift Due to Temperature Effect on the Circuit ............................438C.1.1.5. Parasitic Capacitance Off-chip Between TXTAL and TEXTAL......................438C.1.1.6. Parasitic Capacitance Off-chip Between TXTAL or TEXTAL and VSS..........438C.1.1.7. Parasitic Resistance Between TXTAL and TEXTAL......................................438


C.1.1.8. Parasitic Resistance Between TXTAL or TEXTAL and VSS ......................... 438C.1.2 Quartz Crystal Specification ......................................................................................... 439

D Internal TestD.1 Test Unit Control Register (TUCR) ........................................................................................... 441

Figures

1-1 SA-1110 Features ......................................................................................................................211-2 SA-1110 Example System.......................................................................................................... 252-1 SA-1110 Block Diagram ............................................................................................................. 302-2 SA-1110 Functional Diagram ..................................................................................................... 312-3 SA-1110 Memory Map................................................................................................................386-1 Format of Internal Coprocessor Instructions MRC and MCR ..................................................... 558-1 SA-1110 Clock System Block Diagram ......................................................................................699-1 General-Purpose I/O Block Diagram .......................................................................................... 749-2 Interrupt Controller Block Diagram ............................................................................................. 839-3 Transitions Between Modes of Operation ................................................................................ 10510-1 General Memory Interface Configuration ................................................................................. 12010-2 Memory Pins and Memory Controller State after Hardware Reset ......................................... 12410-3 DRAM Single-Beat Transactions.............................................................................................. 15110-4 Dram Burst-of-Eight Transactions ............................................................................................ 15210-5 SDRAM State Machine............................................................................................................. 15610-6 SDRAM 1-Beat Read/Write/Read Timing for 4 Bank x 4 M x 4 Bit

Organization (64 Mbit) ..............................................................................................................15710-7 SDRAM 1-Beat Read/Write Timing for 4 Bank x 4 M x 4 Bit Organization

(64 Mbit) at Half-Memory Clock Frequency (MDREFR:KnDB2=1)) ......................................... 15810-8 SDRAM 8-Beat Read/Write Timing for 4 Bank x 4 M x 4 Bit

Organization (64 Mbit) ..............................................................................................................15910-9 DRAM/SDRAM CBR Refresh Cycle......................................................................................... 16110-10 Burst-of-Eight ROM or Flash Read Timing Diagram ................................................................16410-11 Eight-Beat Burst Read from Burst-of-Four ROM or Flash ........................................................ 16510-12 Nonburst ROM, SRAM, or Flash Read Timing Diagram – Four Data Beats) ........................... 16610-13 SRAM Write Timing Diagram (4–Beat Burst) ........................................................................... 16810-14 Variable Latency I/O Read Timing (Burst-of-Four) ................................................................... 17010-15 Variable Latency I/O Write Timing (Burst-of-Four) ................................................................... 17110-16 Flash Write Timing Diagram (2 Writes) ....................................................................................17310-17 SMROM State Machine............................................................................................................ 17610-18 SMROM Eight-Beat and Two-Beat Timing for 2 M x 16 Bit Organization

(32 Mbit) at Half-Memory Clock Frequency (MDREFR:K0DB2=1)........................................... 17710-19 PC-Card Memory Map..............................................................................................................17810-20 PC-Card External Logic for a Two-Socket Configuration ......................................................... 18110-21 PC-Card External Logic for a One-Socket Configuration ......................................................... 18210-22 PC-Card Memory or I/O 16-Bit Access..................................................................................... 18310-23 PC-Card I/O 16-Bit Access to 8-Bit Device .............................................................................. 18410-24 DRAM System Example ........................................................................................................... 18710-25 SDRAM System Example......................................................................................................... 188


10-26 SMROM System Example ........................................................................................................18910-27 Memory Configuration Tool - page 1 ........................................................................................19110-28 Memory Configuration Tool - page 1, continued.......................................................................19210-29 Memory Configuration Tool - page 2 ........................................................................................19310-30 Memory Configuration Tool - page 3 ........................................................................................19410-31 Memory Configuration Tool - page 4 ........................................................................................19510-32 Memory Configuration Tool - page 5 ........................................................................................19610-33 Memory Configuration Tool - page 5, continued.......................................................................19710-34 Memory Configuration Tool - page 6 ........................................................................................19810-35 Memory Configuration Tool - page 6, continued.......................................................................19910-36 Memory Configuration Tool - page 7 ........................................................................................20010-37 Memory Configuration Tool - page 8 ........................................................................................20110-38 Memory Configuration Tool - page 8, continued.......................................................................20210-39 Memory Configuration Tool - page 8, continued.......................................................................20311-1 Peripheral Control Module Block Diagram................................................................................20611-2 Big and Little Endian DMA Transfers........................................................................................21211-3 Palette Buffer Format................................................................................................................22211-4 4 Bits Per Pixel Data Memory Organization (Little Endian) ......................................................22311-5 12-Bits Per Pixel Data Memory Organization (Passive Mode Only).........................................22411-6 16-Bits Per Pixel Data Memory Organization (Active Mode Only)............................................22411-7 LCD Data-Pin Pixel Ordering....................................................................................................23111-8 Frame Buffer/Palette Bits Output to LCD Data Pins in Active Mode ........................................23311-9 Passive Mode Beginning-of-Frame Timing...............................................................................25411-10 Passive Mode End-of-Frame Timing ........................................................................................25511-11 Passive Mode Pixel Clock and Data Pin Timing.......................................................................25611-12 Active Mode Timing ..................................................................................................................25711-13 Active Mode Pixel Clock and Data Pin Timing..........................................................................25811-14 Connecting the USB to the SA-1110 UDC ...............................................................................26311-15 NRZI Bit Encoding Example .....................................................................................................26411-16 Setup Token Packet Format .....................................................................................................26611-17 SOF Token Packet Format .......................................................................................................26611-18 Data Packet Format..................................................................................................................26611-19 Handshake Packet Format .......................................................................................................26711-20 Bulk Transaction Formats.........................................................................................................26811-21 Control Transaction Formats ....................................................................................................26911-22 HP-SIR Modulation Example ....................................................................................................30111-23 UART Frame Format for IrDA Transmission (

13-1 Memory Bus AC Timing Definitions..........................................................................................39813-2 LCD AC Timing Definitions.......................................................................................................39913-3 MCP AC Timing Definitions ...................................................................................................... 40014-1 SA-1110 256-Pin mBGA Mechanical Drawing ......................................................................... 40616-1 Test Access Port (TAP) Controller State Transitions ............................................................... 41316-2 Boundary-Scan Block Diagram ................................................................................................ 41716-3 Boundary-Scan General Timing ............................................................................................... 41916-4 Boundary-Scan Tristate Timing ................................................................................................ 42016-5 Boundary-Scan Reset Timing................................................................................................... 420

Tables

1-2 Changes to the SA-1110 Core from the SA-110 ........................................................................ 221-1 Features of the SA-1110 CPU.................................................................................................... 221-3 Feature Additions to the SA-1110 from the SA-110 ................................................................... 231-4 Feature Additions to the SA-1110 from the SA-1100 ................................................................. 232-1 Signal Descriptions..................................................................................................................... 323-1 Vector Summary......................................................................................................................... 424-1 Instruction Timing ....................................................................................................................... 455-1 Effects of the Cacheable and Bufferable Bits on the Data Caches ............................................ 496-1 Cache and MMU Control Registers (Coprocessor 15) ............................................................... 567-1 Valid MMU, Dcache, and Write Buffer Combinations................................................................. 668-1 Core Clock Configurations.......................................................................................................... 709-1 OS Timer Register Locations ..................................................................................................... 999-2 SA-1110 Power and Clock Supply Sources and States During Power-Down Modes .............. 1069-3 Pin State During Sleep ............................................................................................................. 1079-4 Power Manager Register Locations ......................................................................................... 1149-5 Reset Controller Register Locations......................................................................................... 11710-1 Supported Memory Types ........................................................................................................ 11910-2 SA-1110 Transactions On 32-Bit Data Buses .......................................................................... 12310-3 Memory Interface Control Registers......................................................................................... 12710-4 Timing Interpretations of Possible SDRAM/SMROM MDCAS Settings ................................... 13910-5 BS_xx Bit Encoding .................................................................................................................. 14310-6 BCLK Speeds for 160-MHz Processor Core Frequency ..........................................................14310-7 Some DRAM Memory Size Options ......................................................................................... 14810-8 DRAM or SMROM Row/Column Address Multiplexing ............................................................ 14910-9 SDRAM Command Encoding ................................................................................................... 15410-10 Summary of Static Memory and Variable Latency I/O Capabilities .......................................... 16210-11 SMROM Command Encoding .................................................................................................. 17411-1 Peripheral Control Modules’ Register Width and DMA Port Size .............................................20611-2 Peripheral Unit Base Addresses............................................................................................... 20711-3 Peripheral Unit Interrupt Numbers............................................................................................ 20711-4 Dedicated Peripheral Pins ........................................................................................................ 20811-5 Peripheral Unit GPIO Pin Assignment...................................................................................... 20911-6 Valid Settings for the DDARn Register..................................................................................... 21311-7 8-Bits Per Pixel Data Memory Organization (Little Endian)...................................................... 22411-8 Color/Gray-Scale Intensities and Modulation Rates................................................................. 22711-9 LCD Controller Data Pin Utilization ..........................................................................................230


11-10 LCD Controller Control, DMA, and Status Register Locations .................................................25211-11 USB Bus States........................................................................................................................26111-12 Endpoint Field Addressing........................................................................................................26511-13 Host Device-Request Command Summary..............................................................................27011-14 SA-1110 UDC Control, Data, and Status Register Locations...................................................29411-15 UART Control, Data, and Status Register Locations................................................................29911-16 GPCLK Control Register Locations ..........................................................................................30011-17 UART Control, Data, and Status Register Locations................................................................32411-18 HSSP Control, Data, and Status Register Locations................................................................32411-19 Serial Port 3 Control, Data, and Status Register Locations......................................................34111-20 MCP Control, Data, and Status Register Locations..................................................................38111-21 SSP Control, Data, and Status Register Locations ..................................................................38211-22 PPC Control and Flag Register Locations ................................................................................39212-1 SA-1110 DC Maximum Ratings................................................................................................39312-2 SA-1110 DC Operating Conditions........

Intel StrongARM SA-1110 Microprocessor · SA-1110 Developer’s Manual Information in this document is provided in connection with Intel products. No license, express or implied,

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