-
Revision Number: 2.1
March 2013
Intel® Ethernet Controller I350 DatasheetLAN Access Division
(LAD)
FeaturesExternal Interfaces provided: PCIe v2.1 (2.5GT/s and
5GT/s) x4/x2/x1; called PCIe in this
document. MDI (Copper) standard IEEE 802.3 Ethernet interface
for
1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3,
802.3u, and 802.3ab)
Serializer-Deserializer (SERDES) to support 1000BASE-SX/LX
(optical fiber - IEEE802.3)
Serializer-Deserializer (SERDES) to support 1000BASE-KX
(802.3ap) and 1000BASE-BX (PICMIG 3.1) for Gigabit backplane
applications
SGMII (Serial-GMII Specification) interface for SFP (SFP MSA
INF-8074i)/external PHY connections
NC-SI (DMTF NC-SI) or SMBus for Manageability connection to
BMC
IEEE 1149.6 JTAG
Performance Enhancements: PCIe v2.1 TLP Process Hints (TPH) UDP,
TCP and IP Checksum offload UDP and TCP Transmit Segmentation
Offload (TSO) SCTP receive and transmit checksum offload
Virtualization ready: Next Generation VMDq support (8 VMs)
Support of up to 8 VMs per port (1 queue allocated to each
VM) PCI-SIG I/O SR-IOV support (Direct assignment) Queues per
port: 8 TX and 8 RX queues
Power saving features: Advanced Configuration and Power
Interface (ACPI) power
management states and wake-up capability Advanced Power
Management (APM) wake-up functionality Low power link-disconnect
state PCIe v2.1 LTR DMA Coalescing for improved system power
management EEE (IEEE802.3az) for reduced power consumption
during
low link utilization periods
IEEE802.1AS - Timing and Synchronization: IEEE 1588 Precision
Time Protocol support Per-packet timestamp
Total Cost Of Ownership (TCO): IPMI BMC pass-thru; multi-drop
NC-SI Internal BMC to OS and OS to BMC traffic support
Additional product details: 17x17 (256 Balls) or 25x25 (576
Balls) PBGA package Estimated power: 2.8W (max) in dual port mode
and 4.2W
(max) in quad port mode Memories have Parity or ECC
protection
-
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MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS.
Intel may make changes to specifications and product descriptions
at any time, without notice. Designers must not rely on the absence
or characteristics of any features or instructions marked
"reserved" or "undefined". Intel reserves these for future
definition and shall have no responsibility whatsoever for
conflicts or incompatibilities arising from future changes to them.
The information here is subject to change without notice. Do not
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which may cause the product to deviate from published
specifications. Current characterized errata are available on
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trademarks or registered trademarks of Intel Corporation or its
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and brands may be claimed as the property of others.Copyright ©
2013. Intel Corporation. All Rights Reserved.
Intel® Ethernet Controller I350 Revision Number: 2.1Datasheet
March 20132
http://www.intel.com/design/literature.htm
-
Revision History — Intel® Ethernet Controller I350
Revision Number: 2.1 Intel® Ethernet Controller I350March 2013
Datasheet 3
Revision History
Rev Date Comments
.3 1/8/2010 Initial public release.
.5 5/21/2010 Updated using latest internal specs.
1.0 1/7/2011 Updated using latest internal specs.
1.1 4/6/2011 Updated using latest internal specs.
1.9 4/14/2011 Updated with latest internal specs.Version number
moved to 1.9 for PRQ.
1.91 5/6/2011
Added or updated:• Section 6.4.2, Port Identification LED
blinking (Word 0x04)• Section 13.1, Thermal Sensor and Thermal
Diode• Updated power numbers.
1.92 5/10/2011Added (improves coverage of 2-port 17X17
package):• Section 2.2.13, 2-Port 17x17 PBGA Package Pin List
(Alphabetical)• Section 2.2.14, 2-Port 17x17 PBGA Package
No-Connect Pins
1.93 5/20/2011
Updated.• Section 1.6, I350 Packaging Options. Updated to cover
both 17x17 options.• Section 11-5, Flash Timing Diagram. Removed
meaningless line from diagram.• Section 11.7.1.1, 17x17 PBGA
Package Schematics. Corrected display issue
with diagram.
2.00 6/23/2011
SRA release.• RSVD_TX_TCLK was expressed as 1.25MHZ (clock
speed). Corrected to
125MHz in two places. See Table 2-10, Analog Pins, Table 2-23,
PHY Analog Pins.
• Section 11.7.2.1, 25x25 PBGA Package Schematics. Diagram
updated.
2.01 6/24/2011• Section 8.5.5, Flow Control Receive Threshold
Low - FCRTL0 (0x2160; R/W).
Changed: “at least 1b (at least 16 bytes)” to “3b (at least 48
bytes) Diagram updated”.
2.02 8/2/2011• Figure 7-26, Figure 7-26 build issues corrected.•
Section 10.6.3.16, Thermal Sensor Commands. Note added (“Thermal
Sensor
configuration can be done only through NC-SI channel 0.”).
2.03 8/25/2011
• Section 6.2.22, Functions Control (Word 0x21), bit 9 note;
Section 9.4.11.4, Base Address Register Fields, bit 9 description.
Both contain the updated text: “This bit should be set only on
systems that do not generate prefetchable cycles.”
• Section 8.26.1, Internal PHY Configuration - IPCNFG (0x0E38,
RW) and Section 8.26.2, PHY Power Management - PHPM (0x0E14, RW);
tables reformatted.
• Table 10-49, Driver Info Host Command, Byte 1; description
updated. • Table 11-6, Power Consumption 2 Ports, D0a - Active Link
row, total power
column has been corrected.
2.04 9/16/2011
• Section 5.1.1, PCI Device Power States. Section updated. See
text starting with “The PCIe link state follows the power
management state of the device...”
• Section 6.3.11, NC-SI Configuration Module (Global MNG Offset
0x0A). Register descriptions for a number off offsets have been
updated. These include: Offsets 0x01, 0x03, 0x05, and 0x07
• Table 8-10, Usable FLASH Size and CSR Mapping Window Size.
Table added to Datasheet.
• Table 10-30, Supported NC-SI Commands. “Set Ethernet Mac
Address” corrected to “Set MAC Address”. “Clear Ethernet MAC
Address” removed from supported. This is an obsolete reference.
-
Intel® Ethernet Controller I350 — Revision History
Intel® Ethernet Controller I350 Revision Number: 2.1Datasheet
March 20134
2.05 12/20/2011
• Section 6.3.12.2, Traffic Type Data - Offset 0x1. Default
values of 01 added for all traffic types.
• Section 6.4.9, Reserved/3rd Party External Thermal Sensor –
(Word 0x3E). New reserved section added. Section 8.16.28.1, Time
Sync Interrupt Cause Register - TSICR (0xB66C; RC/W1C). Note in
section updated. New text: “Once ICR.Time_Sync is set, TSICR should
be read to determine the actual interrupt cause and to enable
reception of an additional ICR.Time_Sync interrupt.”
• Figure 12-6: Updated to correct error. Section 12.5,
Oscillator Support: Contains similar update in the section’s first
bullet.
2.06 4/10/2012
• Section 3.1.7.9, Completion with Completer Abort (CA). The
discussion has been corrected. The updated paragraph is: “A DMA
master transaction ending with a Completer Abort (CA) completion
causes all PCIe master transactions to stop; the PICAUSE.ABR bit is
set and an interrupt is generated if the appropriate mask bits are
set. To enable PCIe master transactions following reception of a CA
completion, software issues an FLR to the right function or a PCI
reset to the device and re-initializes the function(s).”
• Section 6.3.9.17, NC-SI over MCTP Configuration - 0ffset 0x10.
Phrase in bit 7 description updated. New text: “If cleared, a
payload type byte is expected in NC-SI over MCTP packets after the
packet type...”
• Section 6.4.3, EEPROM Image Revision (Word 0x05). Table
updated; bit assignment descriptions changed. Changed to: 15:12
EEPROM major version; 11:8 are reserved; 7:0 EEPROM minor version.
Example given in note.
• Section 9.6.6.2, LTR Capabilities (0x1C4; RW). The reserved
fields (bits 15:13 and 31:29) now indicate RO, not RW.
• Figure 11-11 : Coupling cap data in figure corrected; changed
10pf to 1000pf.
• Table 12-4, Crystal Manufacturers and Part Numbers. Footnote
added to table for 7A25000165. Text states: “This part footprint
compatible with X540 designs.”
Rev Date Comments
-
Revision History — Intel® Ethernet Controller I350
Revision Number: 2.1 Intel® Ethernet Controller I350March 2013
Datasheet 5
2.1
• Section 2.3.4, NC-SI Interface Pins. Notes added. They specify
pull-ups/downs used when NC-SI is disconnected.
• Section 7.8.2.2.5, Serial ID. New text provided: “The serial
ID capability is not supported in VFs.”
•Section 8.8.10, Interrupt Cause Set Register - ICS (0x1504;
WO). Time Sync (bit 19) exposed.
• Table 11-6, Power Consumption 2 Ports. Some numbers updated.
See bold copy.
• Revised Table 2-15 - 2-Port 17x17 PBGA Package Pin List
(Alphabetical); SDP2 and SDP3 connections.
• Revised Section 2.3.8 (Power Supply and Ground Pins); removed
C4.• Revised Section 2.3.9 (25x25 PBGA Package Pin List
(Alphabetical); C4 signal
name change.• Revised Section 3.7.6.3.1 (Setting Powerville to
Internal PHY loopback Mode);
added new bullet.• Revised Section 4.3.5 (Registers and Logic
Reset Affects); step 10.• Revised Section 6.2.17 (PCIe Control 1
(Word 0x1B); bit 14 description.• Revised Section 6.3.9.17 (NC-SI
over MCTP Configuration - 0ffset 0x10); bit 7
description.• Added Section 6.4.6.11 through Section 6.4.6.18
and (PXE VLAN
Configuration Pointer (0x003C) bit descriptions.• Revised Table
8-6 - Register Summary); Management Flex UDP/TCP Ports
address.• Revised Section 8.8.9 (Interrupt Cause Read Register -
ICR (0x1500; RC/
W1C); bit 20 description.• Revised Section 10.5.8.1 (Transmit
Errors in Sequence Handling); note after
table 10-10.• Revised Section 10.7.1.3 (Simplified MCTP Mode);
removed payload type
references.• Revised Section 10.7.4.1 (NC-SI Packets Format).•
Added Section 10.7.4.1.1 (Control Packets).• Revised Section
10.7.4.1.2 (Command Packets); payload type and message
type.• Revised Section 10.7.4.1.3 (Response Packets); payload
type and message
type.• Revised Section 11.3.1 (Power Supply Specification);
added second footnote.
Rev Date Comments
-
Intel® Ethernet Controller I350 — Revision History
Intel® Ethernet Controller I350 Revision Number: 2.1Datasheet
March 20136
NOTE: This page intentionally left blank.
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Contents — Intel® Ethernet Controller I350
Revision Number: 2.1 Intel® Ethernet Controller I350March 2013
Datasheet 7
Contents
1 Introduction
............................................................................................................
371.1 Scope
......................................................................................................................................
381.2 Terminology and Acronyms
.........................................................................................................
39
1.2.1 External Specification and
Documents...........................................................................
401.2.1.1 Network Interface Documents
.....................................................................................
401.2.1.2 Host Interface
Documents...........................................................................................
411.2.1.3 Networking Protocol
Documents...................................................................................
411.2.1.4 Manageability Documents
...........................................................................................
41
1.3 Product Overview
......................................................................................................................
421.4 External
Interface......................................................................................................................
42
1.4.1 PCIe Interface
...........................................................................................................
421.4.2 Network
Interfaces.....................................................................................................
421.4.3 EEPROM Interface
......................................................................................................
421.4.4 Serial Flash Interface
.................................................................................................
431.4.5 SMBus Interface
........................................................................................................
431.4.6 NC-SI Interface
.........................................................................................................
431.4.7 MDIO/I2C 2-Wire Interfaces
........................................................................................
431.4.8 Software-Definable Pins (SDP) Interface
(General-Purpose I/O)
................................................................................................
441.4.9 LEDs
Interface...........................................................................................................
44
1.5
Features...................................................................................................................................
441.6 I350 Packaging Options
..............................................................................................................
481.7 Overview of Changes Compared to the 82580
...............................................................................
49
1.7.1 Network Interface
......................................................................................................
491.7.1.1 Energy Efficient Ethernet
(IEEE802.3AZ).......................................................................
491.7.1.2 MDI
Flip....................................................................................................................
491.7.2
Virtualization.............................................................................................................
491.7.2.1 PCI SR IOV
...............................................................................................................
491.7.2.2 Promiscuous VLAN Filtering
.........................................................................................
501.7.2.3 Improvements to VMDq
Switching................................................................................
50
1.7.2.3.1 Promiscuous Modes
.................................................................................
501.7.2.3.2 Microsoft NLB Mode Support
.....................................................................
50
1.7.2.4 Number of Exact Match Filters
.....................................................................................
501.7.2.5 Support for 2K Header Buffer
......................................................................................
501.7.2.6 Support for Port Based VLAN
.......................................................................................
501.7.2.7 Header Split on L2 Header
..........................................................................................
501.7.2.8 Updated Pool Decision
Algorithm..................................................................................
501.7.2.9 Statistics
..................................................................................................................
501.7.3 HOST
Interface..........................................................................................................
511.7.3.1 MSI-X Support
..........................................................................................................
511.7.3.2 ID-Based Ordering
.....................................................................................................
511.7.3.3 Alternative Routing-ID Interpretation (ARI)
...................................................................
511.7.3.4 Link State Related Latency Tolerance Reporting
(LTR).....................................................
511.7.3.5 Access Control Services (ACS)
.....................................................................................
511.7.3.6 ASPM Optionality Compliance
Capability........................................................................
511.7.4 Manageability
............................................................................................................
521.7.4.1 Auto-ARP Reply on
SMBus...........................................................................................
521.7.4.2 NC-SI Commands.
.....................................................................................................
52
1.7.4.2.1 NC-SI Hardware Arbitration
......................................................................
521.7.4.3 OS to BMC Traffic
......................................................................................................
521.7.4.4 DMTF MCTP Protocol Over
SMBus.................................................................................
521.7.4.5 Proxying
...................................................................................................................
521.7.5 EEPROM Structures
....................................................................................................
531.7.6 Recovery from Memory
Error......................................................................................
531.7.7 BOM Cost
Reduction...................................................................................................
531.7.7.1 On-Chip 1.8V LVR Control
...........................................................................................
531.7.7.2 On-Chip 1.0V SVR
Control...........................................................................................
531.7.7.3 Thermal Sensor
.........................................................................................................
53
1.8 Device Data Flows
.....................................................................................................................
541.8.1 Transmit Data Flow
....................................................................................................
541.8.2 Receive Data
Flow......................................................................................................
55
2 Pin Interface
...........................................................................................................
572.1 Signal Type Notation
..................................................................................................................
572.2 17x17 PBGA Package Pin Assignment
...........................................................................................
57
2.2.1 PCIe
........................................................................................................................
572.2.2 Flash and EEPROM Ports
............................................................................................
582.2.3 System Management Bus (SMB) Interface
....................................................................
592.2.4 NC-SI Interface Pins
..................................................................................................
592.2.5 Miscellaneous Pins
....................................................................................................
60
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Intel® Ethernet Controller I350 — Contents
Intel® Ethernet Controller I350 Revision Number: 2.1Datasheet
March 20138
2.2.6 SERDES/SGMII Pins
..................................................................................................
612.2.7 SFP Pins
..................................................................................................................
632.2.8 PHY Pins
...................................................................................................................
642.2.8.1 LED’s
......................................................................................................................
642.2.8.2 PHY Analog Pins
........................................................................................................
652.2.9 Voltage Regulator Pins
...............................................................................................
672.2.10 Testability Pins
.........................................................................................................
672.2.11 Power Supply and Ground Pins
...................................................................................
692.2.12 4-Port 17x17 PBGA Package Pin List (Alphabetical)
......................................................... 692.2.13
2-Port 17x17 PBGA Package Pin List (Alphabetical)
......................................................... 722.2.14
2-Port 17x17 PBGA Package No-Connect Pins
................................................................
74
2.3 25x25 PBGA Package Pin Assignment
...........................................................................................
742.3.1 PCIe
........................................................................................................................
742.3.2 Flash and EEPROM Ports
............................................................................................
752.3.3 System Management Bus (SMB) Interface
....................................................................
752.3.4 NC-SI Interface Pins
..................................................................................................
762.3.5 Miscellaneous Pins
.....................................................................................................
762.3.6 PHY Pins
...................................................................................................................
772.3.6.1 LED’s
......................................................................................................................
772.3.6.2 PHY Analog Pins
........................................................................................................
782.3.7 Testability Pins
.........................................................................................................
792.3.8 Power Supply and Ground Pins
....................................................................................
802.3.9 25x25 PBGA Package Pin List (Alphabetical)
..................................................................
81
2.4 Pullups/Pulldowns
......................................................................................................................
862.5 Strapping
.................................................................................................................................
892.6 Interface
Diagram......................................................................................................................
912.7 17x17 PBGA Package Ball-Out
.....................................................................................................
922.8 25x25 PBGA Package Ball-Out
.....................................................................................................
933 Interconnects
..........................................................................................................
953.1 PCIe
........................................................................................................................................
95
3.1.1 PCIe
Overview...........................................................................................................
953.1.1.1 Architecture, Transaction and Link Layer Properties
........................................................ 963.1.1.2
Physical Interface
Properties........................................................................................
973.1.1.3 Advanced
Extensions..................................................................................................
973.1.2 Functionality - General
...............................................................................................
973.1.2.1 Native/Legacy
...........................................................................................................
973.1.2.2 Locked Transactions
...................................................................................................
973.1.3 Host Interface
...........................................................................................................
983.1.3.1 Tag IDs
....................................................................................................................
98
3.1.3.1.1 TAG ID Allocation for Read Transactions
..................................................... 983.1.3.1.2
TAG ID Allocation for Write Transactions
.................................................... 99
3.1.3.2 Completion Timeout
Mechanism..................................................................................1003.1.3.2.1
Completion Timeout
Period......................................................................101
3.1.4 Transaction Layer
.....................................................................................................1013.1.4.1
Transaction Types Accepted by the I350
......................................................................101
3.1.4.1.1 Configuration Request Retry Status
..........................................................1023.1.4.1.2
Partial Memory Read and Write
Requests...................................................102
3.1.4.2 Transaction Types Initiated by the I350
.......................................................................1033.1.4.2.1
Data
Alignment......................................................................................1033.1.4.2.2
Multiple Tx Data Read Requests (MULR)
....................................................103
3.1.4.3
Messages.................................................................................................................1043.1.4.3.1
Message Handling by the I350 (as a Receiver)
...........................................1043.1.4.3.2 Message
Handling by the I350 (as a Transmitter)
.......................................104
3.1.4.4 Ordering Rules
.........................................................................................................1053.1.4.4.1
Out of Order Completion Handling
............................................................105
3.1.4.5 Transaction Definition and Attributes
...........................................................................1053.1.4.5.1
Max Payload Size
...................................................................................1053.1.4.5.2
Relaxed Ordering
...................................................................................1063.1.4.5.3
Snoop Not
Required................................................................................1063.1.4.5.4
No Snoop and Relaxed Ordering for LAN Traffic
..........................................1063.1.4.5.5 TLP
processing Hint (TPH)
.......................................................................107
3.1.4.6 Flow
Control.............................................................................................................1073.1.4.6.1
I350 Flow Control Rules
..........................................................................1073.1.4.6.2
Upstream Flow Control Tracking
...............................................................1083.1.4.6.3
Flow Control Update Frequency
................................................................1083.1.4.6.4
Flow Control Timeout Mechanism
.............................................................108
3.1.4.7 Error
Forwarding.......................................................................................................1083.1.5
Data Link Layer
........................................................................................................1093.1.5.1
ACK/NAK Scheme
.....................................................................................................1093.1.5.2
Supported DLLPs
......................................................................................................1093.1.5.3
Transmit EDB Nullifying
.............................................................................................1103.1.6
Physical Layer
..........................................................................................................1103.1.6.1
Link
Speed...............................................................................................................1103.1.6.2
Link Width
...............................................................................................................110
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Contents — Intel® Ethernet Controller I350
Revision Number: 2.1 Intel® Ethernet Controller I350March 2013
Datasheet 9
3.1.6.3 Polarity
Inversion......................................................................................................1113.1.6.4
L0s Exit latency
........................................................................................................1113.1.6.5
Lane-to-Lane De-Skew
..............................................................................................1113.1.6.6
Lane
Reversal...........................................................................................................1113.1.6.7
Reset
......................................................................................................................1123.1.6.8
Scrambler
Disable.....................................................................................................1123.1.7
Error Events and Error Reporting
................................................................................1133.1.7.1
Mechanism in General
...............................................................................................1133.1.7.2
Error
Events.............................................................................................................1133.1.7.3
Error Forwarding (TLP poisoning)
................................................................................1153.1.7.4
ECRC
......................................................................................................................1153.1.7.5
Partial Read and Write Requests
.................................................................................1153.1.7.6
Error Pollution
..........................................................................................................1163.1.7.7
Completion with Unsuccessful Completion Status
..........................................................1163.1.7.8
Error Reporting
Changes............................................................................................1163.1.7.9
Completion with Completer Abort
(CA).........................................................................1173.1.8
PCIe Power Management
...........................................................................................1173.1.9
PCIe Programming
Interface.......................................................................................117
3.2 Management Interfaces
.............................................................................................................1173.2.1
SMBus.....................................................................................................................1173.2.1.1
Channel
Behavior......................................................................................................1183.2.2
NC-SI......................................................................................................................1183.2.2.1
Electrical Characteristics
............................................................................................1183.2.2.2
NC-SI Transactions
...................................................................................................118
3.3 Flash /
EEPROM........................................................................................................................1193.3.1
EEPROM Interface
.....................................................................................................1193.3.1.1
General Overview
.....................................................................................................1193.3.1.2
EEPROM Device
........................................................................................................1193.3.1.3
HW Initial Load Process.
............................................................................................1203.3.1.4
Software Accesses
....................................................................................................1233.3.1.5
EEPROM Detection and Signature Field
........................................................................124
3.3.1.5.1 EEPROM
Detection..................................................................................1243.3.1.5.2
Detection of Valid EEPROM Image
............................................................124
3.3.1.6 Protected EEPROM Space
...........................................................................................1253.3.1.6.1
Initial EEPROM Programming
...................................................................1253.3.1.6.2
Activating the Protection
Mechanism.........................................................1253.3.1.6.3
Non Permitted Accessing to Protected Areas in the EEPROM
.........................125
3.3.1.7 EEPROM
Recovery.....................................................................................................1263.3.1.8
EEPROM-Less Support
...............................................................................................127
3.3.1.8.1 Access to the EEPROM Controlled
Feature..................................................1273.3.2
Shared
EEPROM........................................................................................................1283.3.2.1
EEPROM Deadlock
Avoidance......................................................................................1283.3.2.2
EEPROM Map Shared Words
.......................................................................................1293.3.3
Vital Product Data (VPD) Support
................................................................................1293.3.4
Flash Interface
.........................................................................................................1313.3.4.1
Flash Interface
Operation...........................................................................................1313.3.4.2
Flash Write Control
...................................................................................................1313.3.4.3
Flash Erase Control
...................................................................................................1323.3.5
Shared FLASH
..........................................................................................................1323.3.5.1
Flash Access
Contention.............................................................................................1323.3.5.2
Flash Deadlock Avoidance
..........................................................................................132
3.4 Configurable I/O Pins
................................................................................................................1333.4.1
General-Purpose I/O (Software-Definable Pins)
.............................................................1333.4.1.1
SDP usage for SFP
connectivity...................................................................................1343.4.2
Software Watchdog
...................................................................................................1343.4.2.1
Watchdog Rearm
......................................................................................................1343.4.3
LEDs
.......................................................................................................................135
3.5 Voltage
Regulators....................................................................................................................1353.5.1
1.8V LVR Control
......................................................................................................1363.5.2
1.0V SVR Control
......................................................................................................137
3.6 Thermal Sensor
........................................................................................................................1383.6.1
Initializing Thermal
Sensor.........................................................................................1383.6.2
Firmware Based Thermal
Management.........................................................................1393.6.3
Thermal Sensor Diagnostics
.......................................................................................1393.6.4
Thermal Sensor
Characteristics...................................................................................140
3.7 Network Interfaces
...................................................................................................................1403.7.1
Overview
.................................................................................................................1403.7.2
MAC Functionality
.....................................................................................................1413.7.2.1
Internal GMII/MII Interface
........................................................................................1413.7.2.2
MDIO/MDC PHY Management Interface
........................................................................141
3.7.2.2.1 Detection of External I2C or MDIO Connection
...........................................1423.7.2.2.2 MDIC and
MDICNFG register
usage...........................................................142
3.7.2.3 Duplex Operation with Copper
PHY..............................................................................1433.7.2.3.1
Full
Duplex............................................................................................1433.7.2.3.2
Half Duplex
...........................................................................................144
-
Intel® Ethernet Controller I350 — Contents
Intel® Ethernet Controller I350 Revision Number: 2.1Datasheet
March 201310
3.7.3 SerDes/1000BASE-BX, SGMII and 1000BASE-KX Support
..............................................1443.7.3.1
SerDes/1000BASE-BX, SGMII and 1000BASE-KX Analog
Block........................................1453.7.3.2
SerDes/1000BASE-BX, SGMII and 1000BASE-KX PCS
Block............................................1453.7.3.3 GbE
Physical Coding Sub-Layer
(PCS)..........................................................................145
3.7.3.3.1 8B10B
Encoding/Decoding.......................................................................1453.7.3.3.2
Code Groups and Ordered Sets
................................................................145
3.7.4 Auto-Negotiation and Link Setup Features
....................................................................1463.7.4.1
SerDes/1000BASE-BX Link Configuration
.....................................................................147
3.7.4.1.1 Signal Detect Indication
..........................................................................1473.7.4.1.2
MAC Link Speed
.....................................................................................1473.7.4.1.3
SerDes/1000BASE-BX Mode Auto-Negotiation
............................................1473.7.4.1.4 Forcing
Link-up in SerDes/1000BASE-BX
Mode...........................................1483.7.4.1.5 HW
Detection of Non-Auto-Negotiation
Partner...........................................148
3.7.4.2 1000BASE-KX Link Configuration
................................................................................1493.7.4.2.1
MAC Link Speed
.....................................................................................1493.7.4.2.2
1000BASE-KX Auto-Negotiation
...............................................................1493.7.4.2.3
Forcing Link-up in 1000BASE-KX
Mode......................................................1493.7.4.2.4
1000BASE-KX HW Detection of Link
Partner...............................................149
3.7.4.3 SGMII Link Configuration
...........................................................................................1493.7.4.3.1
SGMII Auto-Negotiation
..........................................................................1493.7.4.3.2
Forcing Link in SGMII
mode.....................................................................1503.7.4.3.3
MAC Speed Resolution
............................................................................150
3.7.4.4 Copper PHY Link
Configuration....................................................................................1503.7.4.4.1
PHY Auto-Negotiation (Speed, Duplex, Flow
Control)...................................1503.7.4.4.2 MAC Speed
Resolution
............................................................................1513.7.4.4.3
MAC Full-/Half- Duplex Resolution
............................................................1523.7.4.4.4
Using PHY Registers
...............................................................................1523.7.4.4.5
Comments Regarding Forcing
Link............................................................152
3.7.4.5 Loss of Signal/Link Status Indication
...........................................................................1533.7.5
Ethernet Flow Control (FC)
.........................................................................................1533.7.5.1
MAC Control Frames and Receiving Flow Control Packets
................................................154
3.7.5.1.1 Structure of 802.3X FC Packets
................................................................1543.7.5.1.2
Operation and Rules
...............................................................................1543.7.5.1.3
Timing
Considerations.............................................................................155
3.7.5.2 PAUSE and MAC Control Frames Forwarding
.................................................................1553.7.5.3
Transmission of PAUSE Frames
...................................................................................156
3.7.5.3.1 Operation and Rules
...............................................................................1563.7.5.3.2
Software Initiated PAUSE Frame Transmission
...........................................157
3.7.5.4 IPG Control and Pacing
..............................................................................................1573.7.5.4.1
Fixed IPG
Extension................................................................................157
3.7.6 Loopback Support
.....................................................................................................1583.7.6.1
General
...................................................................................................................1583.7.6.2
MAC
Loopback..........................................................................................................158
3.7.6.2.1 Setting the I350 to MAC Loopback Mode
...................................................1583.7.6.3
Internal PHY
Loopback...............................................................................................159
3.7.6.3.1 Setting the I350 to Internal PHY loopback Mode
.........................................1593.7.6.4 SerDes, SGMII
and 1000BASE-KX Loopback
.................................................................159
3.7.6.4.1 Setting SerDes/1000BASE-BX, SGMII, 1000BASE-KX
Loopback Mode............1593.7.6.5 External PHY Loopback
..............................................................................................160
3.7.6.5.1 Setting the I350 Internal PHY to External Loopback
Mode ............................1603.7.7 Energy Efficient Ethernet
(EEE)...................................................................................1603.7.7.1
Conditions to Enter EEE TX LPI
...................................................................................1613.7.7.2
Exit of TX LPI to Active Link State
...............................................................................1623.7.7.3
EEE Auto-Negotiation
................................................................................................1623.7.7.4
EEE Link Level (LLDP) Capabilities Discovery
................................................................1633.7.7.5
Programming the I350 for EEE Operation
.....................................................................1643.7.7.6
EEE Statistics
...........................................................................................................1653.7.8
Integrated Copper PHY
Functionality............................................................................1653.7.8.1
Determining Link State
..............................................................................................165
3.7.8.1.1 False
Link..............................................................................................1663.7.8.1.2
Forced Operation
...................................................................................1673.7.8.1.3
Auto Negotiation
....................................................................................1673.7.8.1.4
Parallel Detection
...................................................................................1673.7.8.1.5
Auto Cross-Over
....................................................................................1683.7.8.1.6
10/100 MB/s Mismatch Resolution
............................................................1693.7.8.1.7
Link Criteria
..........................................................................................169
3.7.8.2 Link Enhancements
...................................................................................................1703.7.8.2.1
SmartSpeed
..........................................................................................170
3.7.8.3 Flow
Control.............................................................................................................1713.7.8.4
Management Data Interface
.......................................................................................1723.7.8.5
Internal PHY Low Power Operation and Power Management
............................................172
3.7.8.5.1 Power Down via the PHY Register
.............................................................1723.7.8.5.2
Power Management
State........................................................................1723.7.8.5.3
Disable High Speed Power Saving Options
.................................................1723.7.8.5.4 Low
Power Link Up - Link Speed
Control....................................................173
-
Contents — Intel® Ethernet Controller I350
Revision Number: 2.1 Intel® Ethernet Controller I350March 2013
Datasheet 11
3.7.8.5.5 Internal PHY Smart Power-Down (SPD)
.....................................................1743.7.8.5.6
Internal PHY Link Energy
Detect...............................................................1753.7.8.5.7
Internal PHY Power-Down State
...............................................................175
3.7.8.6 Advanced
Diagnostics................................................................................................1763.7.8.6.1
TDR - Time Domain
Reflectometry............................................................1763.7.8.6.2
Channel Frequency
Response...................................................................176
3.7.8.7 1000 Mb/s
Operation.................................................................................................1773.7.8.7.1
Introduction
..........................................................................................1773.7.8.7.2
Transmit
Functions.................................................................................1773.7.8.7.3
Receive Functions
..................................................................................180
3.7.9 Media Auto Sense
.....................................................................................................1823.7.9.1
Auto sense setup
......................................................................................................183
3.7.9.1.1 SerDes/SGMII/1000BASE-KX Detect Mode (PHY is Active)
...........................1833.7.9.1.2 PHY Detect Mode
(SerDes/SGMII/1000BASE-KX is active)
...........................183
3.7.9.2 Switching between medias.
........................................................................................1833.7.9.2.1
Transition to SerDes/1000BASE-KX/SGMII
Modes.......................................1833.7.9.2.2 Transition
to Internal PHY Mode
...............................................................184
4
Initialization..........................................................................................................
1854.1 Power
Up.................................................................................................................................185
4.1.1 Power-Up Sequence
..................................................................................................1854.1.2
Power-Up Timing
Diagram..........................................................................................187
4.2 Reset Operation
.......................................................................................................................1884.2.1
Reset Sources
..........................................................................................................1884.2.1.1
LAN_PWR_GOOD
......................................................................................................1884.2.1.2
PE_RST_N
...............................................................................................................1884.2.1.3
In-Band PCIe
Reset...................................................................................................1884.2.1.4
D3hot to D0 Transition
..............................................................................................1884.2.1.5
Function Level Reset (FLR)
.........................................................................................189
4.2.1.5.1 PF (Physical Function) FLR or FLR in non-IOV
Mode.....................................1894.2.1.5.2 VF (Virtual
Function) FLR (Function Level Reset)
........................................1894.2.1.5.3 IOV (IO
Virtualization) Disable
.................................................................189
4.3 Software
Reset.........................................................................................................................1904.3.1
Full Port Software Reset
(RST)....................................................................................1904.3.2
Physical Function (PF) Software
Reset..........................................................................1904.3.3
VF Software Reset
....................................................................................................1904.3.4
Device Software Reset (DEV_RST)
..............................................................................1914.3.4.1
BME (Bus Master Enable)
...........................................................................................1914.3.4.2
Force
TCO................................................................................................................1924.3.4.3
EEPROM
Reset..........................................................................................................1924.3.4.4
PHY
Reset................................................................................................................1924.3.5
Registers and Logic Reset Affects
................................................................................1944.3.6
PHY Behavior During a Manageability Session
...............................................................198
4.4 Function Disable
.......................................................................................................................1994.4.1
General
...................................................................................................................1994.4.2
Overview
.................................................................................................................1994.4.3
Disabling Both LAN Port and PCIe
Function...................................................................2004.4.4
Disabling PCIe Function Only
......................................................................................2004.4.5
PCIe Functions to LAN Ports
Mapping...........................................................................2004.4.6
Control Options
........................................................................................................2024.4.7
Event Flow for Enable/Disable Functions
......................................................................2034.4.7.1
Multi-Function Advertisement
.....................................................................................2044.4.7.2
Legacy Interrupts
Utilization.......................................................................................2044.4.7.3
Power Reporting
.......................................................................................................204
4.5 Device Disable
.........................................................................................................................2044.5.1
BIOS Handling of Device Disable
.................................................................................205
4.6 Software Initialization and
Diagnostics.........................................................................................2054.6.1
Introduction
.............................................................................................................2054.6.2
Power Up
State.........................................................................................................2064.6.3
Initialization
Sequence...............................................................................................2064.6.4
Interrupts During
Initialization....................................................................................2064.6.5
Global Reset and General Configuration
.......................................................................2064.6.6
Flow Control
Setup....................................................................................................2074.6.7
Link Setup Mechanisms and Control/Status Bit Summary
...............................................2074.6.7.1 PHY
Initialization.......................................................................................................2074.6.7.2
MAC/PHY Link Setup (CTRL_EXT.LINK_MODE =
00b).....................................................207
4.6.7.2.1 MAC Settings Automatically Based on Duplex and Speed
Resolved by PHY (CTRL.FRCDPLX = 0b, CTRL.FRCSPD = 0b)
..............207
4.6.7.2.2 MAC Duplex and Speed Settings Forced by Software Based
on Resolution of PHY (CTRL.FRCDPLX = 1b, CTRL.FRCSPD = 1b)
..................208
4.6.7.2.3 MAC/PHY Duplex and Speed Settings Both Forced by
Software(Fully-Forced Link Setup) (CTRL.FRCDPLX = 1b, CTRL.FRCSPD =
1b, CTRL.SLU = 1b)
......................................................................................................208
4.6.7.3 MAC/SERDES Link Setup (CTRL_EXT.LINK_MODE = 11b)
..................................................................................209
-
Intel® Ethernet Controller I350 — Contents
Intel® Ethernet Controller I350 Revision Number: 2.1Datasheet
March 201312
4.6.7.3.1 Hardware Auto-Negotiation Enabled (PCS_LCTL. AN ENABLE
= 1b;CTRL.FRCSPD = 0b; CTRL.FRCDPLX = 0)
..................................................209
4.6.7.3.2 Auto-Negotiation Skipped (PCS_LCTL. AN ENABLE =
0b;CTRL.FRCSPD = 1b; CTRL.FRCDPLX = 1)
..................................................209
4.6.7.4 MAC/SGMII Link Setup (CTRL_EXT.LINK_MODE =
10b)..................................................2104.6.7.4.1
Hardware Auto-Negotiation Enabled (PCS_LCTL. AN ENABLE = 1b,
CTRL.FRCDPLX = 0b, CTRL.FRCSPD = 0b)
.................................................2104.6.7.5
MAC/1000BASE-KX Link Setup
(CTRL_EXT.LINK_MODE = 01b)
..................................................................................2104.6.7.5.1
Auto-Negotiation Skipped (PCS_LCTL. AN ENABLE = 0b;
CTRL.FRCSPD = 1b; CTRL.FRCDPLX = 1)
..................................................2104.6.8
Initialization of
Statistics............................................................................................2114.6.9
Receive Initialization
.................................................................................................2114.6.9.1
Initialize the Receive Control Register
..........................................................................2124.6.9.2
Dynamic Enabling and Disabling of Receive Queues
.......................................................2124.6.10
Transmit
Initialization................................................................................................2134.6.10.1
Dynamic Queue Enabling and
Disabling........................................................................2134.6.11
Virtualization Initialization
Flow...................................................................................2134.6.11.1
VMDq
Mode..............................................................................................................213
4.6.11.1.1 Global Filtering and Offload
Capabilities.....................................................2134.6.11.1.2
Mirroring rules.
......................................................................................2144.6.11.1.3
Per Pool
Settings....................................................................................2144.6.11.1.4
Security Features
...................................................................................215
4.6.11.2 IOV
Initialization.......................................................................................................2154.6.11.2.1
PF Driver
Initialization.............................................................................2154.6.11.2.2
VF Driver Initialization
............................................................................2154.6.11.2.3
Full Reset Coordination
...........................................................................2164.6.11.2.4
VFRE/VFTE
............................................................................................216
4.6.12 Alternate MAC Address Support
..................................................................................2174.7
Access to Shared Resources
.......................................................................................................217
4.7.1 Acquiring Ownership Over a Shared Resource
...............................................................2184.7.2
Releasing Ownership Over a Shared
Resource...............................................................2184.7.3
Software to Software Mailbox
.....................................................................................220
5 Power
Management...............................................................................................
2215.1 General Power State Information
................................................................................................221
5.1.1 PCI Device Power States
............................................................................................2215.1.2
PCIe Link Power States
..............................................................................................222
5.2 Power
States............................................................................................................................2225.2.1
D0 Uninitialized State (D0u)
.......................................................................................2235.2.1.1
Entry into D0u
State..................................................................................................2235.2.2
D0active
State..........................................................................................................2245.2.2.1
Entry to D0a State
....................................................................................................2245.2.3
D3 State (PCI-PM D3hot)
...........................................................................................2245.2.3.1
Entry to D3
State......................................................................................................2255.2.3.2
Exit from D3 State
....................................................................................................2255.2.3.3
Master Disable Via CTRL Register
................................................................................2265.2.4
Dr State (D3cold)
.....................................................................................................2275.2.4.1
Dr Disable Mode
.......................................................................................................2275.2.4.2
Entry to Dr State
......................................................................................................2275.2.4.3
Auxiliary Power Usage
...............................................................................................2285.2.5
Link Disconnect
........................................................................................................2285.2.6
Device Power-Down State
..........................................................................................229
5.3 Power Limits by Certain Form Factors
..........................................................................................2295.4
Interconnects Power
Management...............................................................................................230
5.4.1 PCIe Link Power
Management.....................................................................................2305.4.2
NC-SI Clock Control
..................................................................................................2325.4.3
Internal PHY Power-Management
................................................................................232
5.5 Timing of Power-State
Transitions...............................................................................................2325.5.1
Power Up (Off to Dup to D0u to
D0a............................................................................2335.5.2
Transition from D0a to D3 and Back Without PE_RST_N
.................................................2345.5.3
Transition From D0a to D3 and Back With
PE_RST_N.....................................................2355.5.4
Transition From D0a to Dr and Back Without Transition to D3
.........................................236
5.6 Wake Up
.................................................................................................................................2375.6.1
Advanced Power Management Wake Up
.......................................................................2375.6.2
ACPI Power Management Wake Up
..............................................................................2385.6.3
Wake-Up and Proxying Filters
.....................................................................................2395.6.3.1
Pre-Defined Filters
....................................................................................................239
5.6.3.1.1 Directed Exact Packet
.............................................................................2405.6.3.1.2
Directed Multicast Packet
........................................................................2405.6.3.1.3
Broadcast..............................................................................................2405.6.3.1.4
Magic Packet
.........................................................................................2405.6.3.1.5
ARP/IPv4 Request Packet
........................................................................2415.6.3.1.6
Directed IPv4 Packet
..............................................................................2425.6.3.1.7
Directed IPv6 Packet
..............................................................................243
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Contents — Intel® Ethernet Controller I350
Revision Number: 2.1 Intel® Ethernet Controller I350March 2013
Datasheet 13
5.6.3.1.8 NS and MLD IPv6
Packets........................................................................2435.6.3.2
Flexible Filters
..........................................................................................................245
5.6.3.2.1 IPX Diagnostic Responder Request Packet
.................................................2455.6.3.2.2
Directed IPX Packet
................................................................................2455.6.3.2.3
Utilizing Flex Wake-Up Filters In Normal Operation
.....................................246
5.6.3.3 Wake Up Packet
Storage............................................................................................2465.6.4
Wake-up and Virtualization
........................................................................................246
5.7 Protocol Offload (Proxying)
........................................................................................................2465.7.1
Proxying and
Virtualization.........................................................................................2475.7.2
Protocol Offload Activation in D3
.................................................................................2475.7.3
Protocol Offload Activation in D0
.................................................................................249
5.8 DMA
Coalescing........................................................................................................................2505.8.1
DMA Coalescing Activation
.........................................................................................2505.8.2
Entering DMA Coalescing Operating Mode
....................................................................2525.8.2.1
Entering DMA Coalescing
...........................................................................................2525.8.3
Conditions to Exit DMA
Coalescing...............................................................................2535.8.3.1
Exiting DMA
Coalescing..............................................................................................253
5.9 Latency Tolerance Reporting
(LTR)..............................................................................................2535.9.1
Latency Tolerance Reporting Algorithm
........................................................................2545.9.2
Latency Tolerance Reporting Per Function
....................................................................2565.9.2.1
Conditions for Generating LTR Message with the Requirement Bits
Cleared .......................2565.9.2.2 Conditions for Generating
LTR Message with Maximum LTR
Value....................................2575.9.2.3 Conditions for
Generating LTR Message with Minimum LTR Value
....................................257
6 Non-Volatile Memory Map - EEPROM
.....................................................................
2596.1 EEPROM General
Map................................................................................................................2596.2
Hardware Accessed Words
.........................................................................................................262
6.2.1 Ethernet Address (LAN Base Address + Offsets 0x00-0x02)
............................................2636.2.2 Initialization
Control Word 1 (word
0x0A).....................................................................2636.2.3
Subsystem ID (Word
0x0B)........................................................................................2646.2.4
Subsystem Vendor ID (Word 0x0C)
.............................................................................2646.2.5
Device ID (LAN Base Address + Offset 0x0D)
...............................................................2646.2.6
Vendor ID (Word 0x0E)
.............................................................................................2646.2.7
Dummy Device ID (Word
0x1D)..................................................................................2656.2.8
Initialization Control Word 2 (LAN Base Address + Offset 0x0F)
......................................2656.2.9 EEPROM Sizing and
Protected Fields (Word
0x12)..........................................................2666.2.10
Initialization Control 4 (LAN Base Address + Offset
0x13)...............................................2686.2.11 PCIe
L1 Exit latencies (Word 0x14)
.............................................................................2696.2.12
PCIe Completion Timeout Configuration (Word
0x15).....................................................2696.2.13
MSI-X Configuration (LAN Base Address + Offset 0x16)
.................................................2706.2.14 PCIe
Init Configuration 1 (Word 0x18)
.........................................................................2706.2.15
PCIe Init Configuration 2 Word (Word
0x19).................................................................2716.2.16
PCIe Init Configuration 3 Word (Word
0x1A).................................................................2716.2.17
PCIe Control 1 (Word 0x1B)
.......................................................................................2726.2.18
LED 1,3 Configuration Defaults (LAN Base Address + Offset 0x1C)
..................................2726.2.19 Device Rev ID (Word
0x1E)........................................................................................2746.2.20
LED 0,2 Configuration Defaults (LAN Base Address + Offset
0x1F)...................................2746.2.21 Software Defined
Pins Control (LAN Base Address + Offset
0x20)....................................2756.2.22 Functions
Control (Word 0x21)
...................................................................................2776.2.23
LAN Power Consumption (Word 0x22)
.........................................................................2786.2.24
Initialization Control 3 (LAN Base Address + Offset
0x24)...............................................2786.2.25 I/O
Virtualization (IOV) Control (Word 0x25)
................................................................2806.2.26
IOV Device ID (Word
0x26)........................................................................................2816.2.27
PCIe Control 2 (Word 0x28)
.......................................................................................2816.2.28
PCIe Control 3 (Word 0x29)
.......................................................................................2826.2.29
End of Read-Only (RO) Area (Word 0x2C)
....................................................................2826.2.30
Start of RO Area (Word 0x2D)
....................................................................................2826.2.31
Watchdog Configuration (Word 0x2E)
..........................................................................2836.2.32
VPD Pointer (Word 0x2F)
...........................................................................................283
6.3 CSR Auto load
Modules..............................................................................................................2836.3.1
Software Reset CSR Auto Configuration Pointer (LAN Base Address +
Offset 0x17) ............2836.3.2 Software Reset CSR Configuration
Section Length - Offset
0x0........................................2846.3.2.1 Block CRC8
(Offset 0x1)
............................................................................................2856.3.2.2
CSR Address - (Offset 3*n - 1; [n = 1... Section Length])
..............................................2856.3.2.3 CSR Data
LSB - (Offset 3*n; [n = 1... Section Length])
.................................................2856.3.2.4 CSR
Data MSB - (Offset 3*n + 1; [n = 1... Section
Length])...........................................2856.3.3 PCIe
Reset CSR Auto Configuration Pointer (LAN Base Address + Offset
0x23) ..................2856.3.3.1 PCIe Reset CSR Configuration
Section Length - Offset
0x0..............................................2866.3.3.2 Block
CRC8 (Offset 0x1)
............................................................................................2876.3.3.3
CSR Address - (Offset 3*n - 1; [n = 1... Section Length])
..............................................2876.3.3.4 CSR Data
LSB - (Offset 3*n; [n = 1... Section Length])
.................................................2876.3.3.5 CSR
Data MSB - (Offset 3*n + 1; [n = 1... Section
Length])...........................................2876.3.4 CSR
Auto Configuration Power-Up Pointer (LAN Base Address + Offset
0x27)....................2876.3.4.1 CSR Configuration Power-Up
Section Length - Offset 0x0
...............................................2886.3.4.2 Block
CRC8 (Offset 0x1)
............................................................................................289
-
Intel® Ethernet Controller I350 — Contents
Intel® Ethernet Controller I350 Revision Number: 2.1Datasheet
March 201314
6.3.4.3 CSR Address - (Offset 3*n - 1; [n = 1... Section
Length]) ..............................................2896.3.4.4
CSR Data LSB - (Offset 3*n; [n = 1... Section Length])
.................................................2896.3.4.5 CSR
Data MSB - (Offset 3*n + 1; [n = 1... Section
Length])...........................................2896.3.5 PCIe
PHY Auto Configuration Pointer (Word 0x10)
.........................................................2896.3.5.1
PCIe PHY Configuration Section Length - Offset
0x0.......................................................2906.3.5.2
Block CRC8 (Offset 0x1)
............................................................................................2906.3.5.3
Register Address - (Offset 2*n; [n = 1... Number of Registers to be
Written])...................2906.3.5.4 Register Data - (Offset 2*n
+ 1; [n = 1... Number of Registers to be Written])
.................2906.3.5.5 Setting Default PCIe Link Width and
Link Speed
............................................................290
6.3.5.5.1 PCIe Link Configuration Register Address - Offset 0x2
.................................2906.3.5.5.2 PCIe Link
Configuration Register Data - Offset 0x3
.....................................2906.3.5.5.3 PCIe Link Power
Down Register Address - Offset 0x4
..................................2916.3.5.5.4 PCIe Link Power Down
Register Data - Offset
0x5.......................................291
6.3.6 Management Pass Through LAN Configuration Pointer (LAN
Base Address + Offset 0x11) ...2916.3.6.1 PT LAN Configuration
Structure...................................................................................2926.3.6.2
Management PT LAN Configuration Structure Section Length - Offset
0x0 .........................2926.3.6.3 Block CRC8 (Offset 0x1)
............................................................................................2936.3.6.4
CSR Address - (Offset 2*n; [n = 1... Section Length])
...................................................2936.3.6.5 CSR
Data LSB - (Offset 0x1 + 2*n; [n = 1... Section Length])
........................................2936.3.6.6 CSR Data MSB -
(Offset 0x2 + 2*n; [n = 1... Section Length])
.......................................2936.3.6.7 Manageability
Filters..................................................................................................2936.3.7
Common Firmware Parameters – (Global MNG Offset 0x3)
.............................................2946.3.7.1 Section
Header — Offset 0x0
......................................................................................2946.3.7.2
Common Firmware Parameters 1 - Offset
0x1...............................................................2946.3.7.3
Common Firmware Parameters 2 – Offset 0x2
.............................................................2956.3.8
Pass Through LAN 0...3 Configuration Modules
(Global MNG Offsets 0x05, 0x08, 0x0D, 0X0E)
..............................................................2956.3.8.1
Section Header — Offset 0x0
......................................................................................2966.3.8.2
LAN 0/1/2/3 IPv4 Address 0 LSB; (MIPAF12 LSB) — Offset 0x01
.....................................2966.3.8.3 LAN 0/1/2/3 IPv4
Address 0 MSB; (MIPAF12 MSB) — Offset 0x02
...................................2966.3.8.4 LAN 0/1/2/3 IPv4
Address 1; (MIPAF13) — Offset 0x03-0x04
.........................................2966.3.8.5 LAN 0/1/2/3
IPv4 Address 2; (MIPAF14) — Offset 0x05-0x06
.........................................2966.3.8.6 LAN 0/1/2/3
IPv4 Address 3; (MIPAF15) — Offset 0x07-0x08
.........................................2976.3.8.7 LAN 0/1/2/3
Ethernet MAC Address 0 LSB (MMAL0) — Offset 0x09
..................................2976.3.8.8 LAN 0/1/2/3 Ethernet
MAC Address 0 MID; (MMAL0) — Offset 0x0A
................................2976.3.8.9 LAN 0/1/2/3 Ethernet MAC
Address 0 MSB; (MMAH0) — Offset 0x0B
...............................2976.3.8.10 LAN 0/1/2/3 Ethernet MAC
Address 1; (MMAL/H1) — Offset 0x0C-0x0E
...........................2976.3.8.11 LAN 0/1/2/3 Ethernet MAC
Address 2; (MMAL/H2) — Offset
0x0F-0x11............................2986.3.8.12 LAN 0/1/2/3
Ethernet MAC Address 3; (MMAL/H3) — Offset
0x12-0x14............................2986.3.8.13 LAN 0/1/2/3
UDP/TCP Flexible Filter Ports 0 — 7;
(MFUTP Registers) — Offset 0x15 -
0x1C......................................................................2986.3.8.14
Reserved EEPROM Words - Offset 0x1D - 0x24
.............................................................2986.3.8.15
LAN 0/1/2/3 VLAN Filter 0 - 7; (MAVTV Registers) — Offset 0x25 —
0x2C ........................2986.3.8.16 Reserved EEPROM Words -
Offset 0x2D to
0x2E............................................................2996.3.8.17
LAN 0/1/2/3 MANC value LSB; (LMANC LSB) — Offset
0x2F............................................2996.3.8.18 LAN
0/1/2/3 MANC Value MSB; (LMANC MSB) — Offset
0x30..........................................2996.3.8.19 LAN
0/1/2/3 Receive Enable 1; (LRXEN1) — Offset 0x31
................................................3016.3.8.20 LAN
0/1/2/3 Receive Enable 2; (LRXEN2) — Offset 0x32
................................................3016.3.8.21 LAN
0/1/2/3 MNGONLY LSB; (LMNGONLY LSB) - Offset 0x33
..........................................3016.3.8.22 LAN 0/1/2/3
MNGONLY MSB; (LMNGONLY MSB) - Offset 0x34
........................................3026.3.8.23 Manageability
Decision Filters 0 LSB; (MDEF0 LSB) - Offset 0x35
....................................3026.3.8.24 Manageability
Decision Filters 0 MSB; (MDEF0 MSB) - Offset
0x36...................................3026.3.8.25 Manageability
Decision Filters Extend 0 LSB; (MDEF_EXT0 LSB) - Offset
0x37...................3026.3.8.26 Manageability Decision Filters
Extend 0 MSB; (MDEF_EXT0 MSB) - Offset 0x38
.................3026.3.8.27 Manageability Decision Filters;
(MDEF1-6 and MDEF_EXT1-6) - Offset 0x39-0x50
..............3036.3.8.28 Manageability Ethertype Filter 0 LSB;
(METF0 LSB) -
Offset 0x51
..............................................................................................................3036.3.8.29
Manageability Ethertype Filter 0 MSB; (METF0 MSB) -
Offset 0x52
..............................................................................................................3036.3.8.30
Manageability Ethertype Filter 1...3; (METF1...3) -
Offset 0x53...0x58
....................................................................................................3036.3.8.31
ARP Response IPv4 Address 0 LSB; (ARP LSB) -
Offset 0x59
..............................................................................................................3046.3.8.32
ARP Response IPv4 Address 0 MSB; (ARP MSB) -
Offset 0x5A
..............................................................................................................3046.3.8.33
LAN0/1/2/3 IPv6 Address 0 LSB; (MIPAF0 LSB) -
Offset 0x5B
..............................................................................................................3046.3.8.34
LAN0/1/2/3 IPv6 Address 0 MSB; (MIPAF0 MSB) - Offset 0x5C
.......................................3046.3.8.35 LAN0/1/2/3 IPv6
Address 0 LSB; (MIPAF1 LSB)-
Offset
0x5D..............................................................................................................3046.3.8.36
LAN0/1/2/3 IPv6 Address 0 MSB; (MIPAF1 MSB) -
Offset 0x5E
..............................................................................................................3056.3.8.37
LAN0/1/2/3 IPv6 Address 0 LSB; (MIPAF2 LSB) -
Offset 0x5F
..............................................................................................................305
-
Contents — Intel® Ethernet Controller I350
Revision Number: 2.1 Intel® Ethernet Controller I350March 2013
Datasheet 15
6.3.8.38 LAN0/1/2/3 IPv6 Address 0 MSB; (MIPAF2 MSB) -Offset
0x60
..............................................................................................................305
6.3.8.39 LAN0/1/2/3 IPv6 Address 0 LSB; (MIPAF3 LSB) - Offset
0x61
..............................................................................................................305
6.3.8.40 LAN0/1/2/3 IPv6 Address 0 MSB; (MIPAF3 MSB) -Offset
0x62
..............................................................................................................306
6.3.8.41 LAN0/1/2/3 IPv6 Address 1; MIPAF (Offset 0x63:0x6A)
.................................................3066.3.8.42
LAN0/1/2/3 IPv6 Address 2; MIPAF (Offset
0x6B:0x72.................................................
)3066.3.9 Sideband Configuration Module
(Global MNG Offset 0x06)
..........................................................................................3066.3.9.1
Section Header — Offset
0x0......................................................................................3076.3.9.2
SMBus Maximum Fragment Size — Offset
0x01.............................................................3076.3.9.3
SMBus Notification Timeout and Flags — Offset 0x02
.....................................................3076.3.9.4
SMBus Slave Addresses 1 — Offset
0x03......................................................................3076.3.9.5
Reserved — Offset 0x04
............................................................................................3086.3.9.6
Reserved — Offset 0x05
............................................................................................3086.3.9.7
NC-SI Configuration - Offset
0x06...............................................................................3096.3.9.8
NC-SI Configuration - Offset
0x07...............................................................................3096.3.9.9
NC-SI Hardware Arbitration Configuration - Offset 0x08
.................................................3096.3.9.10 MCTP
UUID - Time Low LSB (0ffset 0x09)
....................................................................3106.3.9.11
MCTP UUID - Time Low MSB (0ffset 0x0A)
...................................................................3106.3.9.12
MCTP UUID - Time MID (0ffset 0x0B)
..........................................................................3106.3.9.13
MCTP UUID - Time High and Version (0ffset 0x0C)
........................................................3106.3.9.14
MCTP UUID - Clock Seq (0ffset
0x0D)..........................................................................3116.3.9.15
SMBus Slave Addresses 2 - Offset 0x0E
.......................................................................3116.3.9.16
Alternative IANA - 0ffset 0x0F
....................................................................................3116.3.9.17
NC-SI over MCTP Configuration - 0ffset 0x10
...............................................................3116.3.10
Flexible TCO Filter Configuration Module
(Global MNG Offset 0x07)
..........................................................................................3116.3.10.1
Section Header — Offset
0x0......................................................................................3126.3.10.2
Flexible Filter Length and Control — Offset 0x01
...........................................................3126.3.10.3
Flexible Filter Enable Mask — Offset 0x02 – 0x09
..........................................................3126.3.10.4
Flexible Filter Data — Offset 0x0A – Block
Length..........................................................3126.3.11
NC-SI Configuration Module (Global MNG Offset
0x0A)...................................................3136.3.11.1
Section Header — Offset
0x0......................................................................................3136.3.11.2
Rx Mode Control1 (RR_CTRL[15:0]) - Offset
0x1...........................................................3136.3.11.3
Rx Mode Control2 (RR_CTRL[31:16]) - Offset 0x2
.........................................................3136.3.11.4
Tx Mode Control1 (RT_CTRL[15:0]) - Offset 0x3
...........................................................3136.3.11.5
Tx Mode Control2 (RT_CTRL[31:16]) - Offset 0x4
.........................................................3146.3.11.6
MAC Tx Control Reg1 (TxCntrlReg1 (15:0]) - Offset
0x5.................................................3146.3.11.7 MAC
Tx Control Reg2 (TxCntrlReg1 (31:16]) - Offset 0x6
...............................................3146.3.11.8 MAC RX
Buffer Size - Offset 0x7
.................................................................................3146.3.11.9
NCSI Flow Control XOFF - Offset 0x8
..........................................................................3146.3.11.10
NCSI Flow Control XON - Offset 0x9
...........................................................................3156.3.12
Traffic Type Parameters – (Global MNG Offset 0xB)
.......................................................3156.3.12.1
Section Header — Offset
0x0......................................................................................3156.3.12.2
Traffic Type Data - Offset
0x1.....................................................................................3166.3.13
PHY Configuration Pointer – (Global MNG Offset
0xF).....................................................3176.3.13.1
PHY Configuration Structure
.......................................................................................317
6.3.13.1.1 PHY Configuration Section Length - Offset 0x0
.............