Integrated Injection Logic: A Bipolar LSI Technique

Integrated injection logic or merged transistorlogic is a novel bipolar circuit design approach toachieve high-density large-scale integration. As thebasic logic units it uses multicollector npn transis-tors which are powered from merged multicollectorlateral pnp transistors. IFL can be fabricated withstandard buried collector technology and is there-fore compatible with conventional bipolar circuitryon the same chip. The feature of having specialinterface circuitry-digital and/or linear-on thesame chip renders 12L a powerful LSI technique.Newer approaches to increase performance or

packing density characteristics of IFL through spe-cial device structures are now under development.One of these, Schottky FL, uses Schottky diodesin the collectors of the npn logic units to reducepropagation delay and improve the power-delayefficiency. This paper will discuss the 12L andSI'L structures and compare their features.

Integrated Injection Logic:A Bipolar LSI Technique

R. A. PedersenBell Telephone Laboratories

Introduction

Integrated Injection Logic (I2L) was disclosed atthe 1972 International Solid State Circuits Confer-ence simultaneously by C. M. Hart and A. Slob ofPhilips, The Netherlands,"2 and by H. H. Bergerand S. K. Wiedmann of IBM, West Germany.3 4

The basic logic unit is a multiple output inverterwhich is physically realized as a conventional npnmulti-emitter transistor operated in the inversemode. Base drive to the npn inverters is supplied bymulticoflector lateral pnp current source transistors.

The emitter of the pnp transistor(s) is referred to asthe injector, and a single injector typically distri-butes base drive to many npn logic units. The simpli-city of the structure is demonstrated in its imple-mentation, in which all transistors-npn and pnp-are formed in a single n-type region into which arediffused p-type (conventional npn base) regions andan n + -type (conventional npn emitter) regions.The outputs of I2L units may be "wire ANDed"

with outputs from other units for NAND implemen-tation of logic functions.The efficiency of layout of logic circuits stems

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from the unit simplicity: no wiring, except the injec-tor line, is required for the completion of a poweredlogic unit; therefore, all signal wiring is of an inter-cell variety.The basic F2L implementation in SBC technology

results in good power-delay efficiency (-lpJ), but islimited in propagation delay to greater than 20 or30 ns/stage. Schottky F2L utilizes the same efficientlayout approach but has an advanced processingtechnique to improve delay characteristics at thesame power levels. Delays of 10-15 ns/stage arereadily realized in Schottky F2L.

TKIDI 1r ,------ OUTPUTSlPru I

Figure 1. Logic unit implementation

A. "Wire AND" followed by inversion

B. NAND logic diagram

Figure 2. NAND logic implementation

February 1976

2L Logic Unit

The F2L logic unit, shown schematically in Fig-ure 1, is a single inverter implemented as a multi-collector npn transistor (a conventional multi-emittertransistor operated inversely). Base drive to the npnlogic unit is supplied from the collector of a lateralpnp transistor operating in a current source mode,whose emitter is referred to as the injector. A multi-plicity of npn inverters can be powered from a singlepnp emitter, the injector, which distributes currentto all units which form its multicollectors. Uniforminjection by the pnp and npn emitter junctions ensureseven current distribution to their respective multiplecollectors. High npn inverse current gain (conven-tional forward gain) prevents current robbing4 fromone output by adjacent saturated outputs, a problemcommon to schematically similar DCTL circuits.NAND logic implementation is achieved by the wireANDing of outputs from the appropriate logic unitsat the input of another unit, as shown in Figure 2.That unit then performs the inversion and makesthe NAND functions available at its multiple outputsto be similarly wire ANDed at the next inverter.Each logic unit output is generally restricted to

driving only one logic unit input. That may, how-ever, be driven from outputs of many units. Therestriction on each output means that for correctlogical operation the current gain of each collector,On, must be greater than 1. For reasons of speedmargins and noise immunity On 2 is usually imposedon the logic unit. This ,Bn is easily achieved in mostconventional npn integrated circuit processes.

12L Device Structure

The logic unit can be implemented in standardburied collector (SBC), non-gold doped, bipolar inte-

'A*B grated circuit technology. Implementation in asimplified technology, which does not include then-type buried collector plug diffusion and the p-typeisolation diffusion; is actually sufficient for logic,and simple input-output buffers may be fabricatedwith the logic in this form. However, the full SBCprocess may be advantageous to allow flexibility inthe incorporation of other circuitry on the same chip.Figure 3 shows the topography and cross section

for a logic unit with fan-out = 3. The logic unit isformed in an n-type epitaxial layer over an n+ sub-strate or buried layer. Three selective diffusions areused in the formation of the unit. A p-type basediffusion forms the emitter and collector of thelateral pnp transistors as well as the npn bases. Ann +-type collector contacting diffusion compensatesthe base diffusion where they intersect, electricallyseparating the logic units and forming the multi-collectors of the lateral pnp transistor. An n+ emit-ter diffusion forms the outputs of the vertical npntransistor. Standard contact window and metaliza-tion operations complete the process. Note thatbecause of the merging of the transistors in the unitno intracell wiring is required, and all wiring is ofthe intercell variety passing directly over the unit.

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1-

+

41+

I I

L11I I1+1+

CROSS SECTION

Figure 3. Injection logic basic unit

The D-type flip-flop, wired in toggle configuration(Figure 4), exemplifies layout technique. The multiple-output and conventional NAND logic diagrams areshown for clarity, although in practice no logic dia-gram conversion is required. The logic units abutone another adjacent to the injector. The "X" and"O" indicate an output or input, respectively,either of which may be placed in the six (example)available wiring channels.

Packing Density of 12L

The high packing density characteristic of F2L is aresult of the following factors:

a) only M + 1 contacts are required per gate(M = fan-out);

b) complete absence of diffused resistors;c) no intra cell wiring;d) all inter cell wiring routes easily over logic unit.These factors result in extremely dense layouts

which are amenable to computer-aided layout. Utiliz-ing lO,u line and space metal results in packingdensitiesof -85 gates/mm2 in irregular logic. Reduc-tion of the minimum tolerances to 5, results in -250gates/mm2. Regular logic can result in densities upto a factor of two greater than these.

Electrical Characteristics of 12L

F2L units are unique in their freedom from depend-ence on resistors. All units are powered throughlateral pnp transistors, and the current that reacheseach unit is the total injector current, multiplied bythe a of the lateral pnp and divided by the number ofunits associated with the injector. This means that asingle design can be operated over a wide range ofcurrents-and therefore speeds-by simply alteringthe total current into the injector. A practical rangeof operation for a single unit design can easily extendfor 3 or 4 orders of magnitude (e.g., -10-8A to _10-4A)or more, depending on the details of the process.The speed-power product associated with the operat-ing power level is typically of the order 1 pJ with aminimum delay in the 20-30 ns range for the conven-tional bipolar process.

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A. Multiple output NAND logic diagram

Q

B. Conventional NAND logic diagram

CLK R 1 3 4 2 6 5CLK X X

V- -----INJECTOR \

C. Corresponding layout

.1Figure 4. D-type flip-fiop

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Figure 5 shows a typical power delay characteristicfor F2L. The linear region where delay and power maybe traded off one-for-one is known as the extrinsicregion of operation. In this region the delay is deter-mined by charging current, parasitic capacitances,and voltage swing. As the current is increased, theintrinsic region of operation is reached where thedelay reaches a plateau. The delay here is determinedby diffusion capacitances which are intrinsic charac-teristics of the device geometry and doping profiles.The delay in this region is a measure of the frequencyresponse of the I2L unit.

Applications of 12L

In the full SBC process, F2L boasts the capabilityof having conventional linear or digital circuitry onthe same chip. This ability is important in manyapplications in minimizing silicon costs through theelimination of peripheral parts which may be needed

U)

z0

I'd

to-5

10-6

to-7

to-B 1o07 Io-6 o_-5 1o-4POWER/UNIT (WATTS)

Figure 5. Average propagation delay vs power per unit

BUFFERS LOGIC

11 /11

Figure 6. Typical LSI chip part

February 1976

- (VCC= .OV)

MEASUREMENT-SLICEA646723-H UNIT# 199 STAGE RING OSCILLATOR 0FAN OUT=5FAN IN = iUNUSED OUTPUTS GROUNDEDCIRCUIT SIMULATION USING FAN OUT=5

1.0 pJ PARAMETERS o

I I .

to-2

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to surround a MOS LSI part to make it fully systemcompatible. Figure 6 shows a part typical of an P2LSBC LSI chip. This part has 250 P2L gates plus 5vinterface circuitry including TTL I-0, several 3OmAdrivers, and a Schmidt trigger'clock input.A simpler process can also be used to make I2L. In

this version, the conventional buried layer and isola-tion diffusions are eliminated. The P2L is then fabri-cated on n-epitaxy over an n+ substrate or even onn-type bulk. This simpler process form of P2L isapplicable to large LSI parts where cost is criticaland noncritical interface requirements to other partsof the system exist.

Schottky 12L (SI2L) Logic Unit

Schottky P2L6 is an extension of P2L which resultsin greater power delay efficiency and lower propaga-tion delays. Schottky diodes are formed in the multi-collectors of the npn transistor as proposed byAgraz-Guerena and Fulton.5"6 The structure hasreduced capacitance, lower signal swing, and lowerintrinsic delays than standard P2L.Figure 7 shows the schematic representation of

SI'2L in comparison to conventional P2L. The diodesschematically perform a level shifting functionwhich results in better power delay efficiency.However, they also perform a charge control func-tion, which will become clearer later.

S12L Device Structure

The topography and cross section of an SI2L unitwith fan-out = 3 are shown in Figure 8. As in con-

Icc

INPUT OUTPUTS

'cc

A. Conventional 12L

INPUT *°OUTPUTS.- ~~~-

'cc

B. Schottky 12L

Figure 7. Conventional and Schottky 12L units

ventional P2L, the unit is fabricated in an n- typeepitaxial layer on an n+ substrate or, in the isolatedprocess, on a buried layer. The n+ collector contact-ing diffusions and p-type extrinsic base -diffusionsare conventional. The difference is in the intrinsicbase for the npn transistor, which is ion implantedwith boron to form a buried p-type region on top ofwhich lies in an n- region. When the conventionalcontact window and metalization processes areapplied, a Schottky diode is formed in series witheach SP2L unit collector. Also, since the SP2L collec-tors are n- rather than n+ as in conventional PL,the collector-base capacitances are'reduced, result-ing in power delay efficiency improvements in addi-tion to those arising from reduction in signal swings.The intrinsic delay of SP2L is also improved by the

addition of the Schottky diodes. This is a result of aparasitic pnp acting on the npn where the emitter,base, and collector of the pnp are the base, collector,and Schottky diode of the npn respectively. The pn(Schottky) p remains in the active region of operationand controls the charge profile in the collector of thenpn, reducing the intrinsic delay.

Electrical Characteristic of S12L

The common emitter characteristics of an SPLdevice with Pd2Si Schottky diodes is' shown in Fig-ure 9. Note that the characteristic is like that of annpn transistor with a Schottky diode in series withits collector except for the negative current shownwith applied voltages less than a diode drop. In thatregion the negative current results from the parasiticpn (Schottky) p transistor action.Figure 10 shows that propagation delay vs power

for SPL and PL for the same device geometrics.

INPUT OUTPUTS

|N+L N), N-I(I rON IMPLANTED INTRINSIC BASE I

CRS SN+

CROSS SECTION

Figure 8. Schottky 12L topography and cross section

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Figure 9. Common emittercharacteristics withPd2Si Schottky

Note that the SF2L gives about a factor of two im-provement in speed in both the extrinsic and intrinsicregions of operation. Practical LSI delays of 10-15 nsare believed achievable with SIFL.

tob6

IPI10-7

1o-8 -10-7 10-6 10-5 10-4

GATE CURRENT (A) OR POWER/VOLT (W/V)

References

1. C. M. Hart and A. Slob, "Integrated Injection Logic-A NewApproach to LSI," ISSCC Dig. Tech. Papers, pp. 92-93,February 1972.

2. , "Integrated Injection Logic-A New Approach toLSI," IEEE J. Solid State Circuits, Vol. S.C. 7, pp. 346-35 1,October 1972.

3. H. H. Berger and S. K. Wiedmann, "Merged-TransistorLogic-A Low-Cost Bipolar Logic Concept," ISSCC Dig.Tech. Papers, pp. 90-91, February 1972.

4. , "Merged-Transistor Logic-A Low-Cost BipolarLogic Concept," IEEE J. Solid State Circuits, Vol. S.C. 7,pp. 340-346, October 1972.

5. J. Agraz-Guerena and A. W. Fulton, private communication.

6. F. W. Hewlett, Jr., "Schottky I2L," IEEE J Solid StateCircuits, October 1975.

10-3

Figure 10. Average propagation delay vs gate current or

power/volt for both conventional and Schottky i2L

Summary

F2L is a bipolar LSI circuit technique whichachieves high packing density and good power-delayefficiency using conventional bipolar processing.Schottky 12L uses the principles of IFL and the prop-erties of ion implantation to achieve improved per-

formance capabilities. F2L has caused rethinking inthe semiconductor industry and provides the firstviable bipolar alternative to MOS for LSI in futuresystem designs. a

Richard A. Pedersen is supervisor of theBipolar SIC Development Group doing de-

velopment of bipolar LSI structures andH40 , i 0 circuits at Bell Laboratoies in Allentown,

Pennsylvania.After doing research work on supercon-

ducting thin films at Minnesota, he joinedLk Bell Laboratories in 1964, where he was

engaged in high-frequency transistor devel-opment and development of silicon integrated

circuits. In 1968 he was promoted to supervisor of the BipolarDigital Integrated Circuits Group.In 1970 he joined Honeywell, Inc., at the Solid State Elec-

tronics Center in Minneapolis, where he was involved in designof bipolar memory and high speed logic. In 1971 he rejoinedBell Labs.Pedersen received the BSEE and MSEE degrees from the

University of Minnesota in 1962 and 1964.

February 1976

X CONVENTIONAL 12L 6723-H0 SCHOTTKY 12L SIL-53 (Pd2Si)

UNUSED OUTPUTS FLOATING

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