Integrated Device Scheduling and Processor Voltage Scaling for System-wide Energy Conservation

Integrated Device Scheduling and Processor Voltage Scaling for System-wide Energy Conservation

Hui Cheng, Steve GoddardComputer Science and Engineering

Univ. of Nebraska-Lincoln

Outline Background Motivation and problems I/O-based DPM Optimal CPU speed SYS-EDF Evaluation

Background Power management

Dynamic power management Task scheduling

EDF+SRP Preemptive scheduling

I/O device scheduling Inter-task device scheduling

Periodic task definition

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Motivation Previous research has focused on:

Energy conservation for the processor Much work has been done on DVS Ignores energy conservation of I/O devices

Energy conservation for I/O devices Most techniques cannot be applied to hard real-time

systems Ignores CPU energy conservation

System-wide energy conservation is needed! How to integrate DVS and DPM?

Device power model

Busy

Active

Idle

High transition overhead

Serving I/O reqs

Ready to

serve

Proportional to the job execution time

High power state

Low power state

Current I/O-based DPMs

System energy

I/O device energy

Processorenergy

Non-preemptive task scheduling

LEDES

MUSCLES

EDS

MDO

Preemptive task scheduling

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Offline scheduling

Online scheduling

ASD Aggressive shut down

Include the transition delay in the WCET Sufficient schedulability condition

Problems: Reduces schedulability for some systems Does not consider the energy penalty

associated with power state transitions

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CEA-EDF

1

2

ON

OFF

ON

OFF

1T

2T

0 2 4 8 146 10 12 2016 18 22 24

Larger than BE

CEA-EDF vs. EASD

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10.35

0.4

0.45

0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

System utilization

Nor

mili

zed

Ene

rgy

Sav

ing

Mean energy saving under different system utilizations

CEA-EDFEASD

CPU power model Dynamic power consumption

Leakage power consumption

Total power consumption

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Optimal speed CPU speed is critical to achieve system-wide

energy conservation Lowest speed:

Good for saving the dynamic power consumption of CPUs

Highest speed: Good for the energy conservation of devices Good for reducing leakage energy consumption of

CPUs

Optimal speed: the speed to balance the energy consumption of all components.

Optimal speed (cont’d) Active device set

Containing all devices that are in the active state at current time.

Optimal speed Energy efficiency scale:

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Energy efficiency scale examples

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10.5

1

1.5

2

2.5

3x 10

-9

Normalized processor speed

Ene

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effic

ienc

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ale

Mobile RAMMobile RAM+SimpleTech flashMobile RAM+MaxStream wireless module

ExampleActive device set

…

Opt speed 0.4 0.6 0.9 …

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0 2 4 8 146 10 12 2016 18 22 24

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0.9

CPU speed

SYS-EDF The DVS scheduling is based on the

DS algorithm proposed in [1]. High speed

Low speed

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SYS-EDF (cont’d) Use CEA-EDF to schedule devices Keep track of the active device set and

compute/adjust the optimal speed. The processor speed is never set below

the optimal processor speed. Same techniques were used in [2][3]

Only scheduled at scheduling points

Evaluation

0-0.1 0.1-0.2 0.2-0.3 0.3-0.4 0.4-0.5 0.5-0.6 0.6-0.7 0.7-0.8 0.8-0.9 0.9-10

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

System utilization

Nor

mili

zed

Ene

rgy

Sav

ing

Mean energy saving under different system utilizations

CEA-EDFSYS-EDFDS+CEA-EDFDS

Conclusion and future work SYS-EDF = I/O based DPM+DVS+Opt speed Provide more energy savings with respect t

o: DVS-alone I/O based DPM alone The straightforward integration of DVS and DPM

Current and future work Consider the device transition delay in the com

putation of optimal speed. Consider the overhead of adjusting CPU voltage Extend to other task models

References [1] Zhang, F., Chanson, S., Processor Voltage Scheduling for Real-Ti

me Tasks with Non-Preemptible Sections. [2] Jejurikar, R., Pereira, C., Gupta, R., Leakage aware dynamic volta

ge scaling for real-time embedded systems. [3] Zhuo, J., Chakrabarti, C., System-Level Energy-Effcient Dynamic

Task Scheduling. [4] Swaminathan, V., Chakrabarty, K., and Iyengar, S.S., Dynamic I/O

Power Management for Hard Real-time Systems. [5] Swaminathan, V., and Chakrabarty, K., Pruning-based, Energy-o

ptimal, Deterministic I/O Device Scheduling for Hard Real-Time Systems.

Transition overhead

OFF

1T

2T

0 2 4 8 146 10 12 16 2018 22 24

1,1J

1,2J

26 28 30

2,1J

k

Missed deadline

1,2J

0 2 4 8 146 10 12 16 2018 22 24 26 28 30

ON

CEA-EDF vs. EASD (cont’d)

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

System utilization

Nor

mili

zed

Ene

rgy

Sav

ing

Mean energy saving under different system utilizations

CEA-EDFEASD

EASD Utilize job slack to further save

energy

1T

2T

0 2 4 8 146 10 12 16 2018 22 24

1,1J

1,2J

Device dependent

system slack

Device slack

26 28

2,1J 3,1J

Device access delay

Device dependent

system slack

Device access delay

k