Adapted from J. Rabaey et al, Digital Integrated Circuits 2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009 1 Integrated Circuits Implementation Choices Integrated Circuits Implementation Choices Full-Custom Standard Cells (with compiled cells and macro cells) Cell-based Mask programmable (Gate Arrays) Pre-wired (FPGA's) Array-based Semicustom Digital Circuit Implementation Approaches ASIC FPGA Adapted from J. Rabaey et al, Digital Integrated Circuits 2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009 2 ASIC ASIC Semicustom Semicustom Design Flow Design Flow RTL (HDL es: VHDL) Logic Synthesis Floorplanning Placement Routing Tape-out Circuit Extraction Pre-Layout Simulation Post-Layout Simulation System specification Design Iteration Design Iteration Libreria di celle
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Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
6CellCell--based (or standard cells): core area and based (or standard cells): core area and pin number depend on the applicationpin number depend on the application
Pad
Core area
die
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Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
7CellCell--based (or standard cells) layoutbased (or standard cells) layout(old generation)(old generation)
Routing channel requirements arereduced by presenceof more interconnectlayers
Functionalmodule(RAM,multiplier, …)
Routingchannel
Logic cellFeedthrough cell
Row
s of
cel
ls
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
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Standard Cell Standard Cell –– The New GenerationThe New Generation
Cell-structurehidden underinterconnect layers
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Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
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LibreriaLibreria di Standard Cellsdi Standard Cells
q Esempio: libreria AMS 0.35um 250 celle elementari§ Celle combinatorie:
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
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Standard Cell Standard Cell -- ExampleExample
3-input NAND cell(from ST Microelectronics):C = Load capacitanceT = input rise/fall time
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Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
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Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
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Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
13Compiled cellsCompiled cells
256×32 (or 8192 bit) SRAMGenerated by hard-macro module generator
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
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““Soft” Soft” MacroModulesMacroModules
Synopsys DesignCompiler
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Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
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““Intellectual Property”Intellectual Property”
A Protocol Processor for Wireless
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
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CellCell--based designbased designü Libreria di celle ottimizzate fino al livello di layoutü Dimensioni del die e numero I/O specifici del progettoü Possono essere inseriti moduli full-custom e macro
(es: memorie, moduli aritmetici) ottimizzate fino al livello del layout (macrocell-based design)
elevate prestazioniû Devono essere generate tutte le maschere
elevati costi NRE
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Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
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The “Design Closure” ProblemThe “Design Closure” Problem
Courtesy Synopsys
Iterative Removal of Timing Violations (white lines)
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
18Integrating Synthesis with Integrating Synthesis with Physical DesignPhysical Design
Physical SynthesisPhysical Synthesis
RTL (Timing) Constraints
Place-and-RouteOptimization
Place-and-RouteOptimization
Artwork
Netlist with Place-and-Route Info
MacromodulesFixed netlists
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Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
19Esempi
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
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Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
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Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
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Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
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Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
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Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
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Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
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Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
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Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
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Data path: blocco critico per le prestazioni del sistema. Metodologia di progetto: full-custom
Unità di controllo: FSM Flusso a celle standard
Memorie: strutture regolari.Specifica: ottimizzazione della cella elementare per rendere massima la densità integrazione e minimo iltempo di accesso.Metodologia full-custom e compilatori
Risc a 5 stadi di pipeline
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Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009
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A Protocol Processor for Wirelesscompilatori di moduli di memoria
Microprocessore embedded e acceleratori HWStandard cell e utilizzo di IP