integrated circuit Logic Effort

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CMPEN 411

g a rcu sSpring 2011

Lecture 12: Logical Effort

[Adapted from Rabaeys Digital Integrated Circuits, Second Edition, 2003J. Rabaey, A. Chandrakasan, B. Nikolic]

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PMOS/NMOS Ratio Effects

5x 10-11

= (W/Lp)/(W/Ln)

4.5

pLH tpHL

of 2.4 (= 31 k/13 k)gives symmetrical

4 tp response

3.5 o . o . g vesoptimal performance

1 2 3 4 5

= (W/Lp)/(W/Ln)



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Example of Inverter Chain Sizing

In Out

CL = 8 Cg,1Cg,1

CL/Cg,1 has to be evenly distributed over N = 3 inverters

F = CL/Cg,1 = 8/1

f =



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Heads up

z Logical Effort

- Reading assignment textbook pp251-257, and handout

Next lecture

z Designing energy efficient logic

- ea ng ass gnment a aey, et a , 5.5 . .



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History

First proposed by Ivan Sutherland and Bob Sproull in

1991

z Logical Effort: Designing for Speed on the back of anEnvelope, IEEE Advanced Research in VLSI, 1991

Microsystems

Gain-based s nthesis based on Lo ical effort

z Implemented in IBMs logic synthesis tool BooleDozer

z Also adopted by Magmas logic synthesis tool



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Inverter Delay

, L,z Cint : intrinsic - diffusion and Miller effect (Cg)

z Cext : extrinsic - wiring and fanout

tp = 0.69 Req Cint (1 + Cext/Cint) = tp0 (1 + Cext/Cint)=0.69(ReqCint + ReqCext)

z where tp0 = 0.69 Req Cint is the intrinsic (unloaded) delay of thegate



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Logical Effort Delay Model

Delay of logic gate has two components

z d = f + p

z f: effort delay

z p: parasitic delay

f=gh g: logical effort

h: electrical effort = Cout/ Cin (the ratio ofoutput capacitance to input capacitance)



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Gate Delay Components

Lo ic

in

Cout

Split delay of logic gate into three components

=

Gate

Logical Effort

z Complexity of logic function (Invert, NAND, NOR, etc)

z Define inverter has logical effort = 1

z Depends only on topology not transistor sizing

z Ratio of output capacitance to input capacitance Cout/Cin

Parasitic Delay


z Intrinsic delay

z Independent of transistor sizes and output load


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Computing Logical Effort

,load, complex gates have to work harderthan an inverter to produce a similar

z the logical effort of a gate tells how muchworse it is at producing an output current thanan inverter how much more in utcapacitance a gate presents to deliver thesame output current)

Logical effort is the ratio of the input

capacitance of a gate to the input

ca acitance of an inverter deliverin

the same output current

Defined to be 1 for an inverter



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Computing Logical Effort

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Logic Gate Delay

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Logic Gate Delay

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Example

Estimate the delay of an inverter driving 4 identicalinverter: (FO4)

g= h= p= d=

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Example

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Path Delay of Complex Logic Gate Network

ota pat e ay t roug a com nat ona og c oc

tp = dj = pj + hj gj

e m n mum e ay roug e pa e erm nes a eac s age

should bear the same gate effort

h1g1 = h2g2 = . . . = hNgN

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Application of Logical Effort

Alternative logic structures, which is the fastest?

F = ABCDEFGH

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Application of Logical Effort

Alternative logic structures, which is the fastest?

F = ABCDEFGHg1=10/3 g2=1

g1=4/3 g2=5/3 g3=4/3 g4=1 g1= g2=5

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Review: Design Technique 4

Isolating fan-in from fan-out using buffer insertion

CL L

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Questions

d = gh+p

Why logical effort g is independent of transistor sizing?

How to calculate parasitic delay p ? Why it is independent of

transistor sizing?

How to calculate single delay parameter:

What if the ratio of p-type to n-type transistor widths changes?

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From Elmore model to Logical Effort Model

RR

CinCin CpCp CoutCout

= += += R*Cout + R*Cp= R*Cout + R*Cp= RCin*(Cout/Cin)+R*Cp= RCin*(Cout/Cin)+R*Cp

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pp


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Parasitic Delay

Main cause is drain capacitancesCgateP

ese sca e w rans s or w

so it is independent of transistorsizesCdrainPR

For inverter:

Parasitic Delay ~= 1.0 CdrainN

RonN

CgateN

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How to calculate single delay parameter:

aracter ze process spee w t s ng e e ay parameter:

~= 15 ps for 0.18um ~=20 ps for 0.25 um

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Inverter Chain Delay

For each stage:

Delay = Logical Effort x Electrical Effort + Parasitic Delay

= 1.0 (definition) x 1.0 (in = out) + 1.0 (drain caps)

=

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Multistage Logic Network

Path logical effort, G = gi (gi = L.E. stage i)

Path electrical effort, H = Cout/Cin (hi = E.E. stage i)

aras c e ay, = pi pi = . . s age

Path effort, F= fi = gi hi

= +

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Paths that Branch

Consider paths that branch:

G =H =

15 90

GH =15

901 =

h2 =

F = GH?

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Paths that Branch

No! Consider paths that branch:

G = 1H = 90 / 5 = 18

15 90

GH = 1815

901 = =

h2 = 90 / 15 = 6

F = g1g2h1h2 = 36 = 2GH

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Add Branching Effort

Branching effort:

pathoffpathon

C

CCb

+=

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Multistage Networks

Path electrical effort: H= Cout/Cin

Branching effort: B = b1b2bN

a e or : =

Path delay D= F+P=GBH+P

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Optimal Number of Stages

Cin

Minimum delay when:

- ~

ou

. .

Fan-out-of-four (FO4) is convenient design size (~5)

FO4 delay: Delay of

inverter driving fourcopies of itself

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Method of Logical Effort

Compute the path effort: F= GBH

Find the best number of stages N~ log4 F

Compute the stage effort f= F1/N

Sketch the ath with this number of sta es

Work either from either end, find sizes:

Cin= Cout*g/f

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Example of Inverter (Buffer) Staging

1

p

1 64 65L = g,1g,1 =

1 8

CL = 64 Cg,1Cg,1 = 1

CL = 64 Cg,1Cg,1 = 1

1

CL = 64 Cg,1Cg,1 = 1

1 2.8 8 22.6 4 2.8 15.3

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Summary

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Next Lecture and Reminders

z Designing energy efficient logic

- Reading assignment Rabaey, et al, 5.5 & 6.2.1

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integrated circuit Logic Effort

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