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1
INTEGRATED-CIRCUIT TECHNOLOGY
1. Processing Steps
1.1. Photolitography
1.2. Oxidation
1.3. Layer Deposition
1.4. Etching
1.5. Diffusion
1.6 Backend: assembly, test
2. Bipolar Technology
3. CMOS Technology
0. Silicon crystal growth and wafer preparation
2
CRYSTAL GROWTH
• Czochralski Process is a
Technique in Making
Single-Crystal Silicon
• A Solid Seed Crystal is
Rotated and Slowly
Extracted from a Pool of
Molten Si
• Requires Careful Control
to Give Crystals Desired
Purity and Dimensions
3
Wafer Slicing & Polishing
The silicon ingot is grown and individual wafers are sliced.
The silicon ingot is sliced into
individual wafers, polished, and
cleaned.
silicon wafer
p+ silicon substrate
4
Photoresist Coating Processes
p- epi
p+ substrate
field oxide
photoresist
PhotoresistsNegative Photoresist *
Positive Photoresist *
Other Ancillary Materials (Liquids)Edge Bead Removers *
Anti-Reflective Coatings *
Adhesion Promoters/Primers (HMDS) *
Rinsers/Thinners/Corrosion Inhibitors *
Contrast Enhancement Materials *
DevelopersTMAH *
Specialty Developers *
Inert GasesAr
N2
5
Exposure Processes
p- epi
p+ substrate
field oxide
photoresist
ExposeKr + F2 (gas) *
Inert GasesN2
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1. Photolitography – Basic Concept
Photolitography – Basic Concept
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Photolitography using positive photoresist
8
The simplest method of producing an oxide layer
consists of heating a silicon wafer in an oxidizing
atmosphere.
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Oxidation of the silicon surface
10
6min20min1.7hWet O2
15min40min1.7h6h30hDry O2
1200°C1100°C1000°C900°C800°CAmbient
Times required to grow 0.1µµµµm of oxide on (III) silicon
Silicon Melting Point, 1410°C
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Selective SiO2 growth, using local oxidation
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Vapor deposition. PVD (a) and CVD(b).
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Chemical Vapor Deposition (CVD) Dielectric
* High proportion of the total product use
CVD DielectricO2
O3
TEOS *
TMP *
TEOSSource
LPCVDChamber
TransferChamber
Gas Inlet
Exhaust
RF Power
Wafer
MeteringPump
Inert MixingGas
Process Gas
Vaporizer
DirectLiquid
Injection
n-w ell
p-channel transistor
p-w ell
n-channel transistorp+ substrate
Metal 1insulator layer 2
Chemical Reactions
Si(OC2H5)4 + 9 O3 → SiO2 + 5 CO + 3 CO2 + 10 H2O
Process Conditions (ILD)
Flow Rate: 100 to 300 sccm
Pressure: 50 Torr to Atmospheric
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Epitaxy and mechanisms of
defect formation in the epitaxial layer
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Epitaxial Silicon DepositionGasInput Lamp
Module
QuartzLamps
Wafers
Susceptor
Exhaust
* High proportion of the total product use
Chemical Reactions
Silicon Deposition: HSiCl3 + H2 → Si + 3 HCl
Process Conditions
Flow Rates: 5 to 50 liters/min
Temperature: 900 to 1,100 degrees C.
Pressure: 100 Torr to Atmospheric
silicon wafer
p- silicon epi layer
p+ silicon substrate
Dopants
AsH3
B2H6
PH3
Etchant
HCl
Carriers
Ar
H2 *
N2
Silicon Sources
SiH4
H2SiCl2HSiCl3 *
SiCl4 *
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Wet etching.
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Dry etching.
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Conductor Etch
* High proportion of the total product use
EtchChambers
Cluster ToolConfiguration
TransferChamber
Loadlock
Wafers
RIE Chamber
TransferChamber
Gas Inlet
Exhaust
RF Power
Wafer
p+ substrate
p-w ell
n-channel transistor
n-w ell
p-channel transistor
source-drain areas
gate linew idth
gate oxide
Polysilicon EtchesHBr *
C2F6
SF6 *
NF3 *
O2
Aluminum EtchesBCl3 *
Cl2
DiluentsAr
He
N2
Chemical Reactions
Silicon Etch: Si + 4 HBr → SiBr4 + 2 H2
Aluminum Etch: Al + 2 Cl2 → AlCl4Process Conditions