1 ATMT 4213 Advanced Materials Testing and Evaluation 1.0 Introduction: What is Semiconductor Device? [1] Semiconductor devices are electronic components that made by semiconductor materials. These semiconductor materials have electrical conductivity that behaves intermediately between a conductor and an insulator. Silicon is an example of common materials that used for the manufacturing of such devices since it is one of the most abundant resources in the earth. Generally, there are two types of semiconductors, which are intrinsic semiconductor and extrinsic semiconductor. An intrinsic semiconductor is a pure semiconductor without any doping atoms within its crystal lattice. Hence, the electrical conductivity is much poorer compare to an extrinsic one. In an intrinsic semiconductor such as silicon, the crystal structure is covalently bonded due to the sharing and pairing of valence electrons among the atoms. The absence of “free” or mobile electrons causes it is not able to transmit electrical current in original states. But when the silicon is exposed to certain external factors such as temperature and light, the valance electrons will be excited out of the bonds and causes the creation of holes. Holes are the vacant positions left by the freed electrons. As a result, the holes and the freed electrons act as charge carriers and are able to conduct current. There is an energy gap needs to be achieved in order to excite the electrons and holes.
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ATMT 4213 Advanced Materials Testing and Evaluation
1.0 Introduction: What is Semiconductor Device? [1]
Semiconductor devices are electronic components that made by semiconductor
materials. These semiconductor materials have electrical conductivity that behaves
intermediately between a conductor and an insulator. Silicon is an example of
common materials that used for the manufacturing of such devices since it is one of
the most abundant resources in the earth. Generally, there are two types of
semiconductors, which are intrinsic semiconductor and extrinsic semiconductor.
An intrinsic semiconductor is a pure semiconductor without any doping atoms
within its crystal lattice. Hence, the electrical conductivity is much poorer compare to
an extrinsic one. In an intrinsic semiconductor such as silicon, the crystal structure is
covalently bonded due to the sharing and pairing of valence electrons among the
atoms. The absence of “free” or mobile electrons causes it is not able to transmit
electrical current in original states. But when the silicon is exposed to certain external
factors such as temperature and light, the valance electrons will be excited out of the
bonds and causes the creation of holes. Holes are the vacant positions left by the freed
electrons. As a result, the holes and the freed electrons act as charge carriers and are
able to conduct current. There is an energy gap needs to be achieved in order to excite
the electrons and holes.
The electrical conductivity of intrinsic semiconductor can be greatly improved
by the adding of impurities through doping process. This doped semiconductor is also
known as extrinsic semiconductor. The difference in the number of valence electrons
between the doping material, or dopant and host semiconductor will determine the
type of doped semiconductor. If a doped semiconductor contains more holes after
doping, it is called ‘p-type’ and if it contains excess free valence electrons, it is called
‘n-type’. P-type semiconductor can be formed by doping with acceptor atoms such as
Boron whereas N-type is doped with donor atoms such as Phosphorus and Arsenic.
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(a) (b)
Figure 1.0: (a) P-type semiconductor that is formed by the doping of Boron atoms. The Boron
atom creates a hole. (b) N-type semiconductor that is formed by the doping of phosphorus
atoms. The phosphorus atom creates an extra electron.
When a p-type semiconductor region is placed adjacent to an n-type region,
they form a region of contact which is called a p-n junction. A diode is a
semiconductor devices made from a single p-n junction. The diode functions as a two
terminals device that conducts in only single direction. Combinations of such
junctions are used to make transistors and other semiconductor devices whose
electrical behavior can be controlled by appropriate electrical stimuli. These
transistors can be further combined with other active components along with passive
ones on a single chip of silicon to form an integrated circuit (IC). IC is a complex
electronic device design to perform certain functions depending on controlling
signals.
Figure 1.1: (a) Diode (inside the red circle) that mounted on the circuit board; (b)
Transistors in various types and forms; (c) An integrated circuit (IC).
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2.0 Manufacturing Process of Semiconductor Devices
Semiconductor devices consist of two major parts: a tiny and fragile silicon chip (die)
together with a package that intended to protect the internal chip. For an integrated
circuit (IC), diodes and transistors are embedded within the silicon chip. The
manufacturing process of all semiconductor devices is basically almost similar. But a
more complex multi-step processes will be involved if the device is designed for a
higher level of functional purpose such as IC.
Figure 2.0: The structure of a semiconductor device.
The manufacturing flow for a semiconductor device is divided into two
phases, which are front-end manufacturing and back-end manufacturing. In front-end
phase, it involved the wafer fabrication process that is extremely sophisticated and
intrinsic in nature to produce the silicon chip. Afterward, the manufactured silicon
chip will be subjected to wafer probing test to ensure its quality and reliability meets
with the required specification. In back-end phase, good chips (die) are assembled
into package via a high precision and automated process. A final test will be done on
the completed semiconductor device before packaging and shipping to customer. [2]
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Figure 2.1: The manufacturing of a semiconductor device can be divided into frond-end
processing and back-end processing.
2.1 Logic Circuit Design and Photomask Creation [3]
Logic circuit design is a very important part for the manufacturing of semiconductor
devices. It must be done before any manufacturing processes could starts. The
expected functions and performances of device are determined and drawn into a logic
circuit diagram. Stimulations are performed multiple times to test the circuit’s
operation. If there is no any faulty with the operations, the actual layout pattern for the
devices and interconnects is designed by using CAD software. This actual layout is
used to create the mask pattern of devices.
The mask pattern functions as a photomask to transcribe the design onto the
surface of wafer during front-end processing. Photomask is simply a copy of designed
circuit pattern that drawn on a glass plate coated with a metallic film. Light is able to
pass through the glass plate, but the metallic film does not. The circuit pattern is
exposed on the photomask by using a state-of-the-art mask drawing system. Due to
the increasingly high integration and miniaturization of the pattern, the size of the
photomask is usually magnified four to ten times the actual size, depending on the
irradiation equipment.
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Figure 2.2: Photomask is used to transcribe the logic circuit design onto the surface of wafer.
2.2 Front-end Processing [2]
Wafer fabrication is carried out in a wafer fab which is isolated from the outside
environment and contaminants. Wafer fab is a cleanroom that air cleanliness is one
million times better than the air we normally breathe in a city, or some orders of
magnitude better than the air in a heart transplant operating theatre. Silicon chip could
be easily spoiled or failed due to the presence of contaminants such as particles,
metallic impurities, organic contaminants, native oxides and electrostatic discharge.
Silicon substrate (wafer) that produced through wafer preparation will
undergoes a series of multi-step processes which consists of deposition,
photolithography, etching, diffusion and ion implantation. Some of the process is
repeated several times at different stages of process. Each step adds a new layer to the
wafer or modifies existing ones. These layer forms the element of individual
electronic circuits. The order shown in Figure 2.3 does not reflect the real order of
fabrication process. It is depend on the predetermined logic circuit design of silicon
chip. But the process flow chart points out the overall major steps involved in the
manufacturing of a die.
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Figure 2.3: The overall flow process of frond-end processing to manufacture the die on
wafer.
2.2.1 Wafer Preparation [4]
Wafer is a thin, circular slice of semiconductor material that made from silicon ingot
with purity as high as 99.999999999% (eleven-nine) through either the Czochralski
(CZ) or the Float Zone (FZ) method. [3] It is a single-crystal silicon substrate with
near-perfect crystalline properties where the logic circuit will build within the silicon
lattice. Quartzite is a type of sand that used as the raw material for wafers. The sand
will undergoes a complicated refining process to become electronic grade polysilicon
(EGS). [5] In Czochralski method, the EGS (silicon chunks) are loaded and heated in a
crucible of furnace at temperature about 1600°C. Once the chunks of silicon are
melted, a seed crystal will be lowered into the furnace until it touches the melt. The
seed will begin to rotate and slowly retracted by CZ crystal puller from the furnace at
a controlled rate. A cylindrical, single crystal silicon ingot is grown from the
withdrawal process.
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Figure 2.4: Process of withdrawing the single-crystal silicon ingot from furnace.
The ingots will subject to a series of routine evaluation to ensure they meet the
quality requirements. It is then ground using diamond wheels to make it a perfect
cylinder with the right diameter. An etching process is done on the ingots to remove
the mechanical imperfections left by the grinding process. The cylindrical ingot will
undergoes another round of grinding to produce one or more ‘flat’ on its surface.
Once these completed, the ingots are sliced into thin wafer with a diamond saw, each
of which will be subjected to further etching to remove damage and contamination,
followed by polishing to create mirror-finish surface on the wafer. The wafer is ready
to be used as the substrate for production of chip. [6]
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Figure 2.5: The ingot is sliced into thin wafer and mirror-finished on one side of its surface.
2.2.2 Deposition
Deposition is a process to introduce a new layer of film on the silicon substrate. It
could be done through three common methods which include Thermal Growing,
Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD).
Thermal growing is a process that involved the growth of oxide layer on a
wafer by providing high purity oxygen in an elevated temperature environment. It is a
chemical reaction between silicon and oxygen that occur in a furnace. A layer of
silicon dioxide, SiO2 will be formed and adhered onto the wafer surface by the
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consumption of original wafer. The silicon dioxide is created with the purpose such as
acts as a protection layer of the device from scratches and contaminations, field
isolation (surface passivation), gate dielectric material, doping barrier and deposited
dielectric layer between metal conductor layers. [7]
Figure 2.6: The growth of oxide layer on the wafer by thermal growing process.
Chemical Vapor Deposition is a process that forms a non-volatile solid film on
a substrate from the reaction of vapor phase chemical reactants containing the right
constituents. The deposition process is done in a reaction chamber in which the
reactant gases are introduced to decompose and react with the substrate to form film.
This process is frequently used to produce amorphous and polycrystalline thin films,
deposition of silicon nitride and SiO2, and growing of single-crystal silicon epitaxial
layers. [8] Epitaxial layer is a deposited film that has the same material as the substrate,
in which functions to minimize latch-up problem as device geometric continue to
shrink and better control of doping concentrations of the devices. [7]
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Figure 2.7: Chemical Vapour Deposition (CVD) is used to produce new layer such as
polycrystalline thin films, silicon nitride, SiO2, and epitaxial layer on the wafer.
Physical Vapor Deposition normally is used in the form of sputtering to
deposit a thin film of conductive metal on the wafer. Actually this is a metallization
process that intended for creating a metal layer to electrically interconnect the various
device structures fabricated on the silicon substrate. The metal layer functions as a
bridge that completes the electric circuit. Thin-film aluminium is the most widely
used material for metallization, with the other two being silicon and SiO2. Sputtering
begins with the generation of high energy ions that used to bombard a target (source
of material for deposition). The ions will sputter or eject atoms from the target. Once
the sputtered atoms reach the substrate, they condense and from a thin metal film over
the substrate. [9]
Figure 2.8: Physical Vapour Deposition (PVD) in the form of sputtering is used to carry out
metallization process on the wafer.
2.2.3 Photolithography
Photolithography is a process that defined the pattern of depositing layers and the
doping region on the substrate. The fabrication of circuit on silicon wafer requires
several different layers. Each of the layers has different pattern where the deposition
is done one at the time on that particular surface. The doping of active regions is
carried out in very controlled amount over tiny regions of precise areas. [10]
In order to create the predetermined pattern on a layer, a layer of photoresist
material is spin-coated on the surface of the wafer. Photomask is placed over the
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photoresist-coated wafer and adjustment is made between them until correct. A
radiation device called stepper is used to radiate UV light through the photomask on
the coated surface of wafer. The exposure causes the designed pattern on photomask
is transcribed onto the wafer surface. Since the photomask is four to ten times larger
than the actual sizes of the circuit, the stepper lens must be adjust to ¼ to 1/10
magnification before being projected onto the wafer. The radiation of UV light causes
a chemical changes to the photoresist material. [3]
Figure 2.9: Schematic diagram of photolithography process.
After exposure, the photoresist layer is subjected to development that destroys
unwanted areas of the photoresist layer, exposing the corresponding areas of the
underlying layer. Depending on the resist type, the development stage may destroy
either the exposed or unexposed areas. The areas with no resist material left on top of
them are then subjected to additive or subtractive processes, allowing the selective
deposition or removal of material on the substrate. The unwanted areas in the
photoresist are dissolved by the developer during development. [10] There are two type
of possibility for the resulting photoresist layer after development, which are positive
photoresist and negative photoresist. Positive photoresist is where the image formed
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in the resist is the same pattern as the photomask whereas negative photoresist
produced a resist image which is negative of the pattern found on the photomask. [7]
Figure 2.10: Two type of photoresist layer is produced after development: positive photoresist
and negative photoresist.
2.2.4 Etching
Etching is the process of removing regions of the underlying material that are no
longer protected by the photoresist after development. It is done by using either
chemical or physical means. There are two types of etching process which are dry
etch and wet etch.
Dry etch exposes the wafer to a plasma (ionized gas) that interacts physically
or chemically (or both) to remove the surface material. It is normally used to deal with
metallic films. Wet etch uses liquid chemicals to chemically remove the wafer surface
material. Wet etch normally is used for oxide films. [7]
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When an etching process is proceed in all directions at the same rate, the
etching process is said to be isotropic. Inversely, if it is proceeds in only one direction,
it is completely anisotropic. Wet etching is generally isotropic whereas dry etching
process is anisotropic in nature. [10]
Figure 2.10: Target layer is removed through etching process.
2.2.5 Diffusion and Ion Implantation
Diffusion and ion implantation are the two major processes where dopants are
introduced into silicon lattice. Phosphorus, Arsenic (N-type) and Boron (P-type) are
the most frequently used dopants in the semiconductor industry.
Diffusion is the movement of one material through another from a region of
relatively higher concentration into a region of lower concentration. Normally, the
dopant is introduced into the silicon lattice by thermal diffusion. There are three steps
involved in thermal diffusion: predeposition, drive in and activation. [7] In
predeposition stages, the dopant gas is arrives at the surface of substrate where the
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concentration gradient of dopant is remains between them. After certain times, the
dopant gases “drive in” into the silicon lattice with the aid of thermal energy. The
concentration gradient of dopant at the surface of the substrate is decreases with time.
The used of thermal diffusion as the doping method has gradually declined nowadays
due to its poor control of doping concentration and depth. [11]
Figure 2.11: Dopant is introduced into silicon substrate through thermal diffusion.
Ion implantation method has steadily replaced thermal diffusion method due to
its superior advantages to doping the silicon substrate. The process is simpler but
more costly as the ion implanters are quite expensive. During ion implantation,
doping atoms are vaporized and accelerated toward the silicon substrate. These high-
energy atoms enter the crystal lattice and lose their energy by colliding with some
silicon atoms before finally coming to rest at some depth. Adjustment on the
acceleration energy could control the average depth of depositing dopants. [12]
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Figure 2.12: Schematic diagram of ion implantation process.
But the introduction of dopant into the lattice could cause the damage to the
lattice. The damage caused by atomic collisions or displacement by both methods
changes the electrical characteristics of the target. Many target atoms are displaced,
creating deep electron and hole traps which capture mobile carriers and increase
resistivity. Annealing is therefore needed to repair the lattice damage and put dopant
atoms in substitutional sites where they can be electrically active again. This is
known as activation where the the crystal lattice disturbances are repaired by making
the dopant as the part of silicon substrate.
Figure 2.13: Annealing is done on wafer to repair the silicon lattice which is damaged by
ATMT 4213 Advanced Materials Testing and Evaluation
For reliability testing or qualification of new devices, 1000 temp cycles are
usually performed, with intermediate visual inspection and electrical testing read
points at 200X and 500X.
(a) (b)
Figure 3.0: (a) Temperature Cycle Machine. (b)Thermal Shock Chamber.
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The example of Temperature Cycle Test specification that used in semiconductor
industry:
M il-Std-883, Method 1010 Specs : Temperature Cycle Test
Total Transfer Time <= 1 minute
Total Dwell Time >= 10 minutes
Specified Temp reached in <= 15 minutes
Must be conducted for a minimum of 10 cycles
Condition Low Temp (°C) High Temp (°C)
A -55 (+0/-10) 85 (+10,-0)
B -55 (+0/-10) 125 (+15,-0)
C -65 (+0/-10) 150 (+15,-0)
D -65 (+0/-10) 200 (+15,-0)
E -65 (+0/-10) 300 (+15,-0)
F -65 (+0/-10) 175 (+15,-0)
Table 3.1: Mil-Std-883 Method 1010 Temp Cycle Test Conditions
JEDEC JESD22-A104 Specs : Temperature Cycle Test
Total Transfer Time <= 1 minute
Total Dwell Time >= 10 minutes
Specified Temp reached in <= 15 minutes
Recommended for lot acceptance screen : 10 cycles
Recommended for qualification : 1000 cycles
Condition Low Temp (°C) High Temp (°C)
A -55 (+0/-10) 85 (+10,-0)
B -55 (+0/-10) 125 (+10,-0)
C -65 (+0/-10) 150 (+10,-0)
D -65 (+0/-10) 200 (+10,-0)
F -65 (+0/-10) 175 (+10,-0)
G -40 (+0/-10) 125 (+10,-0)
H -55 (+0/-10) 150 (+10,-0)
Table 3.2: JEDEC JESD22-A104 Specs Temp Cycle Test Conditions
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The example of Temperature Shock Test specification that used in semiconductor
industry:
M il-Std-883, Method 1011 Specs: Thermal Shock Test
Total Transfer Time < 10 seconds
Total Dwell Time > 2 minutes
Specified Temp reached in < 5 minutes
Must be conducted for a minimum of 15 cycles
Condition Low Temp (°C) High Temp (°C)
A -0 (+2/-10) 100 (+10,-2)
B -55 (+0/-10) 125 (+10,-0)
C -65 (+0/-10) 150 (+10,-0)
Table 3.3: Mil-Std-883 Method 1011 Thermal Shock Test Conditions
JEDEC JESD22-A106 Specs: Thermal Shock Test
Total Transfer Time < 10 seconds
Total Dwell Time > 2 minutes
Specified Temp reached in < 5 minutes
Must be conducted for a minimum of 15 cycles
Condition Low Temp (°C) High Temp (°C)
A -40 (+0/-30) 85 (+10/-0)
B -0 (+2/-10) 100 (+10,-2)
C -55 (+0,-10) 125 (+10,-0)
D -65 (+0,-10) 150 (+10,-0)
Table 3.4: Mil-Std-883 Method 1011 Thermal Shock Test Conditions
3.1.2 Mechanical Shock Test [22]
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Mechanical Shock Test is a test performed to determine the ability of semiconductor
devices to withstand moderately severe shocks. The sources of shock may come from
suddenly applied forces or abrupt changes in motion encountered during mishandling,
improper transportation, or field operation. The devices might degrade in performance
or even get damage permanently as the result of the shocks. If the shock pulses are
repetitive in nature, it can also cause the damage on device that is similar to those
caused by extreme vibration.
In this test, the mechanical shock testing machine must be mounted on a
sturdy and leveled surface. The sample must be rigidly mounted or restrained by its
case or body, with ample protection for the leads. The machine is able to provide
shock pulses of 500 to 30,000 g (peak), with the pulse duration ranging from 0.1 to 1
millisecond, to the body of the device package. The acceleration pulse applied
normally is a half sine wave with a distortion not exceeding +/-20% of the specified
peak acceleration. The measurement is taken by a transducer and optional electronic
filter whose cut-off frequency is at least 5 times the fundamental frequency of the
shock pulse. The pulse width is measured between the 10% point of the peak
acceleration during rise time and the 10% point during decay time. The pulse widths
have a tolerance of whichever is greater between +/-0.1 milliseconds or +/-30% of the
specified width.
After the mechanical shock test has been completed, external visual inspection
of the case, leads, and seals is performed at a magnification of 10 X to 20 X. The
marking is also inspected with or without magnification, but with the magnification
not greater than 3 X. If any illegible mark and/or any evidence of damage to the case,
leads, or seals after the stress test are identified, the device is considered a failure.
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The example of Mechanic Shock testing specification that used in semiconductor
industry:
Mil-Std-883 Method 2002: Mechanic Shock Test
Test Condition g Level (peak) Pulse Duration (ms)
A 500 1
B 1,500 0.5
C 3,000 0.3
D 5,000 0.3
E 10,000 0.2
F 20,000 0.2
G 30,000 0.12
Table 3.5: Mil-Std-883 Method 2002 Mechanical Shock Testing Test Conditions
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3.1.3 Vibration Tests [23]
Vibration test are tests performed to determine the effects of mechanical vibration
within a specified frequency range on semiconductor devices. Basically, there are
two different types of vibration tests, which are vibration fatigue test and variable
frequency vibration test. Both of them are similar in many aspects, but each of them
is intended to reveal different types of vibration-related failures.
For vibration fatigue test, the sample is subjected to sustained vibration within
specified levels. There is optical and electrical equipment that used to perform post-
test measurements. During the test, the sample is fixed on the vibration platform with
its lead adequately secured. The sample is then subjected to a simple harmonic
vibration that a constant amplitude having a peak acceleration corresponding to the
specified test condition. The vibration is performed for minimum of 32+/- 8 hours in
each of X-, Y- and Z- orientations, for a total of 96 hours minimum.
For variable frequency variation test, the sample is subjected to variable
frequency vibration at specified levels. It is same as vibration fatigue test in which
there is also optical and electrical equipment to perform the post-test measurements.
During the test, the sample is firmly fastened on the vibration platform with its leads
adequately secured. The sample is then subjected to a simple harmonic vibration that
has either peak-to-peak amplitude of 0.06 inch +/- 10% or a peak acceleration of the
specified test condition. The vibration frequency is varied approximately
logarithmically between 20 and 2,000 Hz. The entire frequency range of 20-2000 Hz
and the return to 20 Hz must be traversed in not less than 4 minutes. This cycle is
performed 4 times in each of the orientations X, Y, and Z, for a total of 12 times.
Once the vibration test has been completed, external visual inspection of the
case, leads, and seals is performed at the magnification of 10 X to 20 X. The marking
is also inspected with or without magnification, but with the magnification not
greater than 3 X. If there is any illegible mark and/or any evidence of damage to the
case, leads, or seals after the stress test, the device is considered as a failure.
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The example of Vibration testing specification that used in semiconductor
industry:
Mil-Std-883 Method 2005: Vibration Fatigue Test
Test Condition Stress Level (g)
A 20
B 50
C 70
Table 3.6: Mil-Std-883 Method 2005 Vibration Fatigue Testing Test Conditions
Mil-Std-883 Method 2007 : Variable Frequency Vibration Test
Test Condition Stress Level
(g)
A 20
B 50
C 70
Table 3.7: Mil-Std-883 Method 2007 Variable Frequency Vibration Testing Test
Conditions
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3.1.4 Burn-in Test [24]
Burn-in test is an electrical test that accelerates the electrical failure of a device
through the application of voltage and temperature under over range condition. The
electrical excitation applied during burn-in may mirror the worst case bias that the
device will be subjected to in the course of its usable life. Thus, burn-in essentially
stimulates the operating life of the device. Depending on the burn-in duration used,
the reliability information obtained may pertain to the device’s early life or its wear-
out.
Burn-in is usually carried out by applying the electrical excitation to the
sample at temperature about 125°C. During the testing, the samples are loaded into
the burn-in boards. These burn-in boards are then inserted into the burn-in oven in
which the samples are supplied with necessary voltages while maintaining the
temperature at 125°C. The electrical bias applied may either be static or dynamic,
depending on the failure mechanism being accelerated.
(a) (b)
Figure 3.1: (a) Burn-in boards. (b)Burn-in ovens.
The operating life cycle distribution of devices may be modeled as a bathtub
curve. The bath tub curve shows that the highest failure rates experienced by a
population of devices occur during the early life and during the wear-out period of the
life cycle. In the region between the early life and wear-out stages, the device seldom
fails and could performed well over a long period. Thus, burn-in test is useful tool to
identify the operating behaviour of device over a period.
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Figure 3.2: Reliability bathtub curve of a device.
Early Life Failure (ELF) is a type of burn-in test that perform to screen out
potential early life failures. Inversely, High Temperature Operating Life (HTOL) and
Low Temperature Operating Life (LTOL) is burn-in test that identify the reliability of
the samples in their wear-out phase.
3.1.4.1 Early Life Failure (ELF) [24]
Early Life Failure is a burn-in test which accelerates possible early life failure of
devices during production level. It is conducted for duration of 168 hours or less, and
normally for only 48 hours. If the sample shows early life failures during the test, this
means that these units of product will fail prematurely when they were used in their
normal operation.
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3.1.4.2 High Temperature/ Low Temperature Operating Life [25] [26]
High Temperature/Low Temperature Operating Life is performed to determine the
reliability of devices when subjecting to a specified bias (electrical stressing) for
specified amount of time and at a specified temperature. If it is refer to HTOL, the test
will conducted in a high temperature conditions whereas LTOL is done at low
temperature conditions but not exceeding the maximum limits of -10°C unless
otherwise specified. Actually, HTOL and LTOL are just essentially a long term burn-
in of sample that is carried in a burn-in oven capable of operating continuously over
long durations. Both of them are usually conducted for duration of 1000 hours, with
intermediate reading of testing is taken at 168 hour and 500 hour.
There are several requirements need to take care when biasing the sample
during the testing. The sample cannot be electrically overstressed and exceed the
datasheet limits of manufacturer. The bias must also be continuous, and should only
be interrupted when taking the reading of testing.
This test is more concerned with acceleration of wear-out failures in the
samples. This is the reason where the test is required long durations of testing in order
to assure that results are not due to early life failures.
Sometimes, the test duration may be decreased by increasing the ambient
temperature for HTOL and decreasing the temperature for LTOL. Unless otherwise
specified, all intermediate and end-point electrical tests must be performed on the
parts within 96 hours (24 hours for Ta>=175 ° C) after removal of sample from the
specified burn-in conditions. If not specified, an intermediate electrical testing shall
be performed after 168 (+72,-0) hours and after 504 (+168,-0) hours.
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The example of Burn-in test specification that used in semiconductor industry:
Mil Std 883 , Method 1005 Specs: HTOL generally 1000 hours min. at 125 °C max. rated Tc or Ta < 200 ° C (Class B) max. rated Tc or Ta < 175 °C (Class S) Condition A : steady-state, reverse bias Condition B : steady-state, forward bias Condition C : steady-state, power/reverse bias Condition D : steady-state, parallel excitation Condition E : steady-state, ring oscillator Condition F : steady-state, temp.-accelerated
ATMT 4213 Advanced Materials Testing and Evaluation
Figure 3.4: (a) HAST system: the Trio Tech 6000X (b) the chamber of the Trio Tech 6000X
3.1.7 High Temperature Storage (HTS) [29]
High Temperature Storage test is performed to determine the effect of long-term
storage at elevated temperature without any electrical stresses applied. HTS is not
substitute for burn-in because it does not subject the sample to electrical stresses
(bias). This test is effective for testing the sample in terms of mechanism accelerated
by temperature only such as oxidation, bond and lead finish intermetallic growth, etc.
Any oven or chamber capable for providing controlled elevated temperature
can be used for HTS. It is similar to stabilization bake, except that HTS is done over a
much longer period of time at specific temperature. For example, HTS is conducted at
150°C for duration 1000 hours instead of 24 hours for stabilization bake. The purpose
of HTS is to assess the long-term reliability of devices under high temperature
conditions while that of stabilization bake is merely to serve as a preconditioning
treatment prior to conduct other tests.
The example of High Temperature Storage (HTS) test specification that used in semiconductor industry:
Mil Std 883, Method 1008, Stabilization Bake Specs: HTS
storage at a high temperature for a specified duration Test Condition A : 75 °C / 24 hours minimum Test Condition B : 125 °C / 24 hours minimum Test Condition C : 150 °C / 24 hours minimum Test Condition D : 200 °C / 24 hours minimum Test Condition E : 250 °C / 24 hours minimum Test Condition F : 300 °C / 24 hours minimum Test Condition G : 350 °C / 24 hours minimum Test Condition H : 400 °C / 24 hours minimum
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ATMT 4213 Advanced Materials Testing and Evaluation
4.0 Conclusions
Semiconductor devices had change the human world tremendously in this past few
year decades. They are the fundamental of electronic equipment for many applications
such as mobile phones, automobiles and computers. Its related technology is growing
in a rapid and unbelievable rate. The current semiconductor device is undergoes the
trend of miniaturization in size and complexity of device functions. Hence, this result
in more difficulties arises during the manufacturing of devices. The manufacturers
have the responsibility to ensure the quality for each batch of product is within the
safety limits. Otherwise, this would incur a huge lost if the device fail to perform as
intended.
As a result, reliability issue of the devices become the primary concern in all
the semiconductor industries. Reliability testing indirectly becomes the efficient tools
to assess and evaluate the performance of the manufactured devices. In addition,
semiconductor devices are manufactured in mass volume to gain economic scale of
benefits. The manufacturing of the device is high in complexity and involve multi-
step process. Any mishandling either by worker or the machine during the
manufacturing process could the whole batch of the devices to be failed. Thus,
reliability testing is important because these tests function as a mean to control and
monitor the whole process. The successful for the flow of manufacturing process is
depends greatly on the use of reliability testing.
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ATMT 4213 Advanced Materials Testing and Evaluation
5.0 References
1. Siliconfareast, 2006, What is semiconductor?, viewed 17 July 2010,
<http://www.siliconfareast.com/whatissemicon.htm>
2. STMicroelectronics, n.d, Introduction to Semiconductor Technology,
viewed 17 July 2010, <http://www.st.com/stonline/books/pdf/docs/5038.pdf>