Instructor:Yaniv Ben-Itzhak Students:Ofir Shimon Guy Assedou Spring 2009.

NETWORK ON CHIP

PLATFORMInstructor: Yaniv Ben-ItzhakStudents: Ofir Shimon

Guy AssedouSpring 2009

FINAL PRESENTATION

- SPRING 2009 -

General Concept NoC - Network On Chip A network-like structure composed of inter-

connected modules which exchange data efficiently and in very fast rates

Spring 2009

NoC Platform – Project Definition

Design and build basic NoC CPU Module as a part of multi-core NoC platform on an FPGA, and implement a tailored HW/SW verification system.

Spring 2009

NOC Platform

Architecture

Spring 2009

ADAPTOR(cpu-router)

NIOS IIsoftcore

ROUTER

ADAPTOR(cpu-router)

NIOS IIsoftcore

ROUTER

ADAPTOR(cpu-router)

NIOS IIsoftcore

ROUTER

ADAPTOR(router-memory)

MEMORY CONTROLLER

ROUTER

ADAPTOR(cpu-router)

NIOS IIsoftcore

ROUTER

CPU Module Architecture

Spring 2009S

ystem Interconnect

F

abric (BU

S)

ROUTERCPU-ROUTER

ADAPTOR

Avalon M

M

Interface

packets

controls

NIOS IIsoftcore

ADAPTOR)cpu-router(

NIOS IIsoftcore

ROUTER

ADAPTOR)cpu-router(

NIOS IIsoftcore

ROUTER

ADAPTOR)cpu-router(

NIOS IIsoftcore

ROUTER

ADAPTOR

MEMORY CONTROL

LER

ROUTER

ADAPTOR)cpu-router(

NIOS IIsoftcore

ROUTER

System Configuration

Nios II soft-coreCPU freq – 100 MHzPipeline

○ Increase throughput for peripherals that require several cycles to return data

○ Two phase pipeline – Address & Data○ Only Read requests can be pipelined

System Interconnect FabricSelected Bus Interface - Avalon Memory

Mapped: Used for R/W interfaces on master and slave components in a memory-mapped system

Spring 2009

System Configuration

RouterVirtual channels - One channel was defined for

both R/W operations in order to keep static routing in the platform.

Flit type - Head & tail - easy to implement

SystemClock frequency – 100 MHzMax Packets per CPU Module – 16Packet size – 77 bits

Spring 2009

Packet Structure

Spring 2009

Packet Header Flit

Packet

Service Level

Packet Type Flit Header Data

Service Level

Packet Type Processor ID Request

Type Data AddressMemory

X

Coordinate

Memory

Y

Coordinate

76 75 74 73 72 71 70 39 38 8 7 4 3 0

Syste

m In

tercon

ne

ct

Fa

bric (BU

S)

ROUTERCPU-

ROUTERADAPTOR

Avalon M

M

Interface

packets

controls

NIOS IIsoftcore

Adaptor Architecture

Spring 2009

control

BUFFER IN)FIFO(

ROUTER_TX

flit

data

address

waitrequest

packet

control

packet

data

control

BUS_TX

CREDITS CALCULATORcontrol

control control

Verification & Validation

Behavioral SimulationsPre-synthesis VHDL for logic

functionality with ModelSim Develop Verification Environment Full System Testing

Create high load of memory accesses in system

Spring 2009

Verification System

Architecture

Spring 2009

LO

OP

ER

packets

controls

CPU Module

TESTER

System

Interconnect

Fabric (B

US

)

ROUTERCPU-ROUTERADAPTOR

Avalon M

M

Interface

packets

controls

NIOS IIsoftcore

Spring 2009

 Screen clipping taken: 29/06/2009, 12:22

Behavioral Simulations -Write

Waveforms

Behavioral Simulations -Read

Waveforms

Spring 2009

 Screen clipping taken: 29/06/2009, 12:22

LOOPER Module Architecture

Spring 2009

BUFFER IN)FIFO(

packet

control

ROUTER_TX

CREDITS CALCULATOR

control

packet

control

control

packet

packet

LO

OP

ER

packets

controls

CPU Module

TESTER

System

Interconnect

Fabric (B

US

)

ROUTERCPU-ROUTERADAPTOR

Nios II

Verification Software

Harsh and intensive environment that will test the hardware

Write/Read randomly to memoryIncreased paced in compare to average

memory access rate

Spring 2009

Verification Software -Pseudo-

CodeRandomize

number of write instructions to

issue -> wr

Iterate wr times•Write data to memory•Store data & address in dedicated arrays for later use•Increase address & data value

Randomize number of read instructions to

issue -> rd

Iterate rd tims•Read data from memory•Compare data from memory with data stored in data array•Update statistics

Spring 2009

Test Results

Program Iteration Example:

Final Results:

Spring 2009

FPGA Resources Usage

Spring 2009

Adaptor0.13%

Router8.37% Nios II

6.96%

Free Resources84.54%

Adaptor RouterNios II Free Resources

Development Tools Hardware:

GIDEL ProcStar II 180 BoardStratix II 60 FPGAPC

Software:Quartus IISOPC BuilderNIOS II IDEModelSimGIDEL PROCWizard

Spring 2009

Spring 2009

Project MilestonesCharacterization Report & Presentation

Tutorials •VHDL •Nios II softcore – “hello world”

•System Interconnect Fabric

Tools Ramp-up•Quartus II•SOPC Builder•HDL Designer•NIOS II IDE

Router Ramp-up

Mid-semester presentation

Implementing CPU-ROUTER

Adaptor

Implementing CPU Module

Implementing LOOPER

H/W System Integration

S/W Coding

Final Presentation

Achievements & Further Work Main Project Achievements

Fully operational NOC based system in hardware (FPGA)Modular CPU Module - building block which enables easy scalability of future NOC platformsVerification & Validation environment (HW & SW)

Further WorkComplete Memory Module Implementation Complete Platform integrationIn-depth Platform analysis

Spring 2009

THANK YOU!

Spring 2009

Syste

m In

tercon

ne

ct

Fa

bric (BU

S)

ROUTERCPU-

ROUTERADAPTOR

Avalon M

M

Interface

packets

controls

NIOS IIsoftcore

Adaptor interconnections

RouterVirtual channels

○ can be modified as required.2 channels were defined. One for Read requests and one

for Write requests.

Flit type○ Three types – head, tail & head and tail

Only head & tail - easy to implement

Spring 2008

Syste

m In

tercon

ne

ct

Fa

bric (BU

S)

ROUTERCPU-

ROUTERADAPTOR

Avalon M

M

Interface

packets

controls

NIOS IIsoftcore

Adaptor interconnections

System Interconnect Fabric - BusAvailable interfaces to SIF

○ Clock Interface○ Interrupt Interface○ Avalon Memory-Mapped Tristate Interface○ Avalon Streaming Interface○ Conduit Interface○ Avalon Memory-Mapped Interfaces

Interface to Bus is Avalon Memory Mapped○ Used for R/W interfaces on master and slave

components in a memory-mapped system

Spring 2008

Syste

m In

tercon

ne

ct

Fa

bric (BU

S)

ROUTERCPU-

ROUTERADAPTOR

Avalon M

M

Interface

packets

controls

NIOS IIsoftcore

Adaptor interconnections

Slave Transfers:○ Typical Slave Read and Write Transfer○ Burst Transfer○ Pipelined Transfer

Pipeline○ Increase throughput for peripherals that require

several cycles to return data○ Two phase pipeline – Address & Data○ Only Read requests can be pipelined

Spring 2008

Nios II Sofcore Processor

Spring 2009