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Instructor: Yuzhuang Hu [email protected]
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Page 1: Instructor: Yuzhuang Hu yhu1@cs.sfu.ca. Design strategy in ASM.

Instructor: Yuzhuang [email protected]

Page 2: Instructor: Yuzhuang Hu yhu1@cs.sfu.ca. Design strategy in ASM.

Design strategy in ASM

Page 3: Instructor: Yuzhuang Hu yhu1@cs.sfu.ca. Design strategy in ASM.

CISC ArchitectureThe goal of the CISC architecture is to match more

closely the operations used in programming language and to provide instructions that facilitate compact programs and conserve memory.

A purely CISC architecture has the following properties: Memory access is directly available to most types of

instructions. Addressing modes are substantial in number. Instruction formats are of different lengths. Instructions perform both elementary and complex

operations.

Page 4: Instructor: Yuzhuang Hu yhu1@cs.sfu.ca. Design strategy in ASM.

Combined CISC-RISC Organization

Instruction fetch

Decode and operand fetch

Execute

Write-back

Microprogram counter

Control ROM

Page 5: Instructor: Yuzhuang Hu yhu1@cs.sfu.ca. Design strategy in ASM.

CISC CPU Instruction Formats

OPCODE

DR SA SB

OPCODE

DR SA Immediate

31 2524 2019 1514 109 0

OPCODE

DR SA Large target offset

OPCODE

DR SA SB Short target offset

Three register type

Two register type

Branch 1

Branch 2

Page 6: Instructor: Yuzhuang Hu yhu1@cs.sfu.ca. Design strategy in ASM.

Micro-programmed Control

+1

MC

MS

MI

MZMZ-1PSZ

ME

SA CA CA-1

0 1 2 3

Mux E

AddressMicrocode ROM

Data

MZ CA

MZ-1

CA-1

DOF

EX

Page 7: Instructor: Yuzhuang Hu yhu1@cs.sfu.ca. Design strategy in ASM.

Address Control

Page 8: Instructor: Yuzhuang Hu yhu1@cs.sfu.ca. Design strategy in ASM.

Load Indirect Indexed(LII)

ActionAddress

Microinistructions

MZ

CA

RW

DX

MD

BS PS

MW

FS

LC

MA

MB

AX

BX

CX

R16<-R[SA]+zf IML

LII0

01

00

1 10 0 00 0 0 2 0 00 1 00 00 00

MC<-MC+1 (NOP)

LII1

01

00

0 00 0 00 0 0 0 0 00 0 00 00 00

R17<-M[R16]

LII2

01

00

1 11 1 00 0 0 0 0 00 0 10 00 00

MC<-MC+1(NOP)

LII3

01

00

0 00 0 00 0 0 0 0 00 0 00 00 00

R[DR]<-M[R17]

LII4

10

IDLE

1 01 1 00 0 0 0 0 00 0 11 00 00

Page 9: Instructor: Yuzhuang Hu yhu1@cs.sfu.ca. Design strategy in ASM.

A Personal ComputerScree

n

Keyboard

Hard drive

Drive Controll

er

Bus Interface

RAMProcesso

r

Graphics

Adapter

CPU, FPU, MMUInternal Cache

External Cache

Page 10: Instructor: Yuzhuang Hu yhu1@cs.sfu.ca. Design strategy in ASM.

Access TimesCache: 1 ns, memory: 10 ns, hard drive: 13

ms

Assume that 95% of the fetches will be from a cache and about 4.999995 percent of the fetches will be from main memory. The average access time then is:

0.95*2+0.49999995*10+5*10-

8*1.3*107=3.05ns

Page 11: Instructor: Yuzhuang Hu yhu1@cs.sfu.ca. Design strategy in ASM.

Locality of Reference

Temporal Locality: refers to the relative times at which instructions and operands are accessed.

Spatial Locality: refers to the relative locations at which they reside in main memory.

Page 12: Instructor: Yuzhuang Hu yhu1@cs.sfu.ca. Design strategy in ASM.
Page 13: Instructor: Yuzhuang Hu yhu1@cs.sfu.ca. Design strategy in ASM.
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Page 15: Instructor: Yuzhuang Hu yhu1@cs.sfu.ca. Design strategy in ASM.
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Page 17: Instructor: Yuzhuang Hu yhu1@cs.sfu.ca. Design strategy in ASM.
Page 18: Instructor: Yuzhuang Hu yhu1@cs.sfu.ca. Design strategy in ASM.

Write MethodsWrite the result into main memory. This is

also called write-through.

Write the result into the cache if there is a cache hit. This is also called write-back.write-allocate: when a cache miss happens,

read the line containing the word to be written from main memory into the cache, with the new word written into both the cache and main memory. Dirty bit of a line.

Page 19: Instructor: Yuzhuang Hu yhu1@cs.sfu.ca. Design strategy in ASM.
Page 20: Instructor: Yuzhuang Hu yhu1@cs.sfu.ca. Design strategy in ASM.
Page 21: Instructor: Yuzhuang Hu yhu1@cs.sfu.ca. Design strategy in ASM.

THANKS!