Instructor ： Po-Yu Kuo 教師：郭柏佑

Instructor ： Po-Yu Kuo

教師：郭柏佑

Lecture2: Frequency Compensation and Multistage Amplifiers II

EL 6033類比濾波器 ( 一 )

Analog Filter (I)

2

Outline

Miller Compensation in Two-Stage Amplifiers Design of a Two-Stage Amplifier

3

Simplification for Two-Stage Amplifier

Fig. 2 is the signal representation of Fig. 1 gm1 (fig. 2) = gm1,2 (fig. 1)

gmL (fig. 2) = gmL (fig. 1)

r1, C1 (fig. 2) = equivalent output resistance (ro2//ro4), capacitance(Cdtot,M4+Cdtot,M2+Cgtot,ML) at V1 (fig. 1)

rL, CL (fig. 2) = output resistance (roL//rob3), capacitance (CL) at Vo(fig. 1)

4

Hybrid-πModel of Two-Stage Amplifier

Fig. 2 is the Hybrid-π Model of two-stage amplifier

Hybrid-π Model is used to derive small-signal transfer function(Vo/Vin) of the two-stage amplifier

When convert to Hybrid-π Model, the circuit is linear with approximation To understand frequency compensation, small signal model must be

obtained

5

Question#1

What is the Hybrid-π Model and dc gain of this circuit?

6

Answer

Dc gain of the first gain stage is +ve Dc gain of the second gain stage is –ve Overall dc gain=-gm1gmLr1rL (-ve gain!)

7

Why We Need Frequency Compensation?

Frequency compensation relates certain circuit specifications with design parameters

Circuit specifications: unity-gain bandwidth (BW), phase margin (PM) and CL

Design parameters: gm1, gmL, Cm

gm √I, and area of Cm dominates the chip area of amplifier Frequency compensation can optimize BW and PM by using minimum

current consumption (gm) and smallest chip area (Cm) for a particular CL

DC gain specification decides the values of r1 and rL

8

Concept of Bode Plots (1)

Transfer Functions:

A(s)=s

A(s)=1/s

A(s)=1/(1+s/p)

(LHP pole @ p)

9

Concept of Bode Plots (2)

A(s)=1+s/z

(LHP zero @ z)

Both magnitude and phase

Increase!!

A(s)=1-s/z

(RHP zero @ z)

Magnitude increases but phase

decrease!!

10

Miller Compensation in Two-Stage Amplifier (1)

Numerator: DC gain Zero: (1-as) → RHP zero, (1+as) → LHP zero 1 RHP zero exits → phase margin degradation

Denominator: Poles: (1+as+bs2+…), all coefficient terms (a, b, …) should be positive

(LHP poles); otherwise amplifier is unstable 2 LHP poles exist

mL

LLmLm

mL

mLmLm

in

o

g

CsrrgsC

g

Csrrgg

V

V

11

1

1

11

11


DC gain = gm1gmLr1rL= A1x AL

RHP zero (zRHP): gmL/Cm

p-3dB = 1/CmgmLr1rL

p2 = gmL/CL

UGF = DC gain x p-3dB = gm1/Cm

mL

LLmLm

mL

mLmLm

in

o

g

CsrrgsC

g

Csrrgg

V

V

11

1

1

11

12


Stability (phase margin of the amplifier):

PM>45∘to preserve stability PM>60∘to preserve stability and achieve better settling time The presence of RHP zero degrades stability

What is the relationship of gm1, gmL and Cm in order to achieve stability?

mL

m

m

L

mL

m

RHP

RHPdB

g

g

C

C

g

g

z

UGF

p

UGF

z

UGF

p

UGF

p

UGFPM

1111

1

2

1

1

2

1

3

1

tantan90

tantan90

tantantan180

13

Dimension Condition of Cm

If RHP zero neglected Case 1: PM=60 ∘

Case 2: PM=45 ∘

BW of amplifier trades with the stability (PM) In most textbook: Cm=2gm1CL/gmL & UGF=0.5gmL/CL, then PM=63.4∘

L

mL

mL

Lmm

m

L

mL

m

C

gUGF

g

CgC

C

C

g

g

58.0

73.1

30tan

1

11

L

mL

mL

Lmm

C

gUGF

g

CgC

1

Recall: Single-Stage Amplifier, UGF=gmL/CL

& PM=90∘

14

Question

As mentioned previously, UGF=gm1/Cm, do you think is it the best way to increase UGF of the amplifier by decreasing Cm? From equation, decreasing Cm does not increase the power consumption and decreases the chip area. Then you should ask yourself “does it have any free lunch in the world”?

15

Question

UGF increases due to the increase in p-3dB.

However, p2 does not change, p2 is smaller than UGF and PM is much smaller than 45 ∘

Stability problem arises! No Free Lunch!!!

16

Solution(1)

What is the frequency domain behavior if we increase gm1 only based on UGF=gm1/Cm?

Again, UGF increases but the amplifier suffersfrom the stability problem!!

17

Correct approach to increase BW

How to enhance UGF without hurting stability (PM)? Step1: gmL ↑

Both p2 and zRHP move to higher freq.

PM ↑ with same BW Step2: : Cm ↓ according to Cm=2gm1CL/gmL

BW ↑

Rule of Thumb:

Larger current should be allocated to the output stage for UGF enhancement!!

gmL >> gm1!!

18

Effect of RHP Zero

By taking RHP zero into consideration and assume Cm=2gm1CL/gmL; then

If gmL=gm1, then PM=18.4 ∘(instability)

If gmL=10gm1, then PM=57.7 ∘(stability degradation)

gmL >> gm1 to preserve stability due to RHP zero!

larger gmL implies larger power consumption.

Miller compensation is not suitable for low-power design due to the presence of RHP zero!

RHP zero removal techniques Low-Power design!!

mL

m

RHP

g

g

z

BW

p

BWPM

11

1

2

1

tan4.63

tantan90

19

Miller Compensation with Null Resistor

No change in pole locations! Rm is used to improve PM as

zRHP is removed by Rm = 1/gmL

PM = 63.4∘ low-power design condition

mL

LmLm

mmL

mmLm

in

o

g

CsrrgsC

Rg

-sCrrgg

V

V

11

11

L1

L11

Add Extra resistor

20

Dimension Condition of Rm

LHP zero is generated if Rm > 1/gmL

If the LHP zero is used to cancel p2, then Rm is set as

Both zRHP and p2 are cancelled

Rm cannot be too large since very large Rm causes open circuit and no pole-splitting effect due to Miller compensation (Rm < r1/10)

Rule of Thumb:

1/gmL ≤ Rm < r1/10

mLm

mL

mLm

Lm gg

g

gC

CR

121

11

1

21

Miller Compensation Implementation of Two-Stage Amplifier

If Rm is implemented by transistor(s), then the transistor(s)should be placed between the drain of M4 and Cm to ensure the transistor(s) always in the triode region!

Vgs,ML should be equal to Vgs,M3 and Vgs,M4 for minimizing the systematic offset voltage.

Vgs,ML

22

Outline

Miller Compensation in Two-Stage Amplifiers Design of a Two-Stage Amplifier

23

Design Example (1)

If the specification is given as CL=10pF UGF > 3MHz PM > 60 ∘ DC Gain > 80dB SR > 2.5V/μs Power Consumption < 160W Supply Voltage = 2V

Designer’s job is choose Rm, Cm, (W/L)i, Li, I to meet specifications!!

What are the relationship between designer’s job and the specifications?

24

Design Example (2)

Recall: for PM ≈ 63.4 ∘, then UGF=gmL/2CL & Cm=2gm1CL/gmL

gmL is fixed (415 μA/V) & Rm=2.4 kΩ

Assume gm1=150 μA/V, Cm is fixed at 7.2 pF

Theoretical UGF=3.3 MHz (gmL/(2π)2CL)

Further assume r1=1.3 MΩ and ro=200 kΩ Theoretical dc gain=84 dB

Use Hybrid-π model to verify the bandwidth, dc gain and phase margin performances by using Hspice or Cadence

25

Design Example (3)

After choose the value of each circuit parameter such as gm1, gmL, CL, Cm … etc.

Verify the performance of Hybrid-π model

Simulate the Hybrid-π model in Hspice or Spectre

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Design Example (4)

AC Simulation Results of Hybrid-π model in Spectre

27

Design Example (5)

SR is the change rate of output voltage when time change → Ideally, SR is infinity SR=min(IMb3/CL, IMb2/Cm) ≈ IMb2/Cm (in most cases)

Systematic Offset Requirement (Vgs,M4=Vgs,ML (W/L)ML/(W/L)M4=2IML/IMb2) and total power consumption (Itot ≈IMb2+IML) → fix(W/L)ML and IML (need iterations)

Make sure (W/L)ML and IML meet ro and dc gain requirements Iterations of above steps are necessary until all specificationsare met.

28

Design Flow(1)

Step1: Make sure all transistors work in correct region Simulate the common mode result

Then check if the all transistor work in sat. region

29

Design Flow(2)

Transistor status

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Design Flow(3)

Step2: Start AC simulations

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Design Flow(4)

Step3: Start transient response analysis

32

Performance Summary

33

Tips of Simulations

DC Analysis: make sure all transistors operating in the saturation region, and check the lowest supply voltage to achieve the required input common-mode range.

AC Analysis and Pole-Zero Analysis: check dc gain, BW, stability (phase margin, pole and zero locations) and power consumption

Transient Analysis: check step response of the amplifier (slew rate and settling time). It should be noted that the input step amplitude should be within the input common-mode range of the amplifier.

Instructor ： Po-Yu Kuo 教師 ： 郭柏佑

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Instructor ： Po-Yu Kuo 教師：郭柏佑