Instruction Set Design Instruction Set Design by Kip R. Irvine (c) Kip Irvine, 2002-2003. All rights reserved. You may modify and copy this slide show for your personal use, or for use in the classroom, as long as this copyright statement, the author's name, and the title are not changed. Revision date: 3/26/2003
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Instruction Set DesignInstruction Set Design
by Kip R. Irvine
(c) Kip Irvine, 2002-2003. All rights reserved. You may modify and copy this slide show for your personal use, or for use in the classroom, as long as this copyright statement, the author's name, and the title are not changed.
Revision date: 3/26/2003
Copyright 2002-2003, Irvine, Kip R. All rights reserved. 2
Instruction Set Design Factors *Instruction Set Design Factors *
• Operation types: how many operations to provide, and how complex should they be
• Data types: what data types will be supported?• Instruction format: length, number of operands,
fields sizes, etc.• Registers: number and type• Addressing modes: used when accessing memory
* Source: Stallings, William. Computer Organization and Architecture, 2002
Copyright 2002-2003, Irvine, Kip R. All rights reserved. 3
Important ConsiderationsImportant Considerations
• Expansion – ability to add opcodes later• Technology changes
• speed of memory access versus register access
• changes in machine word size
• changes in common applications such as multimedia that have high bandwidth
• superscalar architecture
• cache memory
Copyright 2002-2003, Irvine, Kip R. All rights reserved. 4
Intel ProcessorsIntel Processors
• Started with simple 8-bit processor (8086)• CPU was almost as slow as memory, so there were
few registers and frequent memory access
• no ability to overlap instructions
• 16-bit address fields
• Upgraded to 16-bit and 32-bit processors• CPU much faster than memory
• overlapped instruction execution
• 32-bit address fields
• had to remain backward-compatible with 8086
Copyright 2002-2003, Irvine, Kip R. All rights reserved. 5
UltraSPARC II Instruction Set UltraSPARC II Instruction Set **
• All instructions are 32 bits• Each instruction is simple (single action)• Three-operand instructions:
• Example: Add R3,R1,R2 ; R3 = R1 + R2
• Load/Store: two registers, or register + constant• Example: Load R1,(R2+R3)
• Direct Operand• restricts addressable memory range
• Indirect Operand• same number of bits as register operand• wide range of addresses
• Immediate Operand• convenient use of constant values• usually less than instruction length
Copyright 2002-2003, Irvine, Kip R. All rights reserved. 22
SIS DesignSIS Design
• SIS – Simple Instruction Set• All instructions are the same length• Opcodes vary in length (2 – 20 bits)• Registers are 5 bits (numbered 0-31)• Instructions have 0 – 3 operands• Only the load, store, conditional branch, and call
instructions contain memory offsets• Immediate operand only permitted in MOV instruction• Loosely patterned after MIPS *
* Patterson & Hennessey, Computer Organization and Design.
Copyright 2002-2003, Irvine, Kip R. All rights reserved. 23
SIS FormatsSIS Formats (1 of 8) (1 of 8)
• Format 1: Zero operands• stc ; set Carry flag
• clc ; clear Carry flag
• ret ; return from procedure
20 12
opcode - -
Copyright 2002-2003, Irvine, Kip R. All rights reserved. 24
SIS FormatsSIS Formats (2 of 8) (2 of 8)
• Format 2: Single register operand• push R2 ; push R2 onto top of stack
• pop R1 ; pop top of stack into R1
• inc (R1) ; increment indirect memory
• dec R5 ; decrement R5
20 5 7opcode reg - -
Copyright 2002-2003, Irvine, Kip R. All rights reserved. 25
SIS FormatsSIS Formats (3 of 8) (3 of 8)
• Format 3: Three register operands• add R1,R2,R3 ; R1 = R2 + R3
• mul R2,R0,R4 ; R2 = R0 * R4
• shr R3,R4,R5 ; R3 = R4 >> R5
12 5 5 5 5opcode reg regreg - -
Copyright 2002-2003, Irvine, Kip R. All rights reserved. 26
SIS FormatsSIS Formats (4 of 8) (4 of 8)
• Format 4: Load and Store• STW (myVal),R2 ; store word from R2
• LDW R4,(array) ; load word into R4
6 5 21
opcode reg offset
Copyright 2002-2003, Irvine, Kip R. All rights reserved. 27
SIS FormatsSIS Formats (5 of 8) (5 of 8)
• Format 5: Register and immediate operands• mvi R1,0FFFFFh ; move immediate into R1
• adi R2,3742 ; add immediate to R2
• mvi R3,array ; move address into R3
• cmpi R6,5 ; compare R6 to immediate
opcode reg immediate
6 5 21
Copyright 2002-2003, Irvine, Kip R. All rights reserved. 28
SIS FormatsSIS Formats (6 of 8) (6 of 8)
• Format 6: Conditional jump• jnz target
• ja loopTop
6 5 21opcode cond offset
Copyright 2002-2003, Irvine, Kip R. All rights reserved. 29
Copyright 2002-2003, Irvine, Kip R. All rights reserved. 30
SIS FormatsSIS Formats (7 of 8) (7 of 8)
oc offset
• Format 7: Subroutine call
• call mySub
2 30
Copyright 2002-2003, Irvine, Kip R. All rights reserved. 31
SIS FormatsSIS Formats (8 of 8) (8 of 8)
• Format 8: Two registers and displacement
• ldw R1,(R2+4) ; load R1 from offset R2+4
• stw (R2+8),R1 ; store R1 at offset R2+8
• ldb R1,(R2+4) ; load byte from memory
• stb (R2+8),R1 ; store byte to memory
6 5 5 16
opcode reg dispreg
Copyright 2002-2003, Irvine, Kip R. All rights reserved. 32
Expanding OpcodesExpanding Opcodes
Copyright 2002-2003, Irvine, Kip R. All rights reserved. 33
Example: Sum an ArrayExample: Sum an Array (1 of 2) (1 of 2)
.dataarray DWORD 5 DUP(?)sum DWORD ?
sum = 0;for( int i = 0; i < 5; i++ )
sum = sum + array[i];
Data:
C++/Java code:
Copyright 2002-2003, Irvine, Kip R. All rights reserved. 34
Example: Sum an ArrayExample: Sum an Array (2 of 2) (2 of 2)
mvi R6,0 ; loop countermvi R1,0 ; accumulatormvi R2,array ; R2 points to the array
top:ldw R3,(R2) ; load word from memoryadd R1,R1,R3 ; R1 = R1 + R3adi R2,4 ; point to next integeradi R6,1 ; increment loop countercmp R6,5 ; check for end of loopjb top ; continue loop
stw (sum),R1 ; store sum in memory
Implementation:
Copyright 2002-2003, Irvine, Kip R. All rights reserved. 35