Twin Logic Gates – Improved Logic Reliability by Redundancy concerning Gate Oxide Breakdown Hagen Sämrow, Claas Cornelius, Frank Sill, Andreas Tockhorn, Dirk Timmermann 03.09.2009, Natal Institute of Applied Microelectronics and Computer Engineering University of Rostock
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Institute of Applied Microelectronics and Computer Engineering
Institute of Applied Microelectronics and Computer Engineering. Twin Logic Gates – Improved Logic Reliability by Redundancy concerning Gate Oxide Breakdown Hagen Sämrow , Claas Cornelius, Frank Sill, Andreas Tockhorn , Dirk Timmermann 03.09.2009, Natal. University of Rostock. - PowerPoint PPT Presentation
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Twin Logic Gates – Improved Logic Reliability by Redundancy
concerning Gate Oxide Breakdown
Hagen Sämrow, Claas Cornelius, Frank Sill,Andreas Tockhorn, Dirk Timmermann
03.09.2009, Natal
Institute of Applied Microelectronics
and Computer EngineeringUniversity of Rostock
2
Outline
Motivation and Basics
Approaches for reliability enhancements
Gate oxide breakdown
Redundancy strategies
Redundancy on different levels
Results
Discussion
Conclusion / Outlook
3
Motivation – Known approaches
Yield enhancements
- Layout modifications
- Redundancy
Soft error resilience
- Hardening techniques
- Reusing debug resources
for redundant flipflops [Mitra]
Little effort put into
lifetime reliability
enhancements
Transient failures Permanent failures
Initial failures Failures occuringat runtime
Reliability
4
Basics – Gate oxide breakdown
Gate oxide breakdown – GOB:
Point of time a conducting path between gate and substrate is generated
Mainly dependent on:Gate oxide thicknessElectrical field at the gate