External Use TM Insights into Freescale’s VortiQa Layer 1 LTE-FDD Commercial Software, Including Performance Monitor Capabilities for Small Cell Solutions FTF-SDS-F0225 AUG.2014 Satish Singh | Manager, LTE-FDD Productization Team
External Use
TM
Insights into Freescale’s VortiQa Layer 1
LTE-FDD Commercial Software, Including
Performance Monitor Capabilities for Small
Cell Solutions
FTF-SDS-F0225
A U G . 2 0 1 4
Satish Singh | Manager, LTE-FDD Productization Team
TM
External Use 1
• Ankush Jain | Technical Leader
• Nirali Patel | Program Manager, Baseband Software
• Nitin Jain | Lead, L1 Software
• Natarajan Ekambaram | Senior Member of Technical Staff
• Sharad Kumar | Systems Engineer
Presenter Details
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Session Introduction
• In order to satisfy the rising demand for wireless data, operators
are turning to small cells to reduce network costs and increase
wireless network capacity
• By leveraging the high-performance programmable architectures,
Freescale offers a family of software-compatible devices that
scale from femtocells to macrocells
• Freescale provides not only the silicon but also a comprehensive
software solution for small cells
• Commercial grade VortiQa Layer 1 Baseband Software stack
enables fast time to market and continuous optimization for
throughputs, power and costs
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Session Objectives
• After completing this session you will be able to:
− Understand VortiQa Layer 1 Baseband Software details
− Gain insights into debug and test infrastructure provided
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Agenda
• Introduction
• Reference Development Platforms
• VortiQa Layer 1 Baseband Software
− Software Architecture
− L1/L2 Interface
− Components
− Scheduler
− Error Reporting
• Debug and Test Infrastructure
− Wireless Workbench
• Summary
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Introduction
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Integrated with L2/L3
Commercial VortiQa L1
Baseband Software
Reference Development
Platforms
QorIQ Qonverge BSC913x
SoC
Freescale LTE Femto Offering
Partner L2 / L3 Stack
Complete LTE Femto
Solution
Debugging, Diagnostic and
Testing
Tested OTA with RF in end-to-
end system testing
environment
Pantech UEs
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Why VortiQa L1 Baseband Software Offering
• To jump start small cell equipment design with commercial grade
L1 (L1) baseband software stack
• Fully tested over-the-air with RF front-end
• Integrated with partner L2/3 stacks
• Tightly coupled with QorIQ Qonverge processors for maximum
performance
• Reduce development time, risk and cost
• Enables customers to focus on value-add features
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Reference Development Platform
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QorIQ Qonverge BSC9131 Reference Design Board for
Femtocell Base Stations
BSC9131 Form Factor Reference Design Board
Features:
• Complete communications platform enabling CDMA2K, LTE, WCDMA/HSPA+
• Dual-band system covering up to 2.7 GHz
• Development and debugging tools available from Freescale and our partners
Benefits:
• Form factor design helps speed customers time to market
• Turn-key hardware design
• Integrated with Maxim and ADI RF solutions
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External Use 11
QorIQ Qonverge BSC9132 Development System for
Picocell Base Stations
Features:
• Complete communications platform enabling LTE, WCDMA/HSPA+ and WiMAXtechnologies
• Dual-band system covering up to 2.7 GHz
• Integrated Local and RRH (Remote Radio Head ) RF interfaces
• Development and debugging tools available from Freescale and our partners
Benefits:
• Faster time-to-market
• Customizable development system for picocell solutions
• Integrated with ADI RF solution
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Layer 1 Software Architecture
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Main L1 Software Objectives
• Modularity L1 software should be able to integrate different components including components from third party
• Performance optimization The Software architecture should have optimal usage of accelerators to extract maximum performance
• Reusability and migration The software architecture should scale from femtocell to macrocell
Should cover different flavors of MAPLE accelerators and multicore environments
• Test and validation Femto business model requires fully validated PHY including 3GPP conformance tests
T&V investment has to move from component testing to full system integration testing
• Ease of integration with L2 stack Use of standardized interfaces (ex. FAPI)
Smart support functionality for debug, error reporting, diagonstic, etc.
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L1 Software Architecture
Reduced Scheduling
Overhead
• Run-to-completion scheduler with
deterministic scheduling intervals
• Reduced cost for runtime
decisions as worst case
sequence is always scheduled
• Simplified multicore aware
scheduler engine
Simplified Control Layer
• Removed overhead of multiple
control and translation layers
• L2 FAPI messages are directly
parsered by each component
• Zero memcopy for L2 ctrl /
payload
Seamless MAPLE Access
• Components access MAPLE
directly through SDOS
• No additional communication
layer
SDOS
DL ctrl PDSCHPUSCH
Data
PUSCH
CSI
PUCCH
CSI
RACH
PUCCH
1/1a/1b
PUCCH
2/2a/2b
SRS Meas.
L1 / L2 Interface
RT Scheduler Framework Antenna IF Man
Cell
Search
(LTE /
WCDMA)
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Femto/Picocell (BSC913x) System Architecture
L1 Dcache L1 I Cache
Class ECM
MAPLE B2FRF I/F SEC 4.0 VeTSEC
L1 I Cache L1 DCache
L2 Cache
DDR
FSL L1AricentLinux FSL BSP
Control Packet
flow
Data Packet flow
L2/M2 Cache
e500v2
SEC DriverIPC Driver
Eth Driver
Linux N/W Stack
TCP/UDP SCTP IPSec
MAC
RLC
PDCP
GTP-UIKE/ CP
GTP-C
RRC
L1 IF
ASF - IPSec
PMAL
RT
Sched
UIO
RoHC
WC
DM
A (
25.3
2x)
X1-AP/
S1-AP
e500v2
SEC DriverIPC Driver
Eth Driver
Linux N/W Stack
TCP/UDP SCTP IPSec
MAC
RLC
PDCP
GTP-UIKE/ CP
RRC
L1 IF
ASF - IPSec
PMAL
RT
Sched
UIO
RoHC
WC
DM
A (
25.3
2x)
X2-AP / S1-AP
SC3850
WCDMA Components (26.21x)
LTE Components (SP Lib)
PUSCH
UL SCH
SSC
PMCH
SRS
PUCCH
PFICH
PBCH
PRACH
PDCCH
PHICH
BCH
PDSCH
DL SCH
PSC
MCH
IPC DriverMAPLE Abstraction Layer
IF4
S D
O S
L1 Framework
Coherency
L2 I/F
SC3850
WCDMA Components (26.21x)
LTE Components (SP Lib)
PUSCH
UL SCH
SSC
PMCH
SRS
PUCCH
PFICH
PBCH
PRACH
PDCCH
PHICH
BCH
PDSCH
DL SCH
PSC
MCH
IPC DriverMAPLE Abstraction Layer
IF4
S D
O S
L1 Framework
Coherency
L2 I/F
FAPI
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L1/L2 Interface
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External Use 18
FAPI Interfaces
• FAPI defines 4 relevant interfaces for the LTE L1:
− P4 for all network listening operations (radio sniffing)
− P5 for L1 mode control (start, stop etc)
− P7 for the main data path
− P8 for diagnostics
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Femto Forum API
• FAPI defines 4 PHY states:
− IDLE: PHY is ready to be configured for a certain deployment
− CONFIGURED: PHY is configured and ready for reconfiguration or for subframe operation
− RUNNING: PHY is in running state. Every TTI, the PHY receives UL and DL subframe requests that configure all operations within this coming TTI
− NMM: Network listening mode. The PHY is ready to listen to other radio signals for measurements
− The FAPI spec supports the implementation of a stateless PHY where all user information is stored on the L2
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FAPI Message Support
• The L1/L2 interface follows the FAPI standard
• Some minor changes were added for performance optimization (padding, payload pointers)
• Additional vendor specific fields are used for advanced measurements and additional control options
• The FAPI messages are mapped on a set of interprocessor communication channels (IPC) that handle all communication between the cores
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L1 Components
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LTE L1 Application Components
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Processing Split Between MAPLE and StarCore DSP
• High data rate shared channel operations on MAPLE accelerators:
− DL-SCH/PCH on DEPE
− PDSCH on PDPE + eFTPE
− PUSCH descrambling and demodulation on PUPE
− UL-SCH on eTVPE+PUPE
• Remaining UL channels and signals on StarCore DSP core:
− PUSCH
StarCore support on Equalization and CE
− RACH and Sounding with DFT / FFT support on MAPLE
− PUCCH
− Addional measurements
• Remaining low data rate control channels on StarCore:
− Data encoding and mapping for first control symbols (CFI, HI, DCI, PCFICH, PHICH, PDCCH) excl. IFFT
− BCH / PBCH
DL
UL
Data Control
DL-SCH PCH BCH MCH
PDSCH PBCH PMCH
CFI HI DCI
PHICH PDCCHPCFICH
UL-SCH RACH
PUSCH PRACH
UCI
PUCCH
+ DL synchronization signal on StarCore
SRS
SC3850
MAPLE
SC3850 + MAPLE
• DEPE : Turbo Encoder Processing-Element (DEPE). Accelerates Turbo Encoding and Rate Matching
• PDPE: Accelerates LTE DL processing (Scrambling, modulation, Layering, Pre-coding and Mapping)
• eFTPE: Enhanced FFT/DFT PE. Accelerate FFT and various pre/post transform processing.
• PUPE: Accelerates LTE UL processing (De-Mapping, De-scrambling and De-interleaving).
• eTVPE: Enhanced Turbo/Viterbi PE. Accelerates Turbo Decoding, Rate-De-Matching and HARQ combining
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MAPLE / Core Split in LTE Uplink
eFTPEFFTGR
CP RemFFT
Guard R.
eFTPE
eFTPE
2/2 tfje
IDFTeTVP
E
CETOEFOE
PUSCH_EDF MAPLE – B2F
PUSCH Ref. Symbols (Frequency domain CE)
CE
PUCCH, all formats
UE separation
TOE
ZC
FIRDelay profile
compute
RACH
SRS
ZC
AntennaData (IF4)
TB out
Control output
RACH output
PUPE
cores Maple
legendNoise est.
EQ DTX / RMDec
Delay profile analyze
f
eFTPE
IFFT
eFTPEDFTGR
f
SNRest
SRSoutput
f
EQ
H N
CRCPE
PUSCH_EDF MAPLE – B2P
eFTPE
IDFT
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External Use 25
MAPLE / Core Split in LTE Downlink
• MAPLE accelerates the full downlink data path
• Core intervention is only needed for the control symbols
• Higher data rate has hence no impact on the core loading
TB input
Control intput
PDCCH
DEPE PDPE
PDSCH_EDF
Downlink controls symbols in SW
eFTPE
Guard insertIFFT
CP insert
AntData
CRCPE
PBCH, RS
cores Maple
legend
PHICH
PCFICH
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LTE / WCDMA Cell Search
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LTE Cell Search
• Sniffing modes Dynamic mode (enB <-> Sniffing)
Directed single cell search (eg/. PCID = 270)
Multi-cell search (eg. PCIDs = 40, 200, 450, 10)
Exhaustive cell search - Active neighboring cells
• Supported Physical Channels PSS/SSS – PCID
Management Information Base (MIB)
System Information Base - SIB1, SIB2, and full SIB decode capabilities
• Bandwidth Support Currently supported bandwidths 5, 10, 15, and 20MHz
Upcoming support - 1.4, 3 MHz
• Platform/SoC Designed for QorIQ Qonverge BSC9131, BSC9132, B3421
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External Use 28
WCDMA Cell Search
Buffered I,Q
samples
Request
BCCH
Decode on
UARFCN-a
Run
BCCH
Decode
Request
Cell Search
on
UARFCN-a
Run
Cell
Search
UARFCN-a
selectMeasure
RSSI
AIC
Cfn/Ind
Cell Search
on
UARFCN-a
Cfn/Ind
BCCH Decode
(xtiple inds can
be there)
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External Use 29
L1 Scheduler
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External Use 30
Sym IdTasks (Scheduled to start on Sym Id)
Scheduling on BSC9131
Tasks (Scheduled to start on Sym Id)
Scheduling on BSC9132
0Job_builder (N), PUCCH (N-1), PUCCH
(N-1), EQU(N-1)Job_builder (N), PUCCH (N-1), EQU(N-1)
1PUFFT(N), PUSCH_EDF(N-1),
BCH_ENC(N)
PUSCH_EDF(N-1), BCH_ENC(N),
SRS_GRP(N-1)
2 SRS_GRP(N-1) PUCCH (N-1), PDCCH(N)
3 RACH_TDP(N), PUCCH (N) PUFFT(N), RACH_TDP(N), PUCCH (N)
4RACH_FDP(N-1), RSP_DMRS(N),
RSP(N), EQU(N)
RACH_FDP(N-1), RSP_DMRS(N), RSP(N),
EQU(N)
5
6 RACH_TDP(N), PDSCH(N) RACH_TDP(N), PDSCH(N)
7 PUCCH(N), SRS_SEP(N-1), EQU(N) PUCCH(N), SRS_SEP(N-1), EQU(N)
8 PDCCH(N) SRS_CE(N-1)
9RACH_TDP(N), RACH_DPP(N-1),
SRS_CE(N-1)RACH_TDP(N), RACH_DPP(N-1)
10 RSP_DMRS(N), PUCCH(N) RSP_DMRS(N), PUCCH(N)
11FAPI (N) + CQI_DEC (N-1), RSP(N),
EQU(N)RSP(N), EQU(N)
12 RACH_TDP(N) FAPI(N) + CQI_DEC (N-1), RACH_TDP(N)
13 RACH_TDP(N) RACH_TDP(N)
L1 Scheduling
• L1 scheduling follows run to completion model
• The FAPI control information will determine which components are actually executed in each subframe
• Each component is statically tiggered based on the symbol number
• The scheduling scheme is tailored for the worst case load
• Uplink processing (RACH, PUSCH, PUCCH, SRS) is spread out over the two subframes
• Underlined jobs represent a scheduling difference between BSC9131 and BSC9132
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External Use 31
L1 Scheduling: High Core Load Handling –
Detection and Job Removal
• High core load scenario
− In case of high core load, time critical tasks may get pushed out which can be FATAL for the system
− This case may arise due to
Unknown system behavior
Wrong input to L1
• High core load detection
− L1 scheduler detects whether jobs are missing deadline
− Remove Jobs missing deadline for SF=N, also remove scheduled Jobs that are dependent on removed Jobs
− Sends appropriate FAPI indication
− Sends error indication
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External Use 32
• Following UL channels would be impacted by stopping jobs
− RACH
− ULSCH
• Transparent to L2. L1 would send modified FAPI indication with
appropriate SFN/SF, RNTI,…
− For example, if RACH jobs were dequeued
RACH.Indication will report ‘0’ RACH preambles detected
• However, L2 can know which channel was impacted by reading
Error.Indication message
High Core Load Handling – System Level Impact
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Error Reporting
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External Use 34
Errors Reported By L1 – Error.Indication Message Body
Field Type Description
message_id UINT8Indicate which message received by the
PHY has an error
padding[3] UINT8 To make error_code aligned to 32-bits
error_code UINT32 The error code
Error code
dependent valuesstruct
The format of these bytes is dependent on
the error code
See Below Tables for details
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External Use 35
Errors Reported By L1 – Error.Indication Message Body
Value Error Code Description Msg Id Padding[0] Padding[1]
1MSG_INVALI
D_STATEThe received message is not valid in the PHY's current state. 0x04 NA NA
1MSG_INVALI
D_STATE
If values listed in Padding [0] byte correspond to FSL FATAL Error
Codes, L1 is in FATAL state and L2 shall start L1 recovery process.0xFF
FATAL Err
Code.
Please refer
to Table 5.
NA
3SFN_OUT_O
F_SYNC
The DL_CONFIG.request was received with a different SFN than
the PHY expected0x80 NA NA
4MSG_SUBF
RAME_ERR
Either an error was received in DL_CONFIG.request or
DL_CONFIG.Req message was not received0x80
SFN_SF of last processed
DL_Config.Req message
4MSG_SUBF
RAME_ERR
One of the following error was detected in UL_CONFIG.request
1. PDUs received were less than expected PDUs
2. Same pucch_index in SR information was allocated to more
than 1UE
3. Same pucch_index in CQI information was allocated to more
than 1UE
0x81SFN_SF of last processed
DL_Config.Req message
4MSG_SUBF
RAME_ERR
A non-FATAL Error has happened with any of following conditions:
0xFF
1. Used by L1 scheduler to indicate if it skips processing of L1
channels due to system load. This functionality of L1
scheduler is disabled by default.
NON-FATAL
Err Code.
Please refer
to Table 6.
Symbol on
which Job
was skipped
1. Incorrect RB allocation or More than 4 PUSCH users
scheduled
NON-FATAL
Err Code.
Please refer
to Table 6.
NA
1. L1 component detected an errorSFN_SF of last processed
DL_Config.Req message.
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External Use 36
Additional Errors Reported by L1Value Error Code Description
64 FSL_FATAL_ERR_CODE_START FATAL Error code Starts
65 AIC_Rx_DMA_OVERRUN_ERR Rx DMA overrun has occurred
66 AIC_Tx_DMA_UNDERRUN_ERR Tx DMA underrun has occurred
67 AIC_JESD_TIMEOUT_ERR JESD time out has occurred
68 DMMU_ERR DMMU error has happened
69 IMMU_ERR IMMU error has happened
70 HWI_DBG_ERR Reserved Field.
71 COMP_ERR L1 component has reported an error
72 FAPI_ERR_LINE_NUMBER Send the line number of an error pertaining to L1 to FAPI.
Value Error Code Description
128 FSL_NON_FATAL_ERR_CODE_START Non-FATAL Error code Starts
129 DL_CONFIG_NOT_RECEIVED Not Used
130 UL_CONFIG_NOT_PROCESSED Not Used
131 RACH_JOBS_MISSED_DEADLINEThese three errors have disabled by default. If needed, the errors can be enabled in
function extref_job_deadline_miss( )132 RSP_JOBS_MISSED_DEADLINE
133 EQ_JOBS_MISSED_DEADLINE
134 WRONG_RB_ALLOC_BY_L2
Number of RB allocated by L2 is more than that supported for configured BW and when
number of PUSCH_RB allocated by L2 is 0. If this error is detected, L1 does not process
any of the ULSCH PDUs for this UL_Config.
135 CFICH_PHICH_DCI_CA_INVOKED PCR command is sent to the maple when DLCCH processing enters in 10th symbol.
136 MORE_PUSCH_USERS_SCHEDULEDIf L2 schedules more than 8 ULSCH PDUs in a Subframe, L1 does not process any of
the ULSCH PDUs for current UL_Config.
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External Use 37
Wireless Workbench
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External Use 38
Wireless Work Bench Toolkit
• RF Verifier
• PHY Tester
• Conformance Tester
• Diagnostic Monitor
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External Use 39
Wireless Workbench - Tools
Diagnostic Monitor
Protocol Diagnostics- FAPI Logging
- Real time eNodeB Statistics
- Record & Playback sessions
Module Debug & Diagnostics- Detailed insight into VortiQa L1
Platform Diagnostics
“Insight that raises performance & quality”
PHY Tester
Independent Layer1 Validation Tool
- Simulated Layer2 Agent on PowerPC
- 3GPP Rel8&9 & FAPI v1.1 Compliant
- Ready to use Test Suite for Functional & Channel Characterization
- Call Model (Layer1 Load Testing)
“3GPP & Use Case Compliant Solution”
RF Verifier
Basic RF Interface Validation Tool
- Support of various LTE BW
- Support for all DL ETM Models
- Ability to capture Uplink IQ Samples
- Layer 1 Independent Operation
“Ready for SW Development”
Conformance Tester
Supports 36.141
- Chapter 6 and Chapter 8 Tests
- HomeBS Configuration
End to End integrated solution with
- R&S SMU200A
- R&S FSV
“Conformance Compliant Solution”
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External Use 40
Wireless Work Bench
Wireless Work Bench – High-Level Architecture
QorIQ Linux
LTE L2/L3 StackL2 Simulator
Diagnostics
Sniffing Agent
RF Tool
StarCore SDOS
Freescale LTE L1
Software System
RF Driver
RF Verifier
PHY Tester
Diagnostic Monitor
R&S SMU 200A Aeroflex TM500
FSL HW (MAPLE)
RF (3rd Party)LTE RF
IEEE
488
TCP/IP SocketConformance
Tester
3rd Party RF Testers
FA
PI
QA
M S
ym
bo
ls
TCP/IP Socket
TCP/IP Socket
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External Use 41
Testing
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External Use 42
Integration and Testing
• Integration
− Intgrated with L2, L3 and transport software
− Tested on QorIQ Qonverge BSC9131/9132 processors
− L2/L3 software for LTE-FDD/TDD and WCDMA (licensed by Aricent and
CCPU/RadiSys)
− Transport software, including IPsec, QoS backhaul, etc., through
Freescale’s VortiQa software (licensed by Freescale)
− Development tools and operating system software
(available through Freescale and ecosystem partners)
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External Use 43
User 1Laptop with Pantech data card
User 0Laptop with PanTech data card
CodeWarrior PC
PC2, Windows XP
CodeWarrior for L1
9131 RDB
RF Card
BSC 9131
eNodeB
L1
eNodeB
L2/L3
RF
JTAG
Linux BSP PC
PC3, Linux FC11
(L2/L3 build, Wireshark and Minicom)
EPC PC
PC4, Linux FC11EPC Core Network Simulator (MME/
S-GW/P-GW)
LAN 2
172.16.118.144
172.16.118.18
172.16.118.151
SERIAL
Antenna
Interoperability Test Using Pantech Commercial UEs
UTRAN - FAP EPCUE
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External Use 44
Interoperability Test Using T-Mobile Commercial UEs
Windows Host PC, XP/WIN7
T-Mobile UE
(Internet Manager)
9131 RDB
RF Card
BSC 9131
eNodeB
L1
eNodeB
L2/L3
EPC PC, Linux
LTE EPC (MME/SGW/PGW) and (Minicom/SCP/TFTP)
LAN
172.16.118.144
172.16.118.151
SERIAL
eth0
Ant0Ant1
23.45.67.12
PDN PC, Linux
PDN Ping/Iperf
172.16.10.10
USB
11.0.0.5
RF Link
T-Mobile UE E398
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External Use 45
VortiQa Layer 1 FDD Software
Feature Set
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External Use 46
Salient Features – VortiQa L1 FDD Software Supported
on BSC9131/9132 SoC
BSC9131 SoC• 3GPP release 9 support
• Maximum aggregate PHY throughput – 150 Mbps
• Maximum throughput at 20 MHz - 110 Mbps DL / 37 Mbps UL
• Multi bandwidth support (1.4, 3, 5, 10, 15 and 20 MHz)
• Qualified on multiple RF bands (1, 7, 10, 12, 13)
• Up to 32 active UEs and up to 4 UE / TTI support
• Downlink 2x2 MIMO and uplink receive diversity support
• Localized and distributed PDSCH, localized PUSCH
• Downlink control channel support (PDCCH, PHICH, PFICH, BCH,SSH)
• All PUCCH formats (1/1a/1b/2/2a/2b)
• Closed loop power control (PUCCH, PUSCH)
• V1.1 FAPI compliant (partial and full reconfiguration)
• Frequency hopping and SRS support
• 3GPP 36.141 conformance
• Cell search (TDD LTE, FDD LTE, WCDMA bands)
• Handover (X2) and measurements support
• Fully end-to-end and handover tested with 3rd party L2 and EPC
• Interoperability with test and commercial UEs (FFA, Pantech, AeroFlex)
BSC9132 SoC• 3GPP release 9 and 10 support
• Maximum aggregate PHY throughput – 225 Mbps
• Maximum throughput at 20 MHz - 150 Mbps DL / 75 Mbps UL
• Multi bandwidth support (1.4, 3, 5, 10, 15 and 20 MHz)
• Qualified on multiple RF bands (1, 7, 10, 12, 13)
• Up to 64 active UEs and up to 8 UE / TTI support
• Downlink 2x2 MIMO and uplink receive diversity support
• Localized and distributed PDSCH, localized PUSCH
• Downlink control channel support (PDCCH, PHICH, PFICH, BCH,SSH)
• All PUCCH formats (1/1a/1b/2/2a/2b)
• Closed loop power control (PUCCH, PUSCH)
• V1.1 FAPI compliant (partial and full reconfiguration)
• Frequency hopping, SRS and CoMP support
• 3GPP 36.141 conformance
• Cell search (TDD LTE, FDD LTE, WCDMA bands)
• Handover (X2) and measurements support
• Downlink carrier aggregation, MBSFN, PRS and eICIC support
• Fully end-to-end and handover tested with 3rd party L2 and EPC
• Interoperability with test and commercial UEs (FFA, Pantech, AeroFlex)
Green highlights difference between BSC9131 and 9132 feature
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Summary
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External Use 48
Summary
• Fully End-to-End tested turnkey L1 commercial SW
• Significantly shortens time-to-market for customers
• L1 tested with market leading RFIC and PAs (FSL offering)
• L1 fully integrated and tested with leading 3rd party LTE stacks
(Aricent, Radisys)
• Provides comprehensive tools for PHY diagnostics, operations and
maintenance.
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External Use 49
Demos
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External Use 50
Demos at Technology Lab
Pedestal #405
TM
© 2014 Freescale Semiconductor, Inc. | External Use
www.Freescale.com