June 18, 2008 S. J. Ben Yoo S. J. Ben Yoo UC Davis Campus CITRIS Director UC Davis Campus CITRIS Director Dept of Electrical and Computer Engineering, UC Davis Dept of Electrical and Computer Engineering, UC Davis [email protected][email protected]Innovations in Energy Use Future Information Technology
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June 18, 2008
S. J. Ben YooS. J. Ben YooUC Davis Campus CITRIS DirectorUC Davis Campus CITRIS DirectorDept of Electrical and Computer Engineering, UC DavisDept of Electrical and Computer Engineering, UC [email protected]@ece.ucdavis.edu
Innovations in Energy Use
Future Information Technology
June 18, 2008Slide_2
Next Generation Data Center
Data Centers and Super Computers
MegaWatts of Power
100’s of racks
June 18, 2008Slide_3
$ for Power and Cooling in Data Centers
Courtesy: IBM research
June 18, 2008
Today’s Data Center:
> 10 MegaWatts of Power
100’s of racks
Data Center on a Cell Phone/PDA
Pico_DataCenter
1 – 4 Watt
200 W – 500 W example Pico_DataCenter Cluster
Data Center on a Chip
June 18, 2008
Power Consumption in Electronic IP routers (e.g. CISCO CRS-1)
7%
11%8.5%
25%
3.5%10%
10%25%
ASICs(assume ~12 x 90nm devices)
Memories in Forwarding Engine
Packet Buffer Memories(DRAM)
I/O (optics/framers/MACs/L2 functions)
Control Plane (2 x Route Processors & Control
Plane portion of linecardsincluded)
Switch Fabric(both the centralised components and the part on
the linecards)
Blowers(depends very much on box topology, could be
much higher)
Power Supply efficiency loss(both the 48V input supplies and
the linecard DC:DC included)
Capacity: 320 Gb/s(640 Gb/s LAN)
213 cm
91 cm 60 cm
Power: 10.8 kW
Physical Size: 213x91x60 cm3
Data by Garry Epps of CISCO
June 18, 2008
1,152 slots of 40 Gb/s line cards in 80 shelves (72 linecard shelves and 8 fabric shelves)),
Power Consumption: ~0.85 MW
Weighs: 56,656 kg
Footprint: 50 m2
Each Port Protocol Specific up to OC-768
1024 x 1024One Semiconductor Chip Switching Fabric
Power Consumption: ~500 W (200W)
Weighs: 10 kg
Footprint: 0.1 m2
Each Port Protocol Independent up to OC-768Can achieve Packet /Burst /Circuit Switching
Conventional System All-Optical System on a Chip
MA
CM
AC
46 Tb/s optical routing system on a Chip
BufferMemory
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MemoryMA
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BufferMemory
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ACBuffer
MemoryMA
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BufferMemory
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ACBuffer
MemoryMA
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MemoryMA
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MemoryMA
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20 nJ/b system 10 pJ/b system
June 18, 2008
Overlay Photos: IEEE Spectrum, October 2006
Next Generation Health Care
June 18, 2008
Q&A
June 18, 2008
Incollaboration withProf. Bernd HamannUCD IDAVand Tom Nesbitt UCDMC
• Real-time 3-D Visualization will require ~1 Tb/sec
bandwidth in the future
1000
x 1000
x 1000 pixels/frame
x 28 bit/pixel
x 30 frames/sec
~ 1 Tb/sec
Real-time, On-line, Collaborative Healthcare
June 18, 2008
Chip-Scale Optical Router Micro-system
S. J. B. Yoo, “Ultra-Low Latency Multi-Protocol Optical Routers for the Next Generation Internet,” U. S. Patent 6,925,257 B2 (2005).S. J. B. Yoo, “Integrated Optical Router,” U. S. Patent 6,768,827 (2004).S. J. B. Yoo, “Ultra-Low Latency Multi-Protocol Optical Routers for the Next Generation Internet,” U. S. Patent 6,519,062 (2000).S. J. B. Yoo, “Wavelength Converter with Modulated Absorber,” U. S. Patent 6,563,627 (2001).S. J. B. Yoo, “Compact Optical Receiver with Optical Signal Processing Capabilities,” U. S. Patent pending (2001).S. J. B. Yoo, G. K. Chang, “High-Throughput, Low-Latency Next Generation Internet Using Optical Tag Switching,” U. S. Patent 6,111,673.(1997)
June 18, 2008
Moore’s law vs. Processor Performance
Center for Computing of the Future
Overview
Energy Efficient Large-Scale Computing with Nanophotonic Interconnects
Center for Computing of the FutureCenter for Computing of the Future
OverviewOverview
Energy EfficientEnergy Efficient LargeLarge--Scale Computing with Scale Computing with NanophotonicNanophotonic InterconnectsInterconnects
S. J. Ben Yoo (UC Davis), Venkatesh Akella (UCDavis), Raj Amirtharajah (UCDavis), Bevan Baas (UCDavis), Keren Bergman
(Columbia), Van Carey (UC Berkeley), Shanhui Fan (Stanford), Soheil Ghiasi (UC Davis), James Harris (Stanford), Saif Islam (UC
Davis), Michal Lipson (Cornell), Kai Liu (UCDavis), David Miller (Stanford), James Shackelford (UC Davis), and many others
Ref. “Cramming more components onto integrated circuits” by Gordon Moore, Electronics, Vol. 38. April 19, 1965
Ideal vs. Actual Scaling
Courtesy: IBM research
‘Power Cliff’ and Opportunities
Courtesy: IBM research
Key Challenges
• Performance/watt is the riding the Moore’s law curve
• Gap between peak versus averageperformance
• Pins limits the I/O bandwidth• Leakage and process variation are get worse
as we go to 32nm and beyond• Parallelism is way forward but interconnect
becomes the key - both onchip and offchip
The Rise of Chip Multiprocessors (CMPs)• Emerging trend replicate computational logic: maintain
processing throughput while lowering clock frequencies and supply voltages.
• Parallel architectures:
– better processing performance per watt
• Power– The GHz race is grinding to a halt
Pdyn ∝ Vdd2⋅ fPleak ∝ Vdd ⋅ exp(-qVt/(kT))
– 2 cores at and
– ~4x reduction in dynamic power – equal performance
• As number of cores grows, key is to performance: scalable, fast, and power-efficient:
interconnection networks
2ddV
2f
Balancing Computing and Communications
• Amdahl’s rule => match computation and communications for best operation.– Currently, growing gap between actual computer
performance and the theoretical maximum performance rating.
– Current trends in decreasing Bytes/FLOP• 10 TeraFLOPS chip will need 10 TB/sec or ~100
Tb/s communications !! (US wide Internet traffic is ~3 Tb/s today)
• Electronic communications on-chip will no longer keep up with the demand and power efficiency requirement
Balancing Bandwidth and FLOPS
Figure: Courtesy Robert Drost,
Stanford IFC Meeting, Dec 2006
Design Space
1 byte per flop
Amdahl’s rule => match computation and communications for best operation.
10 TeraFLOPS chip will need 10 TB/sec or ~100 Tb/s communications !! (US wide Internet traffic is ~3 Tb/s today)
Bandwidth versus Memory Capacity
Figure: Courtesy Robert Drost,
Stanford IFC Meeting, Dec 2006
PicoBlade Design Space
1 byte per flop
Electrical interconnects => local interconnects
Courtesy: IBM research
Optical Interconnects => High-way interconnects
Source: IBM
Issues-Next Generation Computing Systems
• Performance/power ratio is a real issue• Memory I/O bottleneck, Power bottleneck• Optics and Electronics can help each other• Optics is especially good at interconnecting
in parallel without impedance, crosstalk, and timing-jitter concerns
• Parallel processing is good, but software, virtualization, and resource management must work.
• We need a systematic approach
Imagine:
• Next Generation Computing System with– Massively parallel ‘pico-blades’ optically
interconnected with massive number of multiple wavelength
– 3-D integration of the above on a very compact ‘chip’by nanophotonics & nanoelectronics
– Intelligent virtualization and resource managementPhase I Phase II
Today
What is Proposed:• 10 year project aiming at x100~x1000
improvement in power efficiency and miniaturization
• New Computing Architecture combining optics, electronics, and embedded intelligence
• New Virtualization and Resource Management• Hardware
• Thermal Engineering• Systems Integration• Emulation and Experimental Testbed Studies
Proposed Center Thrusts• Thrust 1: Next Generation Computing System Architecture• Thrust 2: Resource Management and Virtualization• Thrust 3: Computing System EnablingTechnologies
• Thrust 4: Systems Integration - Picoblade Cluster Data Center - 3-D Chip Integrated Multicore.- Hardware-Software Integration
• Thrust 5: Testbed and Application Studies– Emulation & Simulation studies– Learn from research data center testbeds and try prototypes
• Partnership with HP Data Center Research Testbed, UC Berkeley Data Center Testbed, LBL Data Center, etc.
– Healthcare Applications
UC DavisElectrical Engineering
S.J. Ben Yoo
UC BerkeleyMechanical Engineering
Van Carey
UC DavisComputer Engineering
Bevan Baas
UC DavisComputer Engineering
Rajeevan AmirtharajahProject Leaders:
Columbia Univ.
Electrical Engineering
Keren BergmanCo-Thrust Leader:
UC DavisComputer Engineering
Venkatesh AkellaThrust Leader:
Thrust 1: Next Generation Data-Center Architecture
Thrust 1: Next Generation Computing System/ Data Center Architecture
What’s in a blade?
High Level System View
• PicoBlade composition explorationa) Multi-core CPUs + DRAMb) Multi-core CPUs + DRAM + Flash c) Multi-core CPUs + DRAM + Flash
+ energy-efficient hard disk (distributed disk farm, or for caching)
• Example system cluster– PicoBlades interconnected with optical interconnect– Energy-efficient computation
balanced with high-speed communication
– Hierarchical Optical Networking
1 – 4 Watt PicoBlade
200 W – 500 W example cluster of PicoBlades
Optical vs Electrical Interconnects
Delay distribution of 1 cm optical
Connect (Chen et. al SLIP 2005)PDP comparison of electrical And optical interconnect for a1 cm wire
Power consumption (mw) 1 CM
optical datapath
(source: Chen et. al SLIP 2005) Comparison of BW density today
PicoBlade – Rationale • Goal: performance/watt ~ 2000 (100x better than HS21 @ the
same technology node)• System Architecture - integrated and balanced approach to
blade design: – processor+I/O+memory with focus on energy per transaction
• Heterogeneous compute engines• Codesign of Electrical and Optical Interconnect
– Electrical local interconnets and Optical high-way interconnects– Where to draw the line with between electrical and optical
interconnect in the context of 3D chips– Optical interconnect between layers in 3D– Use of multiple wavelengths – Optical Clock Distribution
• Codesign of Interconnect and Processor Cores– Do we need large L2 caches if low latency, high bandwidth
interconnect is available via optical links?– Heterogeneous cores including FPGA fabrics for some cores.– Simple cores communicating to a large memory (DRAM) via 3D
interconnect technology.
Supporting Evidences1. ASAP (ISSCC 2006, HotChips 2006) - UC Davis
• 36 processor, 180 nm, scalable GALS array• 600+ MHz @ 2.0V, 600+ MOPS in 0.66 mm^2• 5-10x performance and 10-75x lower energy than
8-way VLIW TI C62X• 167 processor, 1.1 GHz, 65 nm chip in development: working!
(latency) by 15% to 55% with 0.08 degree rise in peak temp
• Off-chip BW is reduced by 66% on average• 3D scaling with 3D partitioning of a Pentium can increase
performance by 8% and reduce power by 34% • RMS workloads
3. PicoServer (ASPLOS 2006) - Michigan• 10x improvement in performance/watt over Pentium-4• On the same die area, 12 CPU with no L2 outperforms 8CPU with a
on-chip cache by 15% with 55% lower power• Tier1 Servers (Webservers workload)
4. MICRO 2006 - Cornell• On chip optical buses (2D, 4-12 wavelengths, Si waveguides, 64
core CMP in 32nm)• Effectively latency is reduced by 26%• 26% - 39% improvement in latency
Rapid Tuning (~ 1 nsec) of T_WC to achieve switching in
Wavelength, Time, Space domainsScalable to 42 Petabit/sec capacity32*(2562x2562) connectivity
T_WC
T_WC
T_WC
T_WC
F_WC
F_WC
F_WC
F_WC
switch control
Tunable Wavelength Converters
λ-router(AWGR)
controller
TIME
WAVELENGTH
SPACE
Fixed Wavelength Converters
Chip-Scale Optical Router Micro-system
S. J. B. Yoo, “Ultra-Low Latency Multi-Protocol Optical Routers for the Next Generation Internet,” U. S. Patent 6,925,257 B2 (2005).S. J. B. Yoo, “Integrated Optical Router,” U. S. Patent 6,768,827 (2004).S. J. B. Yoo, “Ultra-Low Latency Multi-Protocol Optical Routers for the Next Generation Internet,” U. S. Patent 6,519,062 (2000).S. J. B. Yoo, “Wavelength Converter with Modulated Absorber,” U. S. Patent 6,563,627 (2001).S. J. B. Yoo, “Compact Optical Receiver with Optical Signal Processing Capabilities,” U. S. Patent pending (2001).S. J. B. Yoo, G. K. Chang, “High-Throughput, Low-Latency Next Generation Internet Using Optical Tag Switching,” U. S. Patent 6,111,673.(1997)
1,152 slots of 40 Gb/s line cards in 80 shelves (72 linecard shelves and 8 fabric shelves)),
Power Consumption: ~0.85 MW
Weighs: 56,656 kg
Footprint: 50 m2
Each Port Protocol Specific up to OC-768
1024 x 1024One Semiconductor Chip Switching Fabric
Power Consumption: ~500 W (200W)
Weighs: 10 kg
Footprint: 0.1 m2
Each Port Protocol Independent up to OC-768Can achieve Packet /Burst /Circuit Switching
Conventional System All-Optical System on a Chip(scalable to 2 million x 2 million,
42 Petabit/sec interconnection)MA
CM
AC
46 Tb/s optical routing system on a Chip
BufferMemory
BufferMemoryM
ACBuffer
MemoryMA
C
BufferMemory
BufferMemoryM
ACBuffer
MemoryMA
C
MA
CM
AC
BufferMemory
BufferMemoryM
ACBuffer
MemoryMA
CBuffer
MemoryBuffer
MemoryMA
CBufferMemoryMA
C
MA
CM
AC
BufferMemory
BufferMemoryM
ACBuffer
MemoryMA
C
BufferMemory
BufferMemoryM
ACBuffer
MemoryMA
C
MA
CM
AC
BufferMemory
BufferMemoryM
ACBuffer
MemoryMA
C
BufferMemory
BufferMemoryM
ACBuffer
MemoryMA
C
MA
CM
AC
High Level System View
• PicoBlade composition explorationa) Multi-core CPUs + DRAMb) Multi-core CPUs + DRAM + Flash c) Multi-core CPUs + DRAM + Flash
+ energy-efficient hard disk (distributed disk farm, or for caching)
• Example system cluster– PicoBlades interconnected with optical interconnect– Energy-efficient computation
balanced with high-speed communication
– Research topics: clustersize and inter-clustercommunication topology
• Emulation studies of the next generation data center/supercomputer
• Simulation studies of the next generation data center/supercomputer
• Learn from research data center testbedsand try out new prototypes
Incollaboration withProf. Bernd HamannUCD IDAVand Tom Nesbitt UCDMC
• Real-time 3-D Visualization will require ~1 Tb/sec
bandwidth in the future
1000
x 1000
x 1000 pixels/frame
x 28 bit/pixel
x 30 frames/sec
~ 1 Tb/sec
Overlay Photos: IEEE Spectrum, October 2006
Data Centers for Health Care and Telemedicine
Bird’s Eye View of the Schedule
Overlay Photos: IEEE Spectrum, October 2006
Workplans and Deliverables-Phase I• Phase I: April 2008-March 2013• Phase II: April 2013- March 2018• Year 1:
– Next Generation Data Center Architecture Comparisons and Full Simulations
– Virtualization and Resource Management Plans– Pico Blade I architecture design– Plasmonic, AWGs, Ring Photonic Device Operational
• Year 2: – Next Generation Data Center Architecture Refinement– Virtualization and Resource Management Implementation– Pico Blade I architecture prototyping– Plasmonic, AWGs, Ring Photonic Device with Electronic Interface
Operational• Year 3:
– Pico Blade I completion– Ring based interconnects operational
• Year 4:– Pico Blade I cluster with virtualization operational – Optical Interconnect Plane – ASAP II Integration operational
Workplans and Deliverables-Phase II
• Year 5: – Pico Blade II completion– Plasmonic, AWGs, Ring Photonic Device with Electronic Interface
Integration with Vertical Vias to ASAP III
• Year 6: – Next Generation Architecture x100 performance/watt completion
• Year 7: – Optical Interconnect- Memory-Processor Plane Design– Testbed with Pico Blade II cluster operational
• Year 8: – Medical Application with Pico Blade II cluster operational– Optical Interconnect- Memory-Processor Plane Co-Design– Pico Blade III design
• Year 9:– Optical Interconnect- Memory-Processor Plane Integration
• Year 10: – Next Generation Architecture x1000 performance/watt completion
Next Generation Data Centers and Computing SystemsS. J. B. Yoo, V. Akella, R. Amirtharajah, B. Baas, K. Bergman, V. Carey, S. Fan, S. Ghiasi,
J. S. Harris Jr., M.S. Islam, M. Lipson, K. Liu, D.A.B.Miller, J. Shackelford, and many others
Figure: J. D. Joannopoulos, P. R. Villeneuve, and S. Fan, Nature, vol. 386, pp. 143 (1997)
10 year team efforts towardsX100~1000 improved performance/power
We appreciate your Partnership
June 18, 2008
What is Proposed:10 year project aiming at x100~x1000 improvement in power efficiency and miniaturizationNew Computing Architecture combining optics, electronics, and embedded intelligence New Virtualization and Resource ManagementHardware
S. J. B. Yoo, “Ultra-Low Latency Multi-Protocol Optical Routers for the Next Generation Internet,” U. S. Patent 6,925,257 B2 (2005).S. J. B. Yoo, “Integrated Optical Router,” U. S. Patent 6,768,827 (2004).S. J. B. Yoo, “Ultra-Low Latency Multi-Protocol Optical Routers for the Next Generation Internet,” U. S. Patent 6,519,062 (2000).S. J. B. Yoo, “Wavelength Converter with Modulated Absorber,” U. S. Patent 6,563,627 (2001).S. J. B. Yoo, “Compact Optical Receiver with Optical Signal Processing Capabilities,” U. S. Patent pending (2001).S. J. B. Yoo, G. K. Chang, “High-Throughput, Low-Latency Next Generation Internet Using Optical Tag Switching,” U. S. Patent 6,111,673.(1997)
June 18, 2008
1,152 slots of 40 Gb/s line cards in 80 shelves (72 linecard shelves and 8 fabric shelves)),
Power Consumption: ~0.85 MW
Weighs: 56,656 kg
Footprint: 50 m2
Each Port Protocol Specific up to OC-768
1024 x 1024One Semiconductor Chip Switching Fabric
Power Consumption: ~500 W (200W)
Weighs: 10 kg
Footprint: 0.1 m2
Each Port Protocol Independent up to OC-768Can achieve Packet /Burst /Circuit Switching
But…it Fails oftenRequires human interventionsVulnerable to security attacksDoes not work towards team resultsNever learns and prone to make the same mistakes
Future Internet will face more security attacks, more diverse physical layers, and more demanding applications
June 18, 2008
Example– Denial of ServiceMalicious attacks
Each network element only sees his/her perspective (surge in traffic) and fails to see a pattern
Vulnerability and failures
Restores only after patches are developed days later (too late)
June 18, 2008
Learn from Biological Systems• Biological Systems work remarkably well through coordination between Brain, Reflex, Sensors, and Actuators.• Brain reasons from partial and conflicting informationfrom sensors by extracting Spatio-Temporal patterns• Reflex provides rapid hard-wired responses • Brain-Reflex provides rapid yet reasonable responses• Cognitive Learning capabilities• Homeostasis -- excellent control of critical functions • Immunization and Vaccination (anti-body)• Teamwork– Colony of ants and bees capable of locating source of food, finding the best path to that source and transmitting that information to other members of their team
June 18, 2008
Cognitive Network Control and Management:Brain-Reflex like Signaling and Control
Brain: Interelement Control Slow but elaboratePerformance monitoring based on labelsAnomaly detectionOverall view of network (topology)Listens and instructs the Reflex
Reflex: Distributed ControlRapid and reflex-likePacket forwardingAnomaly detection Communicates with the Brain
Network Control and Management
June 18, 2008
SensorNetwork
Storage Area Network
Core RouterIPNE
DATA
LABEL
Legacy IP Network
WirelineMPLSIPNE
DATA
LABEL
Optical Label SwitchingNetwork
WirelineO-CDMA LAN
SatelliteNetwork
ReconfigurableWirelessNetwork
Next Generation Heterogeneous Networking
• Internet becoming more and more diverse in application and technology
• Any application on IP, IP on any networking technology
• End-to-end principle
June 18, 2008
100G serial transport
•Use single wavelength (can be multi-level)• Needs 100 G (or 2x50G) electronics• Better spectral efficiency but more sensitive to dispersion and PMD
• Use multiple wavelengths & modulators• Needs 10 G electronics with possible synchronization• Manageable dispersion and PMD but poorer spectral efficiency
(b)
lase
rla
ser
lase
rla
ser
lase
rla
ser
lase
rla
ser
lase
rla
ser
100G parallel transport (OTN VCAT)
Pros and Cons of Serial vs. Parallel 100 G
June 18, 2008
Universal 100 G ~10 G transmitter with built-in dispersion equalization
At a glance, this isuseful for parallel 40G/100G Trx/Rcv with independent ASK, PSK, DPSK, QPSK, DQPSK, etc.
AM PM
AM PM
AM PM
DEM
UX M
UX
June 18, 2008
-300 -200 -100 0 100 200 300-60
-40
-20
0
Frequency (GHz)
Inte
nsity
(dB
)
-300 -200 -100 0 100 200 3000
0.5
1
Time (ps)
Inte
nsity
(au)
-300 -200 -100 0 100 200 300Time (ps)
Pha
se (1
rad/
div)
Pre-chirping 100 Gb/s OOK signal for 1000 km transmission
June 18, 2008
-300 -200 -100 0 100 200 3000
0.5
1
Time (ps)
Inte
nsity
(au)
-300 -200 -100 0 100 200 3000
0.5
1
Time (ps)
Inte
nsity
(au)
-300 -200 -100 0 100 200 300Time (ps)
Pha
se (1
rad/
div)
Real
Imag
Real
Imag
OOK constellation at transmitter OOK constellation at receiver
Prechirped 100 Gb/s OOK signal at receiver after 1000 km transmission (simulated)
June 18, 2008
Peebles Africa• Fixed or mobile platform wireless mesh networking• Rapidly reconfigurable and self-forming cognitive networking• Low-cost, high-performance delivery of:
• ~54 Mb/s for current 802.11 technology (~200 km)• ~ 1 Gb/s Ethernet for current GigE (10 km=> 200 km)• ~ 10 Gb/s Ethernet for optical wireless (~100km)• ~ 1 Tb/s (100 x 10 Gb/s) for WDM optical wireless (~100km)
Wireless Mesh Telemedicine and Emergency Response
June 18, 2008
Wireless Mesh Networks
Multipath wireless meshwith Network Coding
Hierarchical wireless meshnetworking
Example: On-Demand Ambulance NetworkingCognitive Ad Hoc Wireless Mesh Networking with Mobility