Innovation Center UFRGS/Microsoft Virtualization Instruction Set Architecture.

Innovation Center UFRGS/Microsoft

Virtualization Instruction Set Architecture


Development Team


Development Team

Researcher:

Manuela Klanovicz Ferreira

Advisor:

Henrique Cota de Freitas


Motivation


Motivation

VM1 VM2 VM3 VM4

Virtualization provide the isolation of multiple OSs stacks in their own Virtual Machines, so there are no data or instruction dependences

Virtualization provide the isolation of multiple OSs stacks in their own Virtual Machines, so there are no data or instruction dependences

Multi-core architecture can run each guest OSs really in parallel

Multi-core architecture can run each guest OSs really in parallel


GOAL


GOALThe goal of this work is develop an instruction set that offer support for virtualization in a multi-core environment.

The goal of this work is develop an instruction set that offer support for virtualization in a multi-core environment.

Visa Visa

Visa Visa

Visa Visa

Visa

Visa

Visa

Visa

First we have to run a workload in a multi-core model and analyse the operations that have to be improved. Each core uses virtualization technology present in single modern processors.

First we have to run a workload in a multi-core model and analyse the operations that have to be improved. Each core uses virtualization technology present in single modern processors.


Intel VT

Intel VT is the Intel Virtualization Technology that provides hardware virtualization support in order to simplify the Virtual Machine Monitors (VMMs) and to increase the performance of virtualized systems

Intel VT is the Intel Virtualization Technology that provides hardware virtualization support in order to simplify the Virtual Machine Monitors (VMMs) and to increase the performance of virtualized systems

Intel Virtualization Technology (VT) was chosen to be improved to multi-core systems because it has good documentation

Intel Virtualization Technology (VT) was chosen to be improved to multi-core systems because it has good documentation


Intel VT: InstructionsThe operation instructions have the goal of simplify the context switchig between the Virtual Machines (Vms) and the Virtual Machine Monitor (VMM).

The operation instructions have the goal of simplify the context switchig between the Virtual Machines (Vms) and the Virtual Machine Monitor (VMM).

NormalOperation

VMX root(VMM)

VMX non-root

(VM)

VMX active

VMXON: enable VMX instructions VMLAUNCH: launch a new virtual machine (VM) VMCALL: switch the context to virtual machine monitor (VMM)

VMXOFF: disable the VMX instructions

VMRESUME: resume the VM execution


Intel VT: Structures

References the active VMCS, the VMCS that is running on CPU

References the active VMCS, the VMCS that is running on CPU

VMCS 1

VMCS 2

VMCS 3

VMM

root ON

Active

VM

CS

Opera

tion

Mod

e

V

MX O

pera

tions

CPU

On CPU

VM

CS of V

MM

registers

Stores the operation mode: root or non-root

Stores the operation mode: root or non-root

Shows if the VMX operation were ON or OFF

Shows if the VMX operation were ON or OFF

References VMCS of Virtual Machine Monitor (VMM)

References VMCS of Virtual Machine Monitor (VMM)Each launched

VM has a VMCS to save its context, but only one will be the active VMCS of the physical processor

Each launched VM has a VMCS to save its context, but only one will be the active VMCS of the physical processor


ArchC

ArchC is an ADL that can automatically generate simulators using the hardware description language SystemC

ArchC is an ADL that can automatically generate simulators using the hardware description language SystemC


Using ArchC

Model ProcessorDescription

ArchCFramework

ModelAssembler

ModelSimulator

Intel VT instructions Intel VT structures

We modeled Intel VT instructions and structures and use the ArchC framework to generate the model assembler and simulator

We modeled Intel VT instructions and structures and use the ArchC framework to generate the model assembler and simulator


Testing


Source of Assembly Test

Design and Wrote the source of assembly test

Design and Wrote the source of assembly test

VMM

VM1

VM2

VM1

VM LAUN C H

VM LAUN C H

VM C ALL

VM C ALL

VM C ALLVM R ESU M E


Compiling and Running the Test

Model ProcessorDescription

ArchCFramework

ModelAssembler

ModelSimulator

SourceAssembly Test

Binary

Statistics

Using the model assembler and model simulator we can generate statistics of test execution

Using the model assembler and model simulator we can generate statistics of test execution


Test Results

It is possible to check that with VMX instruction, the test has fewer executed instructions. In this case, the context switching is done through only one instruction

It is possible to check that with VMX instruction, the test has fewer executed instructions. In this case, the context switching is done through only one instruction

The trace shows step-by-step each instruction execution. It is possible to add new traces in this model that show what a student needs for a specific work

The trace shows step-by-step each instruction execution. It is possible to add new traces in this model that show what a student needs for a specific work


Events Participations

May of 2007 – ISCAS (International Symposium on Circuits and Systems)

October of 2007 – SBAC-PAD e WSCAD 2007

March of 2008 – ERAD 2008 in Sta Cruz do Sul

June of 2008 – ISCA e WCAE (Workshop on Computer Architecture Education) in Beijing, China

July of 2008 - CSE 2008 in São Paulo

Events Participations

Use this model to simulate and understand virtualization are two contributions of VISA.

Use this model to simulate and understand virtualization are two contributions of VISA.


Virtualization Instruction Set Architecture

.

http://www.codeplex.com/visa

Innovation Center UFRGS/Microsoft Virtualization Instruction Set Architecture.

Documents

virtualization instruction

multicore model

intel vtintel vt

vmx instructions vmlaunch

vmx instructions vmresume

model assembler

vm executionintel vt

new virtual machine