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University: Microfilms
International 300 N.Zeeb Road Ann Arbor, Ml 48106
MORREALE, JAY PHILIP
A GENERAL PURPOSE GRAPHICS PROCESSOR
THE UNIVERSITY OF ARIZONA
University Microfilms
International 300 N. Zeeb Road, Ann Arbor. MI 48106
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University Microfilms
International
A GENERAL PURPOSE GRAPHICS PROCESSOR
by
Jay Philip Horreale
A Thesis Submitted to the Faculty of the
DEPARTMENT OF ELECTRICAL ENGINEERING
In partial Fulfillment of the Requirements For the degree of
MASTERS OF SCIENCE
In the Graduate College
THE UNIVERSITY OF ARIZONA
19 8 4
STATEMENT BY AUTHOR
This thesis has been submitted in partial fulfillment of requirements for an advanced degree at the University of Arizona and is deposited in the University Library to be available to borrowers under rules of the Library.
Brief quotations from this thesis are allowable without special permission, provided that accurate acknowledgement of the source is made. Requests for permission for extended quotations from of reproductions of this manuscript in whole or part may be granted by the head of the major department or the Dean of the Graduate College when in his judgement the proposed use of the material is in the interest of
scholarship. In all other instances, however, permission must be obtained from the author.
SIGNED
APPROVAL BY THESIS DIRECTOR
This thesis has been approved on the date shown below:
L.P. Huelsman Professor of Engineering
Da te
ACKNOWLEGMENTS
I would like to thank several people for their help
on this project. First, to Robert W. Freund for his help in
trouble shooting the proto-type boards. Second, to Tom
Meersman for drawing the figures and illustration in this
document. Third, to Dr. Huelsman for his continued support
throughout this project. Last, to my parents Phil and
Seventh, data within the selected RAM becomes stable on the
s lave processor data bus AD7-AD0, Eighth, S MRD* returns high
a t the rising edge of the n e xt clock cycle causing the data
to be latched i nto the slave processor. Last, the a ddress
lines become unstable in the middle o f the next clock cycle
( T 4) and chip select and D T/R* go high ending the read
memory operation.
52
Slave Memory Write
T h e slave processor may also write a byte to R A M.
This write operation is similar to a bove read operation
except for the following differences. First, after the
valid address has been latched and the particular RAM chip
has been selected, the data to b e written becomes s table on
the slave processor data bus. The 74LS245 tristate
transceiver ( U 29) is directed by DT/R-v t o a l low data to p ass
from the s lave processor to the R AM chip. Second, at the
falling edge of clock cycle T 4 data is latched into the
selected RAM chip. Last, the address becomes unstable in the
m iddle of clock cycle T 4 and chip select returns high ending
the write memory operation.
Host Processor RAM Interface
T he host processor may read and write to the s lave
processor R AM by f i rst writing a 40H and then a 41H to t he
c ontrol port. T he control byte 40H causes the slave
processor to s t op execution a t the end o f the current
instruction. T he second control byte disables the slave
processor address, data, and chip select from this shared
R A M. This two step process is used t o allow the slave
processor' t ime to finish the current instruction before the
h ost takes c ontrol of the RAM space. The control byte 4 1H,
53
more specifically causes bit zero to g o high ( see figure
1 8). It is G E N* in the h igh state that d isables the slave
processor from the R AM. GEN» is inverted to c reate host
enable, HOSTEN, which enables several tristate buffers.
These buffers allow the transfer of data between the host
processor and the RAMS, and the buffers connect the host
processor address lines to the RAMS.
Host Memory Read
Once the host processor has acquired a ccess to the
s lave processor R AM, the host may read data from the RAM by
e xecuting a memory read instruction which causes the
f ollowing events to o ccur ( see figure 1 9). First, at the
rising edge of first ( h ost) clock cycle ( BS1), PSYNC goes
high, and the address and status lines become stable, SMEMR
especially. T he address from the S-100 bus, A10-A0, are
presented to t he R AMS through two 7 4LS244 tristate buffers
V3 and V4. Address lines All and A 12 select a RAM chip to
r ead f rom by a 74LS138 one of four decoder ( V 5). One of the
f our outputs from the 74LS138 will go low depending on the
s tate of All and A 1 2 (see table 9 ) .
DRA
-m—-> «•*
•M
V4 (t/«l
•Wt
HAI> VIO
'liaa •n
OND
HAII HAII •QW IOA*
V*
IIOI
(l/tl
AJO
AO
HM
2 :— Figure 1 8. Host Memory Interface.
DRAV/ING NO REVISIONS RCV APPVD ZONE DESCRIPTION OCH
PI*
W
•AO
HAO
017
007
Odo
DESCRIPTION PART NUMBER
OWN
J/.\ ^RESEARCH
TITLE FIGURE 18, HOST MEMORY INTERFACE AC YD
TtEV DRAWINO NUMBER
iS«Tfi INITIAL USE «HT 4 OF <)
Host Memory Interface
HOST CLK
PSYNC
ADDRESS STATUS
SMEMR
PDBIN
DATA IN BUS
BSI I BS2 I BS3
j~
r VALID ADDRESS AND STATUS dct
J VALI6 V. A DATA r
DATA OUT BUS
MWRT*
RAMSEL
HMRD*
HMWT*
CHIP SELECTS
VALID DATA x
RAM DATA OUT
RAM DATA IN
VALID DATA x
CVALID V DATA r
Figure 1 9 . Host RAM Timing Diagram.
56
Table 9 . Host address selection
A 12 All ADDRESS CHIP SELECTED
0 0 1 1
0 1 0 1
0000-07FFH 0800-OFFFH 1000-17FFH 1800-1FFFH
U 1 2 U13 U14 U15
The remaining address lines A15-A13 from the S -100 bus
s elect the 8K boundary here the host c an access the s lave
processor R A M. Three exclusive OR gates ( 74LS136, V10)
compare the address lines A15-A13 with three switches ( see
table 1 0). When the switch settings and the a ddress lines
a re equal none of the 74LS136 XOR outputs g o low causing
RAMSEL to b e high. RAMSEL, thus, allows the read operation
to o ccur by e nabling the 74LS138 one o f four decoder ( V 5).
Table 10. Host-slave address selection
ADDRESS LINES SWITCHES START ADDRESS
A15 A 14 A13 SI S 2 S3 0 0 0 OFF OFF OFF 0 0 1 OFF OFF ON 0 1 0 OFF ON OFF 0 1 1 OFF ON ON 1 0 0 ON OFF OFF 1 0 1 ON OFF ON 1 1 0 ON ON OFF 1 1 1 ON ON ON
( H E X) 0000 2000 4000 6000 8000 A000 C000 E000
Second, PDBIN g oes high before the next clock cycle ( B S2)
and P SYNC returns low. RAMSEL, PSYNC, and SMEMR are ANDed
and inverted together to c reate host memory read, HMRD*.
57
HMRD* goes low on the rising edge of PDBIN and causes the
74LS244 tristate buffer V2 to become active on the S-100
input data bus DI7-DI0. The selected RAM also responds at
this time by putting data onto the bus. Third, some time
around the next clock cycle (BS3), PDBIN returns low causing
HMRD* to go high and latch the data into the host processor.
The 74LS244 tristate latch (V2) also tristates at this time.
Last, before the end of the next clock cycle (BS3), the
address and status lines become unstable. RAMSEL and SMEM
become inactive ending the host read.memory operation.
Host Memory Write
The host processor may also write to the slave
processor RAM. This write operation is the same as the read
operation except for the following differences. First, only
RAMSEL goes high after the address lines become stable.
SMEMR and PDBIN, in particular remain low. Second, MWRT goes
high at the beginning of clock cycle BS2 (see figure 19).
MWRT is then inverted to create HMWT* which goes low. A
74LS244 tristate buffer (VI) is enabled allowing data to
pass from the host processor to the RAMS. Third, MWRT»"f
r eturns low causing HMWT* to go high and latch the data into
the selected RAM. Last, at the end of clock cycle BS3, the
address, data, and status become unstable. RAMSEL, chip
select, and the tristate buffer, in turn, become inactive
58
ending the write memory operation.
NQN-S-100 Bus Characteristics
The S-100 bus standard (IEEE-696) states that no bus
line will drive more than one low power Schottky inputs per
board. The host processor RAM interface describe above,
however, puts a double input load on both the address lines
and the data input and output bus. This interface,
therefore, does not meet the standard. The omission of the
extra buffers greatly simplified the construction of the
prototype. The host-RAM interface is only for software
development and is not considered a normal function of the
slave processor.
CHAPTER THREE
SOFTWARE
Forth was first written by Charles Moore in 1969 at the
National Radio Astronomy Observatory in Charlottesville
Virginia for telescope control and astronomical data
reduction. In 1973, Charles Moore left NRAO to form his own
company - Forth Inc - which would sell an enhanced
commercial version of Forth for mimicomputers. Then in 1978
a group of Forth programmers (enthusiasts) formed the Forth
Interest Group (FIG) to promote the language Forth. FIG
began writing Forth for various microcomputers and a journal
called Forth Dimensions[6]. The August 1980 issue of Byte
magazine, the Forth issue, brought my attention to Forth and
to FIG[7]. Intrigued by the language, a copy of the Forth
implementation manual and an 8080 listing was ordered.
During the next summer, a month or so was spent implementing
Forth on a Z80 processor system. Once the FIG Forth became
operational, a new Forth enthusiast was created (like CREATE
JAY). Forth is not like basic, Pascal, Fortran nor is it
like assembly language. Forth is more of a cross between a
high and low level language. Forth is better described as
59
60
an interactive interpretive compiler because all compiled
high level words are lists of address pointing to other high
level words which, in turn, ultimately point to low level
assembly language Forth words. Forth, also, allows the
creation of assembly language words at any time for time
critical portions of applications. Forth, therefore, is
faster than basic and more compact than either Pascal or
Fortran compiled programs[8].
Forth was, then, chosen for this project for several
reasons. First, Dr. Dobb's Journal published an 8088 Forth
assembler by Ray Duncan[9]. Second, FIG provided (at
nominal cost) an 8088 Forth source listing which was written
by Thomas Newman[10][11]. This 8088 Forth, in particular,
executes the same high level Forth words as the 8080 Forth
which was currently running on my host system. Third, FIG
also provided a 8080 META-COMPILER written by John Cassady
for implementing a new version of Forth which will not run
on the host system but on a target system[12][13][14][15].
Fourth, the 8088 processor was acquired free of charge
through an INTEL promotion and this processor, more
importantly, was relatively easy to interface to the current
system. Fifth, Forth is very interactive and allows the
programmer complete control to define new high or low level
words and data structures. The programmer, more
specifically, has enough control to define experimental
61
image 'processing' languages and applications in an
interactive manner. Sixth, high level Forth words developed
on the host processor will also compile and run on the slave
processor with (ideally) no modifications. Last, with the
availabilivity of the 8088 Forth, assembler, and
META-Compi1er example at little cost, an 8088 Forth could be
written on a Z80 host microcomputer system. The 8088 Forth,
thus, can be compiled by the host, and transfered to the
8088 slave processor for testing and debugging without
spending hundreds of dollars on assemblers, operating
systems, cross-compilers, and many hours writing a dedicated
assembly language graphics software package.
Host Memory Configuration
The host can be considered somewhat unusual. First,
the North Star Disk Operating System (DOS) begins at memory
addres 2000H - the beginnig of the second 8K byte block of
memory (see figure 20). The DOS is only 2.5K bytes long and
is a very simple operating system. Second, user programs
like BASIC, the editor, the assembler, and of course Forth
must begin at memory address 2A00H. The basic 8080 Forth
kernal, in particular, is approximately 8K bytes long but
requires RAM for disk buffers add for several stacks. Forth,
thus, can be considered to reside from memory address 2A00H
to AFFFH. Third, there is no RAM at address B000H to BFFFH,
62
EOOOH
COOOK
AOOOH
8000H
6000H
4000H
2000H
USER RAM
zrzzzYzrz?. DISK I/O
OOOOH
(GP)
ADDRESS
SRACE
STACK
DISK BUFFERS
BO 80
FORTH
USER
AREA
8060 FORTH
KERNAL
—4 — DOS
6068
FORTH
DEVELOPMENT
AREA
Figure 20. Host Memory Map.
63
EOOOH to E6FFH, and EAOO to EFFFH. Fourth, vhen the host
processor has access to the slave processor RAM space, this
RAM resides at memory address COOOH to DFFFH (of the host).
Vhen the slave processor, in contrast, is given control of
the shared RAM, the above host address space from COOOH to
DFFFH contains no RAM. Fifth, a two hundred and fifty six
byte disk boot* PROM and memory mapped disk 1/0 begins at
memory address E900H. Seventh, the 4K bytes of RAM beginning
at F000H is used for the system monitor and various
utilities. Last, the 8K bytes of RAM residing at 0000H is
used to develop the 8088 Forth.
A Forth Application
During the course of prototyping the slave processor
it was necessary to determine if the I/O ports and memory
were functioning as expected. Some high level Forth words,
for instance, were written to read the status ports, to
write bytes to the command port, to reset the slave
processor and to write into the slave processor RAM (see
screen 88). several 8088 assembly language programs were
also written to test the 8088 processor, RAM, and the I/O
ports (see screen 89 and 90). To illustrate how Forth
works, then, consider some Forth words in screen 88. First,
BASE and HT.ADDR are constants which designate the base
address of the I/O ports of the slave processor and the base
Listing 1. Forth test screens
SCR 4 B6 0 ( GRAPHICS TEST ) 1 HEX 30 CONSTANT BASE COOO CONSTANT HT.ADDR 2 BASE 0 -I- CONSTANT PORTO BASE 1 + CONSTANT PORTl 3 HT.ADDR 6 + CONSTANT IP HT.ADDR A + CONSTANT CS 4 10 CONSTANT SL.ADDRO 00 CONSTANT SL.ADDR1 5 6 i 7OR BEGIN PORTl P@ 1 AND 7TERH1NAL OR UNTIL } 7 t 7IR BEGIN PORTl P@ 2 AND 7TERMINAL OR UNTIL j 8 9 : RESET 80 PORTl P! ; 10 i HALT 40 PORTl PI } : HOST HALT 41 PORTl P! ; 11 t READ 70R PORTO P@ ; t WRITE 7IR PORTO PI ; 12 13 t SET.NMI SL.ADDRO IP I SL.ADDR1 CS 1 ; 14 i GLOAD HOST HT.ADDR SL.ADDRO + SWAP CMOVE SET.NMI ; 15 ;S
SCR # 89 0 ( GRAPHICS PROCESSOR TEST - JPM 12 AUG 82 ) 1 CODE GTEST HERE 2 BEGIN 3 AL, 01 IN 4 AL, 4 1 TEST 5 0<> UNTIL 6 AL, 0 IN 7 AH, AL HOV 8 BEGIN 9 AL, 01 IN
10 AL, 4 2 TEST 11 0<> UNTIL 12 AL, AH HOV 13 0 , AL OUT 14 JMP 15 NXT (S
SCR 4 90 0 ( 8088 TEST PROGRAM 2 - 5 AUGUST 82 ) 1 CODE MGET 2 AX, 30 HOV 3 40 , AX MOV 4 HERE 5 JMP 6 NXT 7 8 9
10 11 12 13 14 15 ;S
65
address of the beginning of the shared RAM as seen by the
host processor, respectively. Constants PORTO and P0RT1
represent the port address of the command/response and
status/control ports of the slave processor and place 30H or
31H on the stack when executed, respectively. Third,
constants IP, and CS locate the address as seen by the host
processor 'of the Instruction pointer and Code segment
interrupt vectors so that these vectors can be set before
the slave processor receives a Non-maskable interrupt by the
word RESET. When the NMI occurs the values at address IP
and CS point to the start of the program. Fourth, SL.ADDRO
and SL.ADDR1 are, also, constants which are placed at
address IP and CS and place values 10H and 00H on the stack
when executed. Fifth, 70R (output ready) and 7IR (input
ready) are colon definitions. Colon definitions, more
specifically, define run time action words. Once a colon
definition, a Word, has been defined, it can be executed
from the keyboard or from within another Word. ?0R, for
example, sits in a loop via a BEGIN-UNTIL loop structure
I w aiting for bit one of the status port to be non-zero or
until a key is pressed oil t he keyboard or both. ?IR, in
contrast, has the same BEGIN-UNTIL loop structure but waits
for status port bit one to be one. These two words, thus,
make the host processor .wait until the command and response
ports are ready to write and read bytes. Sixth, reset,
66
halt, read, and write are also colon definitions which do
what the word implies to the slave processor. HOST, more
uniquely, halts the slave processor and gives the slave
processor access to the shared RAM. Seventh, SET.NMI sets
the address were the slave processor will begin execution
after a non-maskable interrupt (NMI). The phrase 'SL.ADDRO
IP for example, will place the value of SL.ADDRO (10H)
at host address IP (C008H) using ! (store). Eighth, when
GLOAD is executed with the proper address and lenght on the
stack, a previously assembled 8088 program can be moved from
the dictionary (in the host address space) to the slave
processor RAM space. GLOAD also uses the words described
above to set the execution address of the 8088 program just
loaded. Last, once the 8088 program is loaded (see screen
89) reset is executed which will cause the slave processor
to gain control of the RAM and to execute the newly loaded
program. Colon definitions READ and WRITE provide a means of
checking the execution program within the slave processor
board. When 01 WRITE is executed from the keyboard, WRITE
take a sixteen bit value off the stack, 01 in this case,
waits for the status to be ready, and writes the low byte to
the command port. Once the byte 01 progates through the
FIFO registers the slave processor will test the FIFO status
and read in the byte. The slave will test the status again,
wait until it is ready and write the same byte back out to
67
the response port. READ, then, will wait for the status on
the host side to be read and read the byte from the reponse
port. Two programs, therefore, are running concurrently.
READ and WRITE run on the host side and GTEST runs on the
slave side (see the flow cart in figure 21).
A Colon Definition
A Forth colon definition provides the programmer a
means of creating new words such as the words described
above. The Forth interpreter compiles these words into a
dictionary as a linked list of address. To understand this
process more clearly, consider ?0R described above in more
detail. First, tell Forth to defer execution unless
otherwise specified and to create a header in the dictionary
for ?0R (see figure 22). This header consists of a name
field (NFA), a link field (LFA) , and a code field (CFA). The
name field, for example, contains a length byte and the name
of the word (up to thirty-one characters). The link field
points to the name field of the previous word. This link
field provides a means of linking words together for
dictionary searches during word compilation. The code
field, on the other hand, contains an address which points
to the run time portion of 1s* called DOCOLON. Second, the
Forth interpreter searches the dictionary using the link
field address pointers for BEGIN. Since BEGIN has been
POINTER TO NFA OF SL ADDR I POINTER TO DOCOLON POINTER TO PORT I POINTER TO P2 POINTER TO 2 POINTER TO AND POINTER TO ? TERMINAL POINTER TO OR POINTER TO 0BRANCH.
POINTER TO ;5
Figure 22. Memory Map of a Colon Definition.
70
defined before ?0R the search procedure succeeds. The code
field address of BEGIN, however, is not compiled into the
dictionary as is the usual case because BEGIN belongs to a
special class of Forth words. These words have precedence
which cause them to execute immediately. BEGIN and all words
in the same class have a precedence bit set which is within
the length byte within the name field. When BEGIN executes
it puts the address of the next available dictionary
location on the stack and an error handling byte. Third, the
Forth interpreter again searches the dictionary for P0RT1
and will find it. The interpreter then writes a two byte
address, the code field address, of P0RT1 into the next
available dictionary locations. Fourth, the CFA of 2 is
compiled into the next available dictionary locations just
after the CFA of P0RT1. 12 *, however, has been defined as
constant which speeds up compilation and saves dictionary
space especially for frequently used numbers. All words, in
particular, that are compiled into the dictionary for a new
word must already exist in the dictionary so that the
interpreter can find them. Forward word references, thus,
are not possible (but recurrsion is with special
techniques'). Fifth, the code field addresses of P@ (port
fetch), AND, 7TERMINAL, and OR are, likewise, compiled into
the dictionary. Sixth, UNTIL also has precedence and
executes immediately. UNTIL, for instance, removes the error
71
byte from stack and compiles OBRANCH into the dictionary
along with the address left on the stack by BEGIN. OBRANCH
and this address will cause the inner interpreter to branch
back to the first word within 70R (P@) for as long as the
value on the stack, the status of the FIFO register, is zero
when the word is executed. Last, again, has precedence
and executes immediately by checking for any leftover error
flags and compiles the CFA of ;S into the dictonary. ;S is
like a 'return' from subroutine in other languages because
it causes the inner interpreter to clean up the return stack
and to execute the next word. also ends compilation
mode.
Once defined ?0R can be executed from the keyboard by
typing it or by including it within another colon
definition. When 20R is executed from the keyboard, however,
the Forth interpreter searches the dictionary for ?0R. Once
70R has been found the interpreter executes the code pointed
to by the code field address of ?0R. In this case, the CFA
of ?0R contains a pointer to DOCOLON. When DOCOLON is
executed by the interpreter, the return stack and the Forth
instruction (word) pointer are set so the interpreter will
remember what word to execute next. DOCOLON i s , in effect,
functioning as an assembly language call instruction without
actually executing a call instruction. The word P0RT1, for
example, is 'called' first. P0RT1 executes by 'calling' the
72
run time portion of DOES> which is part of the definition of
a constant. Once P0RT1 has finished execution P<3 w ill
execute by 'calling' words within P@. (P@ is a low level
assembly language word.) Each word, in general, 'called'
contains other words which 'call' other words which...so on
and so forth until machine language primitives are
ultimately executed. When all words 'called* have completed
execution, the interpreter will then look at the keyboard
for more instructions.
In conclusion, Forth has some very unique features.
First, all Forth words are linked lists of address or linked
groups of machine code, and are part of a dictionary.
Second, all Forth words interact with each other through a
parameter stack. The return stack is usually used to keep
account of where to come back to. Third, Forth has three
modes of operation like 'run time', 'compile time', and
'definition time' (not discussed above). Fourth, once Forth
words are defined, they do not search the dictionary to
execute. Last, all words, once defined, can be tested and
debugged interactively[16][17][18] .
A Code Definition
A code definition is a Forth word which contains
machine language code as part of the word and is linked into
the dictionary in a way similar to a colon definition
73
described above. To illustrate how a code definition is
constructed, consider the word GTEST in screen 89. First,
CODE invokes the assembler and creates a header in the
dictionary. This header contains a name field, a link field,
and a code field just like the colon definition. The name
field, in contrast, contains a different length byte and
characters 'GTEST', and the code field address points to the
start of the machine code in the next successive dictionary
locations (see figure 23). Second, HERE executes
immediately by leaving the address of the next available
dictionary location on the stack which turns out to be the
start of the machine language code. Third, BEGIN also
executes immediately and leaves the same address on the
stack. Fourth, the next instruction, 'AL, 01 IN* is written
in Forth assembly language mnemonics. 'AL,', for instance,
sets several assembler variables to designate that the AL
8088 register is the destination. *01', on the other hand,
is a number which is placed on the stack. 'IN', then, comes
and looks at the assembler variables and takes 01 off the
stack to build the actual machine language code into the
dictionary, E4 01. Fifth, the words 'AL # 1 TEST' execute
ultimately creating F6 CO 01 (HEX) in the dictionary. 'AL,',
as before, sets the AL register as the destination but '#'
designates that TEST should be an immediate instrution where
'1' is the value to be used. Sixth, 0<> UNTIL places a 74H
74
NFA
LFA
CPA
PFA
85 GTEST
E4 01
F6 CO 01
74 F9
E4 00
E4 EO
E4 01
F6 CO 02
74 F9
BA CA
E6 00
E7 E9
73 POINTER TO 6L0AD
POINTER TO PFA
AL, 01 IN
AL,# 01 TEST
-7 JUMP
AL, 00 IN
AH, AL MOVE
AL, 01 IN
AL,#02 TEST
-7 JUMP
At- AH MOV
00, AL OUT
- 24 JUMP POINTER TO NEXT
Figure 23. Memory Map of a Code Definition.
75
into the dictionary along with the address on the stack that
was put there by BEGIN. The resulting instruction placed in
the dictionary is a jump relative if zero. Seventh, in a
similar manner, Forth words 'AL, 00 IN' puts bytes E4 00
into the dictionary. Eighth, 'AH, AL MOV 1 causes 8A E0 to be
placed in the dictionary next. 1AL 1 specifies the AL
register as the source, where as 'AH* defines the
destination of the move instruction. Ninth, BEGIN leaves the
address of the next dictionary location on the stack. Tenth,
forth words 'AL, 01 IN', 'AL, # 2 TEST*, and 0<> UNTIL cause
E4 01 F6 CO 02 74 F9 to be put into the dictionary by a
similar procedure used in the above instructions. Eleventh,
'AL, AH MOV',\'00 , AL OUT', and JMP are the last to execute
and place bytes 8A C4 E6 00 E9 E7 into the dictionary. The
OUT instruction is somewhat unique in that the comma sets 00
as the destination (port) and register AL as the source. The
jump instruction, on the other hand, gets its operand from
the stack which was originally placed on the stack by the
word HERE. Last, NEXT ends the code definition by placing a
jump to the inner interpreter and checks for errors
[15] [16][17][18] .
76
APPENDIX A
8088 FORTH ASSEMBLER
The 8088 Forth Assembler in listing 2 appeared in
the February 1982 issue of Dr. Dobb's Journal and was
written by Ray Duncan[8]. This assembler, however, has been
modified slightly to facilitate the compilation of the 8088
Forth. A more extended IF-ELSE-THEN, more specifically,
structure was added to the assembler. Readers will notices
from the previous example that all assembly language
instrustions are backwards. The instructions, in general,
take the form DESTINATION, SOURCE OP-CODE. The operands,
then, place values onto the stack or manipulate assembler
variables. When the op-code executes, it uses the variables
and the values on the stack to create the desired machine
language code. In addition, the 8087 instruction set has
SCR # 120 0 ( 8088 ASSEMBLER - DDJ FEB 82 1 I IF 0 C, HERE RESET ; 2 t ELSE EB C, 0 C, DOP 3 0 C, HERE SWAP - DUP ABS 4 SWAP 1 - CI HERE RESET t 5 : ENDIF DUP HERE SWAP - DUP ABS 6 SWAP 1 - C! RESET | 7 8 t BEGIN HERE RESET ; 9 i UNTIL HERE 1+ -10 DUP ABS 7F > 23 7ERROR C 11 12 13 14 15 -->
DDJ FEB 82 )
> 23 ?ERROR
Listing 2. 8088 Forth Assembler
SCR # 121 0 ( 8088 ASSEMBLER - DDJ FEB 82 1 : BYTE 0 <W> I 0 <WD> 1 J 2 t WORD 1 <W> t 1 <Vn» I ; 3 t # 1 <#> I 1 <TS> 1 ; 4 5 i DB C, J 6 i DM 7 8 t DEPTH SO <? SP@ - 2 - 2 / } 9 i , DEPTH 1 < 2E 7ERROR 0 <TD> 1 f 10 11 12 13 14 15 -->
SCR # 122 0 ( 8068 ASSEMBLER EXTENTION - 29 OCT 83 JPM 1 ( CHDITIOHALS FOR IF [TRDE] ELSE [FALSE] ENDIF 2 ( SIGHED 3 t 0- 75 ( JNE.JNZ ) c, ( EQ ) 4 i 0<> 74 ( JZ,JE ) c, < NE ) 5 t > 7E < JliE|JNG ) C, ( GT ) 6 t < 7D ( JGE,JNL ) C, ( I»T ) 7 : -> 7C { JL.JNGE ) c, ; < GE ) 8 i <- 7F { JG,JNLE ) C, ; ( LE ) 9 ( UNSIGNED 10 i 0> 76 ( JBE,JNA ) c, ( GT ) 11 i 0< 73 { JAE,JNB ) c, < LT > 12 i 0-> 72 ( JB,JNAE ) c, ( GE ) 13 t 0<- 77 < JA.JNBE ) c, ( LE ) 14
SCR # 123 0 ( 8088 ASSEMBLER - EXTENSIONS 1 t NOV ( JNO ) 71 C, ; 2 : OV < JO > 70 C, ; 3 > PO ( JNP,JPO ) 7B C, ; 4 i PE ( JPE.JP ) 7A C, | 5 i NSS ( JNS ) 79 C, i 6 j SS ( JS ) 78 Cf ; 7 > 00 ( JMP ) EB C, | 8 9 ( SEGMENT RESITER OVER RIDES - 17 FEB 84 ) 10 26 1MI ESOV 11 2E 1MI CSOV 12 36 1MI SSOV 13 3E 1MI DSOV 14 15 -->
SCR # 100 0 ( 8088 1 FORTH - START 1 LABEL ORG KOP HERE JHP 2 NOP HERE JMP 3 0000 DU 4 0000 DU 5 0000 DU 6 0008 DU 7 EM CO - US - DU 8 EM CO - US - RTS - DU 9 EM CO - us - DU 10 EH CO - us - RTS - DU 11 0020 DU 12 0000 DU 13 0000 DU 14 0000 DU 15 0000 DU
SCR # 101 0 ( 8088 FORTH - USEP, RETP 1 2 LABEL UP EM CO - US - DW 3 LABEL RSP EM CO - US - DU 4 5 6 7 8 9 10 11 12 13 14 15 -->
SCR # 128 0 ( 6088 FORTH - CI 1 CODE Ct BX • POP 2 AX POP 3 [BX], AL MOV 4 NEXT JMP 5 NXT 6 7 CODE 2! BX POP 8 AX POP 9 [BX], AX HOV 10 AX POP 11 2 [BX] , AX HOV 12 NEXT JMP 13 NXT 14
SCR # 129 0 ( 8088 FORTH - META1 COMPILER STUFF 1 NF: ; ?CSP COMPILE [FROHtNEWFORTH] ;S 2 SMUDGE [COMPILE] FORTH [COMPILE] [ NF; 3 NFs ENDIF HERE OVER - SWAP I NF; 4 NFi BEGIN HERE NF; 5 NF: DO COMPILE [FROMiNEWFORTH] (DO) HERE NF; 6 NF: LOOP • COMPILE [FROM:NEWFORTH1 (LOOP) HERE - , NF; 7 NF: +LOOP COMPILE [FROMiNEWFORTH] (+LOOP) HERE - , NF 8 NF: UNTIL COMPILE [FROM:NEWFORTH] OBRANCH HERE - , NF; 9 NF: AGAIN COHPILE [FROMiNEWFORTH] BRANCH HERE - , NF; 10 NF: REPEAT SWAP COMPILE [FROHtNEWFORTH] BRANCH HERE -11 HERE OVER - SWAP I NF; 12 NF: IF ~ COMPILE [FROM:NEWFORTH] OBRANCH HERE 0 , NF; 13 NF: ELSE COMPILE [FROHtNEWFORTH] BRANCH HERE 0 , 14 SWAP HERE OVER - SWAP I NF; 15 NF: WHILE COMPILE [FROHtNEWFORTH] OBRANCH HERE 0 , NF
Listing.4. 808B Forth
SCR #130 0 ( 8086 FiORTH - COLON 1 t I GAP GAP GAP ( 7EXEC ICSP CURRENT ) 2 <3 GAP ( CONTEXT ) 1 3 GAP GAP ( CREATE ] ) ;CODE IMMEDIATE 4 DX INC 5 BP DEC 6 BP DEC 7 [BP], SI HOV 8 SI, DX HOV 9 NEXT JHP 10 NXT 11 ' *COLON* I 12 13 « ; GAP GAP ( 7CSP COMPILE ) ;S 14 GAP GAP ( SMUDGE I ) ; IMMEDIATE 15 -->
SCR # 132 0 ( 8088 FORTH - USER 1 t USER CONSTANT (CODE 2 DX INC 3 BX, DX HOV 4 BL, [BX] HOV 5 BH, BH SUB 6 CSOV DI, UP HOV 7 AX, [BX+DI] LEA 8 APUSH JHP 9 NXT 10 * *USER* t 11 0 CONSTANT 0 01 CONSTANT 1 02 CONSTANT 2 12 20 COHSTANT BL 40 CONSTANT C/L 13 ASH88 EH CO - CONSTANT FIRST 14 ASM88 EH CONSTANT LIMIT 15 -->
Libting 4. 8088 Forth
SCR # 133 0 ( 8088 FORTH - USER VARIABLES 1 s +0RIGIN GAP GAP ( LIT 'ORIG* ) + ; 2 06 USER SO 3 08 USER RO 4 OA USER TIB 5 OC USER WIDTH 6 OE USER WARMING 7 10 USER FENCE 8 12 USER DP 9 14 USER VOC-LINK 16 USER BLK 10 18 USER XN 11 1A USER OUT 12 20 USER CONTEXT 13 22 USER CURRENT 14 24 USER STATE 15 —>
SCR # 134 0 < 8088 FORTH • BASE
" 1 26 USER BASE 2 2A USER FLD 3 2E USER R# 4 5 l 1+ 1 + } 6 : HERE DP @ } 7 I , HERE t 2 ALLOT | 8 9 CODE - DX POP 10 AX FOP 11 AX, DX SUB 12 APUSH JHP 13 NXT 14 15 - ->
28 USER DPL 2C USER CSP 30 USER HLD
t 2+ 2 + j 1 ALLOT DP +! ; i C, HERE CI 1 ALLOT
SCR # 135 0 ( 8088 FORTH - < 1 i • • 0" | 2 CODE < DX POP 3 AX POP 4 BX, DX MOV 5 BX, AX XOR 6 SS IF AX, DX SUB ENDIF 7 AX, AX OR 8 AX, t 0 HOV 9 NSS IF AX INC ENDIF 10 APUSH JHP NXT 11 12 t U< 2DUP XOR 0< IF DROP 0< 0- ELSE - 0< ENDIF J
13 : > SWAP < ; 14 15 -->
Listing 4. 8088-Forth
SCR # 136 0 ( 8088 FORTH - ROT 1 CODE ROT DX POP 2 BX POP 3 AX POP 4 BX PUSH 5 DPUSH JMP 6 MXT 7 : SPACE BL EMIT j 8 J -DUP DUP IF DUP ENDIF ; 9 1 TRAVERSE SWAP BEGIN OVER + 7F OVER C@ < mtTIL SWAP DROP 10 I LATEST CURRENT Q @ ; 11 i LFA 4 - ; : CFA 2 - j t NFA 5 - -1 TRAVERSE t 12 : PFA 1 TRAVERSE 5 + ; 13 t 1CSP SPG CSP ! $ 14 I 7ERROR SWAP IF GAP ( ERROR ) ELSE DROP ENDIF ; 15 —>
SCR # 137 0 ( 8088 FORTH - 7C0MP 1 t 7C0MP STATE @ 0- 11 ?ERROR } 2 : 7EXEC STATE @ 12 7ERROR ; 3 t 7PAIRS - 13 7ERROR { 4 : 7 CSP SP@ CSP <3 - 14 7ERROR ; 5 J COMPILE 7C0HP R> DUP 2+ >R 0 , } 6 : [ 0 STATE ! ; IMMEDIATE 7 :] CO STATE 1 j 8 : SMUDGE LATEST 20 TOGGLE ; 9 I HEX 10 BASE ! ; 10 t DECIMAL OA BASE I } 11 i (;CODE) R> LATEST PFA CFA 1 * 12 'NF (;CODE) CFA ' *{}CODE)* 1 13 : {CODE 7CSP COMPILE (;CODE> [COMPILE] [ SMUDGE 14 NOOP ( ASSEMBLER ) ; IMMEDIATE 15 -->
SCR #139 0 ( 8068 FORTH - COUNT ) 1 t COUNT BOP 1+ SWAP C@ ; 2 i TYPE -DUP IF OVER + SWAP DO I C@ EMIT LOOP 3 ELSE DROP ENDIF ; 4 s -TRIALING DUP 0 DO OVER OVER + 1 - C@ BL -5 IF LEAVE ELSE 1 - ENDIF LOOP ; 6 t (.") R COUNT DUP 1+ R> + >R TYPE } 7 *NF (.") CFA ' *(.")* 1 8 t 22 STATE 0 IF COMPILE (.") CAP ( WORD ) HERE C@ 1+ ALLOT 9 ELSE GAP ( WORD ) HERE COUNT TYPE ENDIF ; IMMEDIATE 10 t EXPECT OVER + OVER 11 DO KEY DUP OE +ORIGIN @ -12 IF DROP DUP I - DUP R> 2 - + >R 13 IF GAP GAP ( LIT PNOT ) ELSE GAP GAP ( LIT PBS ) 14 ENDIF ELSE DUP OD - IF LEAVE DROP BL 0 ELSE DUP 15 ENDIF I C! 0 I 1+ 1 ENDIF EMIT LOOP DROP ; —>
SCR # 140 0 < 8088 FORTH - QUERY ) 1 t QUERY TIB @ 50 EXPECT 0 IN I ; 2 i X ( 3 4
. 5 6 CODE FILL AX POP 7 CX POP 8 DI POP 9 BX, DS MOV 10 ES, BX MOV 11 CLD 12 REP AL STOS 13 NEXT JMP 14 NXT
SCR # 145 0 ( 80B8 FORTH - ERASE ) 1 : ERASE 0 FILL ; 2 t BLANKS BL FILL ; 3 i HOLD -1 HLD +1 HLD @ CI j 4 t PAD HERE 44 + ; 5 t WORD TIB @ IK @ + SWAP ENCLOSE HERE 22 BLANKS IN +! 6 OVER - >R R HERE CI + HERE 1+ R> CHOVE J 7 > (NUMBER) BEGIN 1+ DUP >R C@ BASE @ DIGIT 8 WHILE SWAP BASE @ U* DROP ROT BASE Q U* D+ 3 DPL Q 1+ IF 1 DPL +1 ENDIF R>
10 REPEAT R> f 11 : NUMBER 0 0 ROT DUP 1+ C@ 2D - DUP >R + -1
. 12 BEGIN DPL t (NUMBER) DUP C@ BL -13 WHILE DUP C@ 2E - 0 7ERROR 0 14 REPEAT DROP R> IF DMINUS ENDIF j 15 —>
SCR # 146 0 ( 8088 FORTH - -FIND ) 1 t -FIND BL WORD HERE CONTEXT <a @ (FIND) 2 DUP 0- IF DROP HERE LATEST (FIND) ENDIF ; 3 t (ABORT) GAP ( ABORT ) ; 4 : ERROR WARNING @ 0< 5 IF (ABORT) ENDIF HERE COUNT TYPE 7 ,r
6 GAP ( MESSAGE ) SP1 BLK @ -DUP 7 IF IN @ SWAP ENDIF GAP ( QUIT ) } -2 ALLOT 8 t ID. PAD 20 5F FILL DUP PFA LFA OVER -9 PAD SWAP CMOVE PAD COUNT IF AND TYPE SPACE J
10 i CREATE -FIND IF DROP NFA ID. 4 GAP ( MESSAGE ) SPACE ENDIF 11 HERE DUP C@ WIDTH @ GAP ( MIN ) 1+ ALLOT 12 DUP AO TOGGLE HERE 1-80 TOGGLE 13 LATEST , CURRENT 0 1 HERE 2+ , ; 14 15 —>
SCR # 147 0 ( 8088 FORTH - [COMPILE] ) 1 t [COMPILE] -FIND 0- 0 7ERROR DROP CFA , J IMMEDIATE 2 t LITERAL STATE @ IF COMPILE LIT , ENDIF ; IMMEDIATE 3 t DL1TERAL STATE @ IF SWAP [COMPILE] LITERAL 4 [COHPILE] LITERAL ENDIF f IMMEDIATE 5 t 7STACK SP@ SO @ SWAP U< 1 7ERROR SP@ 6 HERE 80 + U< 7 7ERROR ; 7 : INTERPRET BEGIN -FIND IF ( FOUND ) STATE @ < 8 IF CFA , ELSE CFA EXECUTE ENDIF 7STACK 9 ELSE HERE NUMBER DPL Q 1+
10 IF [COMPILE] DLITERAL ELSE DROP [COHPILE] 11 LITERAL ENDIF 7STACK 12 ENDIF AGAIN ; -2 ALLOT 13 14 15 —>
Listing 4. 6088 Forth
SCR # 14B 0 ( 8088 FORTH - IMMEDIATE 1 t IMMEDIATE LATEST 40 TOGGLE ; 2 t VOCABULARY <BUILDS A081 , CURRENT 6 CFA , 3 HERE VOC-LINK 6 , 4 VOC-LINK 1 DOES> 2+ CONTEXT ! ; 5 HERE 8 - DELTA - ' *VOCAB* t 6 VOCABULARY FORTH IMMEDIATE 7 : DEFINITIONS CONTEXT @ CURRENT 1 ; 8 j < 29 WORD ; IMMEDIATE 9 : QUIT 0 BUC I [COMPILE] [ BEGIN RP! CR QUERY INTERPRET
10 STATE @ 0- IF OK" ENDIF AGAIN ; -2 ALLOT 11 12 t ABORT SP! DECIMAL 7STACK CR 13 FIG-FORTH GDC VI.1" [COMPILE] FORTH 14 DEFINITIONS QUIT } -2 ALLOT 15 -->
SCR # 150 0 ( 8088 FORTH • COLD 1 t COLD GAP GAP GAP GAP ( LIT ORIG 12+ LIT UP ) 2 @ 6 + 1 0 C M O V E G A P G A P ( L I T O R I G 0 C + ) @ 3 GAP GAP ( LIT FORTH 6+ ) I ABORT ; -2 ALLOT 4 5 CODE SOD DX POP 6 AX, AX SUB 7 DX, DX OR 8 NSS IF AX DEC ENDIF 9 DPUSH JHP NXT 10 11 12 13 14 15 -->
Listing 8086 Forth
SCR # 0 ( 1 2 3 4 5 6 7 8 9 10 11 12 13 14
151 8088 FORTH - +-+- 0< IF HINUS ENDIF } D+- 0< IF. DHINUS ENDIF ; ABS DUP +- i DABS DDP IH- { HIN 2DUP > IF SWAP ENDIF DROP f MAX 2DUP < IF SWAP ENDIF DROP ; H* 2DUP XOR >R ABS SWAP ABS U* R> D+ M/ OVER >R >R DABS R ABS D/ R> R XOR
SCR # 156 0 < 8088 FORTH - CUSTOM I/O ROUTINES 1 LABEL (7TERMINAL) AL, 01 IN 2 AX, # 01 AND 3 AFUSH JHP 4 5 LABEL (KEY) BEGIN 6 AL, 01 IN 7 AL, # 01 TEST 8 0<> UNTIL 9 AL, 0 IN
10 AH, # 0 HOV 11 APDSH JMP 12 13 14 15 —> •
Listing 4. 6068 Forth
SCR # 157 0 ( 8088 FORTH - CUSTOH I/O ROUTINES 1 LABEL POUT BEGIN 2 AL, 01 IN 3 AL, # 02 TEST 4 0<> UNTIL 5 AL, BL HOV 6 0 , AL OUT 7 RET 8 LABEL (EMIT) 9 AX POP
10 BL, AL HOV 11 POUT CALL 12 CSOV BX, UP HOV 13 1A [BX] INC 14 NEXT JMP 15 —>
SCR # 158 0 ( 8068 FORTH - CUSTOH 1/0 ROUTINES 1 LABEL (CR) BL, # OD MOV 2 POUT CALL 3 BL, # OA HOV 4 POUT CALL 5 NEXT JMP 6 7 8 9 10 11 12 13 14 15 -->
SCR # 166 0 ( 8088 FORTH - BACK 1 t BACK HERE - , j 2 t BEGIN 7COHP HERE 1 ; IHHEDIATE 3 J ENDIF 7C0MP 2 7PAIRS HERE OVER - SWAP t ; IHHEDIATE 4 : THEN [COMPILE] ENDIF ; IHHEDIATE 5 t DO COMPILE (DO) HERE 3 ; IHHEDIATE 6 t LOOP 3 7PAIRS COMPILE (LOOP) BACK J IMMEDIATE 7 I +LOOP 3 7PAIRS COHPILE (+LOOP) BACK | IHHEDIATE 8 ; UNTIL 1 7PAIRS COHPILE OBRANCH BACK ; IMMEDIATE 9 i END [COMPILE] UNTIL j IHHEDIATE
10 i AGAIN 1 7PAIRS COMPILE BRANCH BACK } IMMEDIATE 11 t REPEAT >R >R [COMPILE] AGAIN R> R> 12 2 - [COMPILE] ENDIF J IHHEDIATE 13 t IF COMPILE OBRANCH HERE 0,2; IMMEDIATE 14 15 —>
SCR # 167 0 ( 8088 FORTH - ELSE 1 i ELSE 2 7PAIRS COMPILE BRANCH HERE 0 , 2 SWAP 2 [COHPILE] ENDIF ; IHHEDIATE 3 t WHILE [COHPILE] IF 2+ ; IMMEDIATE 4 t SPACES 0 MAX -DUP IF 0 DO SPACE LOOP ENDIF ; 5 > <# PAD HLD ! ; 6 t #> DROP DROP HLD @ PAD OVER - } 7 t SIGN ROT 0< IF 2D HOLD ENDIF } 8 i # BASE Q H/HOD ROT 9 OVER < IF 7 + ENDIF 30 + HOLD } 9 : #S BEGIN # OVER OVER OR 0- UNTIL ;
10 i D.R >R SWAP OVER DABS <# #S SIGN #> 11 R> OVER - SPACES TYPE ; 12 t .R >R S->D R> D.R { 13 : D. 0 D.R SPACE ; 14 t . SOD D. ; 15 —>
SCR # 168 0 ( 8088 FORTH - 7 1 : 7 @ { 2 I U. 0 D, | 3 t VLIST 80 OUT t CONTEXT @ Q 4 BEGIN OUT @ C/L > IF CR 0 OUT 1 ENDIF 5 DUP ID. SPACE SPACE PFA LFA Q DUP 0-6 7TERMINAL UNTIL DROP ; 7 8 9 10 11 12 13 14 15 —>
119
Listing 4. 8088 Forth
SCR # 169 0 ( 8088 FORTH - HATCH ) 1 CODE MATCH DI, SI MOV CX FOP BX POP DX POP 2 SI POP SI PUSH 3 BEGIN AL LODS AL, [BX] CMP 4 0- IF BX PUSH CX PUSH SI PUSH 5 BEGIN CX DEC 0<> IF DX DEC 6. 0<> IF BX INC AL LODS AL, [BX] CMP 7 ROT 0<> UNTIL 8 SI POP CX POP BX POP DX POP 9 ROT ENDIF
10 DX DEC ROT 0- UNTIL 11 BEGIN AX, SI MOV SI POP SI, DI MOV DPUSH JMP 12 SWAP ENDIF SWAP ENDIF 13 CX POP CX POP CX POP 00 UNTIL NXT 14 15 -->
SCR # 171 0 < 8088 FORTH AND HETAl COMPILER - FINISH UP ) 1 09 BYTEIIN MESSAGE REPLACED:BY . 2 LAST @ DELTA - OC COHPILE-ADDR + ! 3 LAST 0 DELTA - 04 BYTEtIN FORTH ! 4 80E1 'NF X CFA 4 - DELTA +1 5 HERE DELTA - 1C COMPILE-ADDR + ! 6 HERE DELTA - IE COMPILE-ADDR + 1 7 04 BYTE!IN FORTH DELTA - 20 COMPILE-ADDR + ! 8 00 BYTEtIN 21 NFA DELTA - -4 BYTEsIN i t 9 00 -4 BYTEtIN LIT t 10 11 /SMUDGE 12 ;S 13 14 15
Listing 4. 8088 Forth
#100 HEC 7220 Graphics routines - defining words )
HEX { RDJ status WTt data port ) ( RDt data WTs command port ) < WT: soom/cofig port ( internal variable for "TO"
0 CONSTANT PTO 51 CONSTANT FT1
2 CONSTANT PT2 00 VARIABLE %TO
OTO 0 XTO I TO 1 XTO I GET 2 XTO 1 PT 3 XTO I ; 2* 2 * }
ARRAY <BUILDS 2* ALLOT D0ES> SWAP 2* + ;
ARRAY - defining word to create an array n ARRAY array.name - m array.name will leave the address of the mth element of the stack ) -->
101 NEC 7220 Graphics ARRAY FUNCTION PTO! @ PTO P! ;
( . ) @ • I PTO! 0 FUNCTION I 1 FUNCTION
@ 2 FUNCTION (.) 3 FUNCTION
routines - defining words
put address of functions ) to be used in the extended TO variable )
VALUE <BUILDS
t < ! ( 1 t D0ES> XTO @ OTO FUNCTION
0 CFA EXECUTE ;
a VALUE has three possible execution statest Formt n VALUE vname 1. vname will send n to port PTO 2. ra TO vname will save m in vname 3. GET vname puts value of vname on stack
102 NEC 7220 Graphics routines - defining words ) CMD <BUILDS , DOES> Q PT1 PJ ;
-->
a CMD has one execution state Formi n CHD cname 1. cname sends n to port PT1
CMD2 <BUILDS , DOES> @ PT2 P! ;
a CMD2 has one execution state ) Form: n CMD2 cname ) 1. cname sends n to port PT2 )
-->
Listing 4. 8068 Forth
SCR 0 1 2 3 4 5 6 7
# 103 ( NEC 7220 Graphics routines - defining words ) ( reset or sync command ) 06 VALUE FLAGS 04 VALUE HFPVSH F1 VALUE ALL ( pram command 00 VALUE SAD1L OF VALUE IMLEN1
8 10 VALUE LEH2SAD2 9 FF VALUE PTNH
10 ( cchar command ) 11 00 VALUE LR 12 ( soom , curs commands 13 00 VALUE ZFACT 14 00 VALUE EADL 00 VALUE EADM 15 -->
3E VALUE AU 07 VALUE HBP 3C VALUE VBPALH
) 00 VALUE SAD1H 40 VALUE SAD2L 3F VALUE XMLEN2
00 VALUE CTOP )
65 VALUE VSLHS 03 VALUE VFP
10 VALUE LEN1SAD1 3C VALUE SAD2M FF VALUE PTNL
00 VALUE CBOT
00 VALUE EACH
SCR 0 1 2 3 4 5 6 7 8 9 10
# 104 ( NEC 7220 Graphics routines - defined words ) ( figs command ) 00 VALUE DIR 00 VALUE DL 00 VALUE D2H 00 VALUE DHL ( mask command FF VALUE ML ( wdat command 00 VALUE VBL ( pitch )
11 40 VALUE PIT 12 ( pramS ) 13 00 VALUE PT08 14 00 VALUE PT11 15 00 VALUE PT14
00 VALUE DCL 00 VALUE DCM 00 VALUE DH 00 VALUE D2L 00 VALUE D1L 00 VALUE D1H 00 VALUE DMH
10 ZOOM ZFACT ZOCON 11 MASK ML HH 12 CURS EADL EADM EADL 13 START ; *4 15 —>
SCR # 107 0 ( NEC 7220 Graphics routines - clear screen ) 1 i 7BUSY BEGIN,PT0 P@ OA AND 0- UNTIL f 2 : (FGl) 7BUSY FIGS DIR DCL DCH ; 3 : (WD1) CLEAR WBL WBH ; 4 i (WD2) ' SET WBL WBH ; 5 J (MSK) MASK ML MH j 6 t PCUR CURS EADL EADH EADH 7 i (STCL) 02 TO DIR FF TO DCL 8 . FF TO ML FF TO HH 9 FF TO WBH 00 TO EADL
10 00 TO EADH ; 11 t (HC) 15 0 DO (FGl) (WD1) LOOP ; 12 t (HS) 15 0 DO (FGl) (WD2) LOOP ; 13 t CLS (STCL) PCUR (MSK) (HC) ; 14 t STS (STCL) PCUR (HSK) (HS) ; 15 —>
SCR # 108 0 ( NEC 7220 Graphics routines - drawline ) 1 t VAL <BUILDS , DOES> XTO @ IF 1 OTO ELSE Q ENDIF ; 2 00 VAL XI 00 VAL X2 00 VAL DX 00 VAL ADX 3 00 VAL Y1 00 VAL Y2 00 VAL DY 00 VAL ADY 4 00 VAL +-X 00 VAL +-Y 00 VAL DLI 00 VAL DLD 5 40 VAL P 6 7 : STOXY TO Y2 TO X2 TO Y1 TO XI J 8 ( NIB> SP@ 1+ C@ SWAP DROP J 9 t <NIB 10 * ;
10 t NIB FF AND } 11 x IEAD XI 10 /HOD P Yt * + DUP NIB TO EADL HIB> TO EADM 12 <NIB TO EADH PCUR j 13 i 7CUR CURD 5 0 DO PTl P@ CR . LOOP ; 14 ; PUT TO Y1 TO XI 7EAD j 15 —>
f 3F TO DCH FF TO WBL 00 TO EADH
Listing 4. 8088 Forth
SCR #109 0 ( NEC 7220 Graphics routines - drawline ) 1 j DLX X2 XI - TO DX j 2 t DLY Y2 Y1 - TO DY ; 3 ( signi 1-poeitlve O-negative ) 4 i SIGNX DX S->D 0- TO +-X AfiS TO ADX j 5 J SIGNY DY SOD 0- TO +-Y ABS TO ADY J
6 7 : 2ARRAY <BVXLDS DUP 2* , * 2* 2-1- ALLOT DOES> 8 DUP @ >R SWAP 2* + SWAP R> * + 2+ j 9 ( n m 2ARRAY name +-x +-y name addr )
10 2 2 2ARRAY 7 QUAD 11 2 0 0 7QUAD I 12 3 0 1 7QUAD 1 ( 7QAUD is a look up table to ) 1 3 1 1 0 7 Q U A D 1 ( d e t e r m i n e t h e q u a d r a n t o f t h e l i n e ) 14 4 11 7QUAD I ( found by the sign of DX and DY ) 15 — >
SCR # 110 0 ( NEC 7220 Graphics routines - drawline ) 1 t 7X>Y ADX ADY > IF 0 ENDIF } 2 : 7X<Y ADX ADY < IF 1 ENDIF ; 3 I 7X-Y ADX ADY - IF 2 ENDIF ; 4 5 3 2ARRAY 7OCT 5 ( 7OCT ia a look up table to determine the octant ) 6 (from the quadrant and the magnitude of ADX and ADY ) 7 ( val quad oflag ) B 9 2 1 0 70CT 1 6 3 0 7 OCT !
10 3 1 1 70CT t 7 3 1 70CT I 11 3 1 2 70CT ! 7 3 2 7 OCT 1 12 5 2 0 70CT I 1 4 0 70CT 1 13 4 2 1 7OCT i 0 4 1 70CT 1 14 5 2 2 70CT I 1 4 2 70CT 1
SCR # 111 0 ( NEC 7220 Graphics routines - drawline ) 1 8 ARRAY 7AXIS 2 3 ( 7AXIS is a look up table to detemine the ) 4 ( dependent and independent axis ) 5 ( 1-Y Indep • 0-X indep > 6 7 10 7AXIS t 1 4 7AXIS t 8 0 1 7AXIS 1 0 5 7AXIS I 9 0 2 7AXIS t 0 6 7AXIS !
10 1 3 7AXIS 1 1 7 7AXIS t 11 12 t 71ND 7AXIS <3 IF ADY TO DLI ADX TO DLD ELSE 13 ADX TO DLI ADY TO DLD ENDIF j 14
. 15 -->
Listing 4. 8088 Forth
SCR #112 0 ( NEC 7220 Graphics routines - drawline+ 1 ( direction masks for figure drawing ) 2 3 t LINES 08 OR TO DIR ; 4 t ARCS 20 OR TO DIR f 5 t RECT 40 OR TO DIR ; 6 l DOT 00 OR TO DIR { 7 t AREA 10 OR TO DIR { 8 A
t SLANT 90 OR TO DIR { J
10 t (FG2) 7BUSY FIGS DIR 11 •
• (FG3) 7BUSY FIGS DIR 12 DHL 13 I (FG4) 7BUSY FIGS DIR
SCR # 113 0 < NEC 7220 Graphics routines - drawline ) 1 t PARTS DUP NIB> 3F AND ; 2 t (DC) PARTS TO DCH TO DCL ; 3 : (D) PARTS TO DH TO DL ; 4 t (D2) PARTS TO D2H TO D2L ; 5 : (Dl) PARTS TO D1H TO D1L ; 6 I D DLD 2* DLI - J 7 t D2 DLD DLI - 2* ; 8 t Dl DLD 2* j 9
SCR # 114 0 ( NEC 7220 Graphics routines - set, clear dots ) 1 t SETRU TO DIR TO DCL TO DCH (FG1) ; 2 t 7READ PTO P@ 1 AND ; 3 : CHORD 7READ IF PT1 P@ . ENDXF { 4 t SETH FF TO ML FF TO MH (HSK) j 5 t SETHI 01 TO HL 00 TO HH (HSK) f 6 : REP REPL PTNL PTNH ; 7 6 ( wdcountH wdcountL direction RUORDS ) 9 t RUORDS SETH SETRU READU BEGIN GUORD 7READ UNTIL } 10 11 ( wdcountH wdcountL direction UUORD ) 12 i UUORD SETRU REP } 13 t 1D0T SETHI 0 0 2 UUORD ; 14 15 -->
Listing 4. 8088 Forth
SCR #115 0 ( NEC 7220 Graphics routines - zoom ) 1 : SETZ1 1+ MINUS FO OR PT2 PI ; 2 1 SETZ2 <NXB FO AND TO ZFACT ZOOM ZFACT ; 3 4 ( n ZM - room display by n ) 5 : ZM DUP SETZ1 SETZ2 ; 6 7 ( n CZH - zoom character size ) B : CZH OF AND GET ZFACT FO AND OR TO ZFACT ZOOH ZFACT j 9
10 11 12 13 14 15 -->
SCR # 116 0 ( NEC 7220 Graphics routines - rectangle ) 1 j 1- 1 - } 2 : SETR RECT 1- DUP TO D2L NIB> TO D2H 3 1- DUP TO DL DUP TO DHL NIB> DUP 4 TO DH TO DCL 03 TO DCL 00 TO DCH 5 FF TO D1L 3F TO D1H ; 6 7 ( xl yl ilen plen pdir RECTANGLE ) 6 t RECTANGLE SETR PUT (FG3) FZGD { 9 10 11 12 13 14 15 -->
SCR # 117 0 ( NEC 7220 Graphics routine - characters, fill ) 1 t (CHAR) 7 TO DCL 0 TO DCH 2 7 TO D2L 0 TO D2H 3 8 TO DL 0 TO DH ; 4 5 ( pl5, pl4, pl3, pl2, pll, plO, p9, p8 CHAR cname ) 6 ( cname will put character at current cpostion ) 7 ( based o£ pram ram data pl5-p8 ) 8 9 t CHAR <BUXLDS C, C, C, C, C, C, C, C, D0ES>
10 PRAM8 DUP 8 + SWAP DO I C@ PTO P! LOOP 11 (CHAR) (FG4) GCHRD ; 12 13 ( preceeded by n AREA or n SLANT n is the direction ) 14 15 -->
Listing 4. 8088 Forth
SCR #116 0 ( NEC 7220 Graphics routines - circle ) 1 0 VAL RAD 00 VAL RX1 00 VAL RY1 2 t 1/SQR2 RAD 3624 4C91 */ , 3 t 2MSK 3FPF AMD ; 4 t STOXYR TO RAD TO RY1 TO RX1 ; 5 1 1PT RX1 RAD + TO XI RY1 TO Y1 ; 6 : 2PT RY1 RAD + TO Y1 RX1 TO XI ; 7 t 3PT RX1 RAD - TO XI RY1 TO Y1 ; 8 t 4PT RY1 RAD - TO Yi RX1 TO XI { 9 i <CIR) ARCS 1/SQR2 2MSK DUP TO DCL NXB> TO DCH
10 RAD 1- DUP DUP TO DL NIB> TO DH 11 2 * 2HSK DUP TO D2L NIB> TO D2H 12 FF TO D1L 3F TO D1H 13 00 TO DHL 00 TO DHK <FG3> FIGD } 14 15 -->
SCR # 120 0 ( NEC 7220 Graphics routines - area fill ) 1 J (FILL) 1- DUP TO DCL NIB> TO DCH 2 DUP TO DL DUP TO D2L 3 NXB> DUP TO DH TO D2H ; 4 5 ( ptl5....pt8 PFXLL cname ) 6 ( xl yl ilen plen dir cname ) 7 t PFXLL <BUXLDS C, C, C, C, C, C, C, C, D0ES> 8 PRAMS DUP 8 + SWAP DO X C@ PTO PI LOOP 9 (FILL) PUT (FG4) GCHRD ; 10 11 ( used with n AREA or n SLANT ) 12 13 14 15 -->
Listing 4. 8088 Forth
SCR #121 0 { NEC 7220 Graphics routines - partions ) 1 00 VAL SXl 00 VAL SYl P VAL SPl 2 00 VAL SX2 00 VAL SY2 P VAL SP2 3 i (SD1) PRAMO SADIL SAD1H LEN1SAD1 IMLEN1 ; 4 1 (SD2) PRAM4 SAD2L SAD2M LEN2SAD2 IMLEN2 ; 5 t STOSl SWAP TO SYl SWAP TO SXl | 6 J STOS2 SWAP TO SY2 SUAP TO SX2 » 7 ( xl yl lien 7SAD1 - sat area partionl ) 8 ( 7SAD1 STOSl SXl 10 /MOD SPl SYl * + DUP TO SADIL 9 HIB> TO SAD1M DROP DUP <HIB TO LEN1SAD1
. 10 HIB> TO IMLEN1 (SD1) J
11 ( xl yl lien 7SAD2 - set area partion2 ) 12 t 7SAD2 ST0S2 SX2 10 /MOD SP2 SY2 * + DUP TO SAD2L 13 HIB> TO SAD2M DROP DUP <NIB TO LEN2SAD2 14 NIB> TO IMLEN2 (SD2) ; 15 ;S
SCR # 122 0 ( NEC 7220 Graphics routines - demo ) 1 : (PTN) TO PTHL TO PTNH PRAM8 PTNL PTHH ; 2 J SLINE 255 255 (PTN) ; 3 i BORDER SLINE 0 0 240 1023 0 RECTANGLE ; 4 0 VAL CNT 32 VAL CNT2 5 t OCNT 0 TO CNT ; 6 t CNT+ CNT CNT2 + TO CNT j 7 t CUPT CNT+ CNT DUP NIB> SUAP (PTN) } B j LNS CLS SET OCNT 1023 0 DO I 0 1023 I - 240 DRAWLINE 9 CHPT CNT2 +LOOP ; 10 11 ! DEHOO CLS 0 0 240 7SAD1 32 TO CMT2 LNS ; 12 ! DEMOl 0 0 240 CLS 7SAD1 1 TO CNT2 LNS j 13 14 15 -->
SCR # 123 0 ( NEC 7220 Graphics routines - demo ) 1 t 7VSYNC BEGIN PTO P@ 96 AND UNTIL ; 2 i SLIDE 1024 0 DO I 0 240 7VSYNC 7SAD1 CNT2 +LOOP \ 3 HEX 4 55 55 55 55 55 55 55 55 PFILL PAT1 5 00 00 00 00 00 00 00 00 PFILL PAT2 6 FF FF FF FF FF FF FF FF PFILL PAT3 7 33 CC 33 CC 33 CC 33 CC PFILL PAT4 8 77 EE 77 EE 77 EE 77 EE PFILL PAT5 9 88 11 88 11 88 11 88 11 PFILL PAT6
10 FF FE FC F8 EO CO 10 00 PFILL PAT7 11 00 01 CO EO F8 FC FE FF PFILL PAT8 12 IF 10 10 IE 10 10 IF 00 CHAR EEE 13 14 DECIMAL 15 -->
128
Listing 4. 6088 Forth
SCR #124 0 ( NEC 7220 Graphics routines - demo ) 1 0 VAL WH 0 VAL LH 2 0 VAL CX 0 VAL CY 3 : (CUB) TO LH TO UH TO CY TO CX ; 4 5 ( xl yl width length CUBE ) 6 I CUBE (CUB) REPL 6 AREA CX CY VH LH PAT6 7 2 SLANT CX WH - CY VH LH PAT4 8 3 SLANT CX CY LH + LH LH PAT3 ; 9 10 11 12 13 14 15 -->
SCR # 125 0 ( NEC 7220 Graphics routines - demo ) 1 : VSLIDE 240 0 DO 0 I 240 7VSYNC 7SAD1 LOOP j 2 t TIME 20000 TO CNT ; 3 i WAIT TIME CNT 0 DO LOOP ) 4 : DZH TIME -1 14 DO I ZM WAIT -1 +L00P j 5 : BOXES 32 7 10 10 CUBE 32 260 10 10 CUBE 6 64 30 20 30 CUBE 64 270 20 30 CUBE 7 700 50 20 40 CUBE 700 300 20 40 CUBE 8 128 60 10 60 CUBE 128 300 10 60 CUBE 9 500 100 200 50 CUBE 500 340 200 50 CUBE