An Inductorless 0.3-2.6 GHz CMOS Receiver Front-end Group 3 Muhammad Faisal, David Pfeiffer, and Brian Stump
An Inductorless 0.3-2.6 GHz CMOS Receiver Front-end
Group 3 Muhammad Faisal, David Pfeiffer,
and Brian Stump
Outline
1. Motivation2. Architecture3. Low Noise Amplifier4. Mixer5. Baseband Filter6. Results7. Layout and Comparison8. Conclusions
1. Motivation
• Need to support each wireless standard– Software-Defined Radio Wideband
LNA
Widely Tunable LO
Tunable Baseband
Filter(s)
ADC
This Work
• Solutions:1. GHz Analog-to-Digital ConvertersExpensivePower Hungry
2. Flexible Wideband RF Front-ends Lower Cost Low Power
1. Why Inductorless?
• Smaller area Lower cost– 50 Ω at 300 MHz L ≈ 27 nH– Outer Dimension 1 (n=15):
Octagonal = 310 μm; Hexagonal = 315 μm; Square = 290 μm
• Wideband operation– Wideband matching with inductors requires a ladder
• Less substrate coupling• Easier to integrate with baseband/digital circuitry
1. S.S. Mohan, T.H. Lee, “Integrated Spiral Inductor Calculator”, Stanford Microwave Integrated Circuits Laboratory.
2. Front-end Architecture
• Direct conversion• Quadrature• Variable gain LNA
– Dynamic Range
• Fully differential– Reduce common
mode noise– Help IIP2
• Tunable filters
3. Low Noise Amplifier
• Source follower output– Isolates– Drives large mixer input
• Variable gain• No need for output
impedance matching
4. Mixer• Two Stages
– Transconductance– double-balanced
switching quad
• Goals:– Noise– Linearity– Conversion Gain– Power
Gm
Zf
Zf
Cpar
Cpar
VRF VIF
Zgm
LO+
LO+
LO-
Z’gm
4. Mixer: Gm Stage
• Complementary Input– Higher effective Gm
• DC coupled to the switching quad– No DC Current Output– Mid-rail VOUT
• Multi-gated Transistors– Subthreshold– Linearity
Vin+Vin-
VDD
GND
Io+
Io-
Vb1
Vb_MGN
Vb_MGP
4. Gm Linearity (Multi-gated FETs)
• IIP3 Second Derivative of gm
Highly non-linear• Solution: Parallel FET
in subthreshold• [No] Additional Power
RFin
Rugh, J. W. “Nonlinear System Theory: The Volterra/Wiener Approach”, 1981
EECS 522 View
Volterra Series
0 0.4 0.8 1.2
-2
0
2
4
VGS (V)
d/dv
gs(d
/dv g
s(gm
))
Effective g’’m
0 0.4 0.8 1.2-2
0
2
4
VGS (V)d/
dvgs
(d/d
v gs(g
m))
4. “Passive” Mixer LO+
LO+
LO-VRFTo Opamp
• No IDC Low Flicker Noise• Biased at in triode • VG= Vthreshold
• LO-to-RF/LO-to-IF feedthrough and RON trade-off
RON
GateCgdCgs
Rsub
CdjCsj
IFRF
“ON” Switch
GateCgdCgs
Rsub
CdjCsjCgb
“OFF” Switch
W for RON vs. W for Feedthrough Cap
5. Active RC Filter• Active RC filter
– Tunable with Off-Chip Passives– Open-Loop Attributes
• BW = 20 MHz• Gain = 70dB
• Topology– Folded Cascode
• Simplicity• Noise/Linearity tradeoff
– Common-Mode Feedback
Vref
Vbias2
VDD
Vref
Vbias2
Vx Vy
Vx Vy
Vout-Vout+
Vin-
Vbias1
Vin+M1 M2
M7 M8
M9 M10
5. Amplifier Linearity
• Importance of last stage in cascade
• Design Considerations– Differential circuit– Decrease gain error
• Common-mode feedback– Basic resistor divider– Cross-coupled topology
6. Results: LNA S11
0 0.5 1 1.5 2 2.5 3
-10
-8
-6
-4
-2
0
RF Frequency (GHz)
S11
(dB
)
LNA Low Gain
LNA High Gain
6. Results: Conversion Gain
105 10 6 10 7 1080
10
20
30
40
Intermediate Frequency (Hz)
Con
vers
ion
Gai
n (d
B)
6. Results: Noise Figure
2 4 6 8 103.2
3.6
4
4.4
4.8
Intermediate Frequency (MHz)
Noi
se F
igur
e (d
B)
LO = 2.5GHz
LO = 2.0GHz
LO = 1.5GHz
LO = 900MHz
6. Results: Linearity
-30 -20 -10 0 10-80
-40
0
40
80
Input Power (dBm)
Out
put P
ower
(dB
m)
First Order
Third Order
IP3
1 1.5 2 2.5-8
-6
-4
-2
0
2
4
LO Frequency (Offset Frequency = 5 MHz)
IIP3
(dB
m)
• Improves with LO frequency• Example for 2GHz (right)
7. Performance ComparisonParameters [1] [2] [6] This Work
Bandwidth RF (GHz) .3-2.6 .9 .1-3.85 .3-2.6
Conversion Gain (dB) 38 18 20 35
Bandwidth IF (MHz) .250 - 70 1-10
NF (dB) 3.6 DSB 10 SSB 8.4-11.5 3.3 DSB*IIP3 (dBm) 4 30 - -3.8**
Power (mW) 52.5 16.2 9.78 23.3***Technology (µm) 0.13 CMOS 0.35 CMOS 0.09 CMOS 0.13 CMOS
Notes Mixer only LNA + Mixer
* LO 900 MHz, IF 5 MHz ** LNA in high gain mode*** Excludes Biasing and LO circuitry
8. Conclusion
• Inductorless Front-end– Low Noise– High Linearity– Wideband– Appropriate for SDR
• Future improvements– Addition of LO Circuitry
References
[1] Poobuapheun, N.; Wei-Hung Chen; Boos, Z.; Niknejad, A.M.; , "An inductorless high dynamic range 0.3 − 2.6 GHz receiver CMOSfront- end," Radio Frequency Integrated Circuits Symposium, 2009. RFIC 2009. IEEE , vol., no., pp.387-390, 7-9 June 2009
[2] Poobuapheun, N.; Wei-Hung Chen; Boos, Z.; Niknejad, A.M.; , "A 1.5V 0.7-2.5GHz CMOS Quadrature Demodulator for Multi-BandDirect-Conversion Receivers," Custom Integrated Circuits Conference, 2006. CICC '06. IEEE , vol., no., pp.797-800, 10-13 Sept. 2006
[3] A. Amer, E. Hegazi, and H. F. Ragaie, “A 90-nm wideband merged CMOS LNA and mixer exploiting noise cancellation,” IEEE J. Solid-State Circuits, vol. 42, no. 2, pp. 323–328, Feb. 2007.
[4] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, 1st ed. Cambridge, U.K.: Cambridge Univ. Press, 1998.[5] M. T. Terrovitis and R. G. Meyer, “Intermodulation distortion in current- commutating CMOS mixers,” IEEE J. Solid-State Circuits, vol.
35, no. 10, pp. 1461–1473, Oct. 2000.[6] E. Sacchi, I. Bietti, S. Erba, L. Tee, P. Vilmercati, and R. Castello, “A 15 mW, 70 kHz 1/f corner direct conversion CMOS receiver,” in
Proc. IEEE Custom Integrated Circuits Conf., San Jose, CA, Sep. 2003, pp. 459–462.[7] Nam, I.; Bonkee Kim; Kwyro Lee; , "CMOS RF amplifier and mixer circuits utilizing complementary Characteristics of parallel
Combined NMOS and PMOS devices," Microwave Theory and Techniques, IEEE Transactions on , vol.53, no.5, pp. 1662- 1671, 2005[8] Tae Wook Kim; Bonkee Kim; Kwyro Lee; , "Highly linear receiver front-end adopting MOSFET transconductance linearization by
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IEEE Journal of , vol.24, no.6, pp.1737-1740, Dec 1989[10] D.D. Wentzloff, “Lecture 9: Intermodulation”, EECS 522 Lecture Notes, University of Michigan, April 2010,