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DUAL GATE SINGLE MATERIAL JLFET
MODELLING
9thMay 2014
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GOALS
Motivation
DGSMJLFET Device Operation
Surface potential modelingtheoretical
Creating Model
Surface potentialsimulation results
Correlating Model vs Simulation results
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MOTIVATION
Aggressive Scaling.
Difficult to control Abrupt junction profiles.
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DGSMJLFET Device Operation
The device works in two mode full-depletion and accumulation
In Full-Depletion mode there are no mobile charges present in
channel for conduction hence the device is in off state
As the voltage starts to increase on gate (assuming N device) the
device starts to move from fully depleted mode to accumulationmode
In accumulation mode, as there are mobile charges present in
channel so the device is turned on
Figures 1 and 2 shows conc. Of carriers at off and on states
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Carrier Conc. Vg=0V (Off state)
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Carrier Conc. Vg=1V ( On State)
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SIMULATION RESULTS
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DEVICE PROPERTY
DEVICE PROPERTY
TYPE N+ Si
DOPING 1*1E+19
SUBSTRATE THICKNESS 10nm
ToX 1nm
GATE PPOLY
GATE LENGTH 1um
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Surface Potential @ VG=0V
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Surface Potential @ Vg=1.0V
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Energy Band Diagram @ Vg=0V
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Id-VgsCurve Vg(-0.5V to 1V)
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Analytical Model
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1-D Poisson Equation
()
(1)
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Energy Band Diagram
Symmetrical behavior of gates.
Figure: [2]
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Boundary Conditions
()
() . (2)
()
|x=0
(3)
(0) =0 , for gate voltages above
threshold voltage of device.
Figure: [2]
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Integral Solution
()
= ()
= ()2
()/ ()/ + /
()/ ()/ (0)
(4)
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Bulk Charge
2 ( 0 ) (5)
(6)
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Solving for (s)
Equation 4 , using equation 2,3,5 and 6 reduces to: (0) = VgVFB; for Vg< threshold voltage of device.
(0) = 0; for Vg> threshold voltage of device.
Finally (s) :
0
(7)
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Approximations
(0) = 0 , if the device is conducting. (s) = 0 , for Flat band conditions.
For Vg> VFB, charge term still taken as that of fully
depleted.
Behavior of both gates is symmetrical.
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Correlation Model vs. Simulation
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Simulation data
SURFACE POTENTIAL (V)
Vgate(V) X=-5nm X=-4 X=-2 X=-1 X=-0.5 X=-0.1 X=0 X=0.1 X=0.5 X=1 X=2 X=4 X=5nm
0 -0.795 -0.743 -0.634 -0.611 -0.605 -0.604 -0.604 -0.604 -0.605 -0.611 -0.634 -0.743 -0.795
0.25 -0.504 -0.4762 -0.384 -0.361 -0.356 -0.355 -0.354 -0.355 -0.356 -0.361 -0.384 -0.4762 -0.504
0.5 -0.297 -0.256 -0.138 -0.116 -0.11 -0.108 -0.108 -0.108 -0.11 -0.116 -0.138 -0.256 -0.297
0.75 -0.082 -0.095 -0.036 -0.028 -0.026 -0.025 -0.025 -0.025 -0.026 -0.028 -0.036 -0.095 -0.082
1 -0.017 -0.017 -0.016 -0.016 -0.016 -0.016 -0.016 -0.016 -0.016 -0.016 -0.016 -0.017 -0.017
1.2 0.036 0.003 -0.012 -0.014 -0.014 -0.014 -0.014 -0.014 -0.014 -0.014 -0.012 0.003 0.036
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Analytical Model data
SURFACE POTENTIAL (V)
Vgate(V) X=-5nm X=-4 X=-2 X=-1 X=-0.5 X=-0.1 X=0 X=0.1 X=0.5 X=1 X=2 X=4 X=5nm
0 -0.78969 -0.7214 -0.63035 -0.60759 -0.6019 -0.60008 -0.6 -0.60008 -0.6019 -0.60759 -0.63035 -0.7214 -0.78969
0.25 -0.53969 -0.4714 -0.38035 -0.35759 -0.3519 -0.35008 -0.35 -0.35008 -0.3519 -0.35759 -0.38035 -0.4714 -0.53969
0.5 -0.28969 -0.2214 -0.13035 -0.10759 -0.1019 -0.10008 -0.1 -0.10008 -0.1019 -0.10759 -0.13035 -0.2214 -0.28969
0.75 0.189692 0.121403 0.030351 0.007588 0.001897 7.59E-05 7.59E-07 7.59E-05 0.001897 0.007588 0.030351 0.121403 0.189692
1 0.189692 0.121403 0.030351 0.007588 0.001897 7.59E-05 7.59E-07 7.59E-05 0.001897 0.007588 0.030351 0.121403 0.189692
1.2 0.189692 0.121403 0.030351 0.007588 0.001897 7.59E-05 7.59E-07 7.59E-05 0.001897 0.007588 0.030351 0.121403 0.189692
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Comparison
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
-5 -4 -2 -1 -0.5 -0.1 0 0.1 0.5 1 2 4 5
MODEL , VG=0
MODEL , VG=0.25
MODEL , VG=0.5
MODEL , VG=0.75
MODEL , VG=1
MODEL , VG=1.2
SIM , VG=0
SIM , VG=0.25
SIM , VG=0.5
SIM , VG=0.75
SIM , VG=1
SIM , VG=1.2
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Future Targets
Model Drain current using model developed for (s). Develop model for Dual gate dual material device.
Add second order effects to the model.[7][8][9][10]
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junctionless transistors." Electron Devices, IEEE Transactions on58.12 (2011): 4219-4225.
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