IN2305-II Embedded Programming

IN2305-IIEmbedded Programming

Lecture 2:Digital Logic

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Main Subjects

Combinational logic: no memory (state)Sequential logic: state (clocked)VHDL implementation issuesHow to model / synthesize digital circuits

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VHDL in a Nutshell

y <= x or c;c <= a and b;z <= y when p else not y when not p;process (s) begin a <= not s; end process; -- a <= not s;

concurrent execution model: everything executes in parallel (data flow)

behavioral versus structural specification: structural = composition (“wiring”)

sequential behavior (state):

z <= y when p; -- no else => latchprocess (clk) begin y <= x; -- sample x when clk changes -> latch if clk = ‘1’ then q <= d; -- d-ff (pos edge-trig)end process;

note: within process: sequential execution model

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Combinational Logic

y <= a and b;ab

y

ab

y

a y

y <= a or b;

y <= not a;

Essence of combinatorics: process triggered by the input events(y assignment is synchronous with a and b signal changes)

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Example Combinational Blocks

with a select -- enc y <= “00” when “0001”, “01” when “0010”, “10” when “0100”, “11” when “1000”;

ad

ydec

24

a yenc4 2

with a select -- dec z <= “0001” when “00”, “0010” when “01”, “0100” when “10”, “1000” when “11”;y <= z when d = ‘1’ else “0000”;

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Example Combinational Blocks

ab

ymux

with s select -- mux y <= a when ‘0’, b when ‘1’;

s

a

b

8

8

op

8y

with op select -- alu y <= a + b when ‘00’, a and b when ‘01’, ...

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Sequential Logic

process (clk) -- d-ffbegin if rising_edge(clk) then q <= d; end if;end process;

d

Essence of state: assignment is NOT triggered by input eventsbut by an auxiliary signal (usually called a clock)

q

clk

process (d) -- bufferbegin q <= d; -- only sensitive to d => combinational!end process;

dff

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Comb. + Sequential: FSM

process -- fsmbegin wait until rising_edge(clk); case s is when 0x”00” => if (x = ‘1’) then s <= 0x”01”; end if; y <= ‘1’; when 0x”01” => .. .. end case;end process;

s

clk

dff

cmb

Mealy FSM: y = f(s,x) Moore FSM: y = f(s)

x y

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Example Sequential Blocks (1)

yram

process -- rambegin wait until rising_edge(clk); if (we = ‘1’) then mem(a) <= d; end if; y <= mem(a);end process;

clk

da

we

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Example Sequential Blocks (2)

yctr

process -- counterbegin wait until rising_edge(clk); if (rst = ‘1’) then c <= (others => ‘0’); else c <= c + 1; end if; y <= c;end process;

clk

rst

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Tri-state Logic: Busses

ay

oe_a

b

oe_b

y <= a when oe_a = ‘1’ else ‘Z’;

y <= b when oe_b = ‘1’ else ‘Z’;

More efficient than mux for n-bit data paths

dec

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Simple Processor (Delta)

r0 r1

pc

alu

..

decrom

a

rn...

data bus

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VHDL Implementation IssuesStructural synthesis

entities reg, tristate-buf, rom, enc, alu, connected by bus each entity behavioral example: Delta-1 source code

Behavioral synthesis entities cpu, rom cpu entirely behavioral example: X32 source code pro: simple, understandable code, virtually no HW design con: more burden on synthesizer, less efficient HW (space),

potentially larger critical path which may lead to slower freq.

Trade-off depends on appl. and available resources

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Behavioral Approachprocess -- delta cpu (behavioral)begin wait until rising_edge(clk); .. case op is when .. => pc <= op(..); -- jp .. when .. => r(a) <= acc; -- st r.. when .. => acc <= acc + op(..); -- add #.. when .. => acc <= acc and r(a); -- and r.. when .. => if (zero = ‘1’) then -- bz .. pc <= op(..); end if; end case; if (-- not jp/bz/bc/..) then pc <= pc + 1;end process;

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Button Debouncer

Vcc

GND

x:x

y:

time

x’

10

x

2

t’t,x

t,x’

x

x’

0: output’, timer enable’1: output, timer enable2: output, timer enable’

tmre t

clk

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Debouncer Code (1)process -- fsm (behavioral)begin wait until rising_edge(clk); case s is when “00” => if (x = ‘1’) then s <= ”01”; end if; when ”01” => if (t = ‘1’) then s <= “00” when (x = ‘0’) else “10” when (x = ‘1’); end if; when “10” => if (x = ‘0’) then s <= “00”; end if; end case; output <= ‘0’ when (s = “00”) else ‘1’; timer_enable <= ‘1’ when (s = “01”) else ‘0’;end process;

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Debouncer Code (2)process -- timer (behavioral)begin wait until rising_edge(clk); if (timer_enable = ‘0’) then counter <= (others => ‘0’); t <= ‘0’; else if (counter < THRESHOLD) then counter <= counter + 1; else t <= ‘1’; end if; end if;end process;

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Demo using FPGA boardFPGAs are a flexible, low-cost “bread-board” to experiment with HW using SW (VHDL) instead of ICs and wiresXilinx Board:

Cheap: $99

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Demo

Demo ..

(vhdl_projects.tgz, debouncer)

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Autorepeat

input:

output:

time

i’

/o/o’

i/o’

t1’.i

t1.i t2.i

t2’.i

i’

t1 t2

t2’.i

t2.i /o

i’

t2

i’

clk

t2

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Autorepeat Codeprocess -- fsm, using counter is more simplebegin wait until rising_edge(clk); case s is when “00” => if i = ‘1’ then c <= ..; s <= ”01”; end if; when ”01” => if i = ‘0’ then s <= “00”; end if; c <= c + 1; if c > .. then c <= ..; s <= “10”; end if; when “10” => if i = ‘0’ then s <= “00”; end if; c <= c + 1; if c > .. then c <= ..; s <= “11”; end if; when “11” => if i = ‘0’ then s <= “00”; end if; c <= c + 1; if c > .. then c <= ..; s <= “10”; end if; end case; output <= ‘1’ when s = “01” and s = “11” else ‘0’;end process;

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Demo

Demo ..

(vhdl_projects.tgz, reaction timer)