i.MX 6SoloLite Applications Processor Reference Manual Document Number: IMX6SLRM Rev. 1, 04/2013
IMX6SLRM Processor Reference Manual
Nov 26, 2015
IMX6SLRM Processor Reference Manual
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i.MX 6SoloLite ApplicationsProcessor Reference Manual
Document Number: IMX6SLRMRev. 1, 04/2013
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i.MX 6SoloLite Applications Processor Reference Manual, Rev. 1, 04/2013
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Contents
Section number Title Page
Chapter 1Introduction
1.1 About This Document...................................................................................................................................................125
1.1.1 Audience......................................................................................................................................................125
1.1.2 Organization.................................................................................................................................................125
1.1.3 Suggested Reading.......................................................................................................................................126
1.1.3.1 General Information.................................................................................................................126
1.1.3.2 Related Documentation............................................................................................................126
1.1.4 Conventions.................................................................................................................................................126
1.1.5 Register Access............................................................................................................................................128
1.1.5.1 Register Diagram Field Access Type Legend..........................................................................128
1.1.5.2 Register Macro Usage..............................................................................................................128
1.1.6 Signal Conventions......................................................................................................................................129
1.1.7 Acronyms and Abbreviations.......................................................................................................................130
1.2 Introduction...................................................................................................................................................................131
1.3 Target Applications.......................................................................................................................................................132
1.4 Features.........................................................................................................................................................................132
1.5 Architectural Overview.................................................................................................................................................135
1.5.1 Simplified Block Diagram...........................................................................................................................135
1.5.2 Architectural Partitioning.............................................................................................................................136
1.5.3 Endianness Support......................................................................................................................................138
1.5.4 Memory Interfaces.......................................................................................................................................138
Chapter 2Memory Maps
2.1 Memory system overview.............................................................................................................................................139
2.2 ARM platform memory map........................................................................................................................................139
2.3 DMA memory map.......................................................................................................................................................145
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Chapter 3Interrupts and DMA Events
3.1 Overview.......................................................................................................................................................................147
3.1.1 AP interrupts................................................................................................................................................147
3.2 SDMA event mapping..................................................................................................................................................151
Chapter 4External Signals and Pin Multiplexing
4.1 Overview.......................................................................................................................................................................153
4.1.1 Pin Assignments...........................................................................................................................................153
4.1.2 Muxing Options...........................................................................................................................................208
Chapter 5Fusemap
5.1 Boot Fusemap...............................................................................................................................................................255
5.2 Lock Fusemap...............................................................................................................................................................262
5.3 Fusemap Descriptions Table.........................................................................................................................................263
Chapter 6External Memory Controllers
6.1 Overview.......................................................................................................................................................................271
6.2 Multi-mode DDR controller (MMDC) overview and feature summary......................................................................271
6.3 EIM-PSRAM/NOR Flash controller overview.............................................................................................................272
6.3.1 EIM features.................................................................................................................................................273
6.3.2 EIM boot scenarios......................................................................................................................................274
6.3.3 EIM boot configuration................................................................................................................................274
6.3.4 OneNAND requirements..............................................................................................................................274
Chapter 7System Debug
7.1 Overview.......................................................................................................................................................................275
7.2 Chip and Cortex-A9 Core Platform Debug Architecture.............................................................................................275
7.2.1 Debug Features............................................................................................................................................276
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7.2.2 Debug System components..........................................................................................................................277
7.2.2.1 AMBA trace bus (ATB)...........................................................................................................278
7.2.2.2 ATB replicator.........................................................................................................................278
7.2.2.3 Embedded Cross Triggering....................................................................................................278
7.2.2.3.1 Cross-Trigger Matrix (CTM)............................................................................279
7.2.2.3.2 Cross-Trigger Interface (CTI)...........................................................................280
7.2.2.4 Debug Access Port (DAP).......................................................................................................280
7.2.2.5 CoreSight trace port interface (TPIU)......................................................................................281
7.2.3 i.MX6SoloLite-Specific SJC Features.........................................................................................................282
7.2.3.1 JTAG Disable Mode................................................................................................................282
7.2.3.2 JTAG ID...................................................................................................................................282
7.2.4 System JTAG Controller - SJC....................................................................................................................283
7.2.5 System JTAG controller main features........................................................................................................283
7.2.6 SCJ TAP Port...............................................................................................................................................283
7.2.7 SJC main blocks...........................................................................................................................................283
7.3 Smart DMA (SDMA) core............................................................................................................................................284
7.3.1 SDMA On Chip Emulation Module (OnCE) Feature Summary.................................................................284
7.3.1.1 Other SDMA Debug Functionality..........................................................................................285
7.3.1.2 SDMA ROM Patching.............................................................................................................286
7.4 Miscellaneous...............................................................................................................................................................286
7.4.1 Clock/Reset/Power.......................................................................................................................................286
7.5 Supported tools.............................................................................................................................................................286
Chapter 8System Boot
8.1 Overview.......................................................................................................................................................................289
8.2 Boot modes...................................................................................................................................................................290
8.2.1 Boot mode pin settings.................................................................................................................................290
8.2.2 High level boot sequence.............................................................................................................................291
8.2.3 Boot From Fuses Mode (BOOT_MODE[1:0] = 00b).................................................................................292
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8.2.4 Serial Downloader........................................................................................................................................293
8.2.5 Internal Boot Mode (BOOT_MODE[1:0] = 0b10)......................................................................................294
8.2.6 Boot security settings...................................................................................................................................295
8.3 Device Configuration....................................................................................................................................................296
8.3.1 Boot eFUSE Descriptions............................................................................................................................296
8.3.2 GPIO Boot Overrides...................................................................................................................................298
8.3.3 Device Configuration Data..........................................................................................................................300
8.4 Device Initialization......................................................................................................................................................300
8.4.1 Internal ROM /RAM memory map..............................................................................................................300
8.4.2 Boot Block Activation ................................................................................................................................301
8.4.3 Clocks at Boot Time....................................................................................................................................302
8.4.4 Enabling MMU and Caches.........................................................................................................................303
8.4.5 Exception Handling......................................................................................................................................304
8.4.6 Interrupt Handling During Boot...................................................................................................................305
8.4.7 Persistent Bits...............................................................................................................................................305
8.5 Boot Devices (Internal Boot)........................................................................................................................................305
8.5.1 NOR Flash/OneNAND using EIM Interface...............................................................................................306
8.5.1.1 NOR Flash Boot Operation......................................................................................................306
8.5.1.2 OneNAND Flash Boot Operation............................................................................................307
8.5.1.3 IOMUX Configuration for EIM Devices.................................................................................308
8.5.2 Expansion Device........................................................................................................................................309
8.5.2.1 Expansion Device eFUSE Configuration................................................................................309
8.5.2.2 MMC and eMMC Boot............................................................................................................312
8.5.2.3 SD, eSD and SDXC.................................................................................................................320
8.5.2.4 IOMUX Configuration for SD/MMC......................................................................................320
8.5.2.5 Redundant Boot Support for Expansion Device......................................................................321
8.5.3 Serial ROM through SPI and I2C................................................................................................................322
8.5.3.1 Serial ROM eFUSE Configuration..........................................................................................323
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8.5.3.2 I2C Boot...................................................................................................................................324
8.5.3.2.1 I2C IOMUX Pin Configuration........................................................................325
8.5.3.3 ECSPI Boot..............................................................................................................................325
8.5.3.3.1 ECSPI IOMUX Pin Configuration...................................................................327
8.6 Program image..............................................................................................................................................................328
8.6.1 Image Vector Table and Boot Data..............................................................................................................328
8.6.1.1 Image Vector Table Structure..................................................................................................329
8.6.1.2 Boot Data Structure..................................................................................................................330
8.6.2 Device Configuration Data (DCD)..............................................................................................................330
8.6.2.1 Write Data Command..............................................................................................................331
8.6.2.2 Check Data Command.............................................................................................................333
8.6.2.3 NOP Command........................................................................................................................334
8.6.2.4 Unlock Command....................................................................................................................335
8.7 Plugin Image.................................................................................................................................................................335
8.8 Serial Downloader........................................................................................................................................................336
8.8.1 USB..............................................................................................................................................................337
8.8.1.1 USB Configuration Details......................................................................................................338
8.8.1.2 IOMUX Configuration for USB..............................................................................................338
8.8.2 Serial Download protocol............................................................................................................................339
8.8.2.1 SDP Command.........................................................................................................................339
8.8.2.1.1 READ REGISTER............................................................................................339
8.8.2.1.2 WRITE REGISTER..........................................................................................340
8.8.2.1.3 WRITE_FILE...................................................................................................341
8.8.2.1.4 ERROR_STATUS............................................................................................342
8.8.2.1.5 DCD WRITE....................................................................................................343
8.8.2.1.6 JUMP ADDRESS.............................................................................................344
8.9 Recovery Devices.........................................................................................................................................................344
8.10 USB Low Power Boot..................................................................................................................................................345
8.11 SD/MMC Manufacture Mode.......................................................................................................................................346
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8.12 High Assurance Boot (HAB)........................................................................................................................................347
8.12.1 ROM Vector Table Addresses.....................................................................................................................348
Chapter 9Multimedia
9.1 Display and graphics subsystem...................................................................................................................................351
9.1.1 Electrophoretic Display Controller..............................................................................................................352
9.1.2 SiPix Display Controller..............................................................................................................................353
9.1.3 PiXel Pipeline..............................................................................................................................................353
9.1.4 LCD Interface..............................................................................................................................................353
9.1.5 CMOS Sensor Interface...............................................................................................................................354
9.1.6 2D Graphics Processing Unit (GPU2Dv2)..................................................................................................354
9.1.6.1 2D feature summary.................................................................................................................355
9.1.6.2 2D Performance.......................................................................................................................356
9.1.6.3 2D Software.............................................................................................................................356
9.1.7 Vector Graphics Processing Unit (GPUVGv2)...........................................................................................356
9.1.7.1 Vector Graphics Features.........................................................................................................356
9.1.7.2 Vector Graphics Performance..................................................................................................357
9.1.7.3 Vector Graphics Software........................................................................................................357
9.2 Audio subsystem...........................................................................................................................................................357
9.2.1 Audio subsystem module overview.............................................................................................................357
9.2.2 Synchronous Serial Interface (SSI)..............................................................................................................359
9.2.3 Digital Audio MUX (AUDMUX)................................................................................................................359
9.2.4 Sony/Philips Digital Interface (SPDIF).......................................................................................................361
Chapter 10Clock and Power Management
10.1 Introduction...................................................................................................................................................................363
10.2 Device Power Management Architecture Components................................................................................................363
10.2.1 Centralized components of clock generation and management...................................................................364
10.2.2 Centralized components of power generation, distribution and management.............................................365
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10.2.3 Reset generation and distribution system.....................................................................................................365
10.2.4 Power and clock management framework...................................................................................................365
10.3 Clock Management.......................................................................................................................................................366
10.3.1 Centralized components of clock management system...............................................................................366
10.3.2 Clock generation..........................................................................................................................................369
10.3.2.1 Crystal Oscillator (XTALOSC) ..............................................................................................369
10.3.2.2 LVDS I/O ports........................................................................................................................369
10.3.2.3 PLLs.........................................................................................................................................369
10.3.2.3.1 General PLL Control and Status Functions......................................................371
10.3.2.4 CCM ........................................................................................................................................372
10.3.2.5 Low Power Clock Gating unit (LPCG)....................................................................................373
10.3.3 Peripheral components of clock management system.................................................................................373
10.3.3.1 Interface and functional clock..................................................................................................374
10.3.3.2 Block level clock management................................................................................................374
10.3.3.2.1 Master clock protocol.......................................................................................375
10.3.3.2.2 Slave clock protocol..........................................................................................375
10.3.3.3 Clock Domain(s)......................................................................................................................376
10.3.3.4 Domain level clock management.............................................................................................376
10.3.3.5 Domain dependencies..............................................................................................................376
10.4 Power management.......................................................................................................................................................376
10.4.1 Centralized Components of Power Management System............................................................................377
10.4.1.1 Integrated PMU........................................................................................................................377
10.4.1.1.1 Digital LDO Regulators....................................................................................378
10.4.1.1.2 Analog LDO regulators.....................................................................................379
10.4.1.1.3 USB LDO..........................................................................................................380
10.4.1.1.4 SNVS regulator.................................................................................................380
10.4.1.1.5 Reverse well biasing.........................................................................................380
10.4.1.2 GPC - General Power Controller.............................................................................................380
10.4.1.3 SRC - System reset Controller.................................................................................................381
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10.4.1.4 Power domain(s)......................................................................................................................382
10.4.1.4.1 Power distribution ............................................................................................382
10.4.1.4.2 Domain Memory and domain logic state retention in case of Power Gating...383
10.4.1.4.3 Power Gating Domain Management.................................................................384
10.4.1.4.3.1 Cortex-A9 Core Platform.........................................................384
10.4.1.4.3.2 GPU2D.....................................................................................385
10.4.1.4.3.3 SoC...........................................................................................386
10.4.1.4.4 Power Gating domain dependencies.................................................................386
10.4.1.5 Voltage domains......................................................................................................................387
10.4.1.6 Voltage domain management...................................................................................................387
10.4.1.6.1 Dynamic............................................................................................................387
10.4.1.6.1.1 DVFS........................................................................................387
10.4.1.6.1.2 Voltage Scaling........................................................................388
10.4.1.6.2 Static ................................................................................................................389
10.4.1.6.2.1 Standby Leakage reduction (SLR)...........................................389
10.4.1.6.3 Voltage domain dependencies..........................................................................389
10.4.1.6.4 IO voltage .........................................................................................................390
10.4.1.7 system domains layout.............................................................................................................390
10.4.2 Power management techniques....................................................................................................................392
10.4.2.1 Power saving techniques..........................................................................................................393
10.4.2.2 Thermal-aware power management.........................................................................................393
10.4.2.3 Peripheral Power management.................................................................................................394
10.4.2.3.1 Main memory power management...................................................................394
10.4.2.3.2 Video-Graphics system power management....................................................395
10.4.2.3.3 IO power reduction...........................................................................................395
10.4.3 Examples of External Power Supply Interfacing in the i.MX 6SoloLite based systems ............................395
10.5 ONOFF (Button)...........................................................................................................................................................399
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Chapter 11System Security
11.1 Overview.......................................................................................................................................................................401
11.2 Central Security Unit (CSU).........................................................................................................................................403
11.2.1 CSU Overview.............................................................................................................................................403
11.2.2 CSU Features...............................................................................................................................................403
11.2.3 CSU Functional Description........................................................................................................................404
11.2.3.1 CSU Peripheral Access Policy.................................................................................................404
11.3 Secure Non-Volatile Storage (SNVS)..........................................................................................................................405
11.3.1 SNVS Overview...........................................................................................................................................405
11.3.2 Tamper Detection.........................................................................................................................................406
11.4 Data Co-Processor (DCP).............................................................................................................................................406
11.5 High Assurance Boot (HAB)........................................................................................................................................406
11.6 System JTAG Controller (SJC)....................................................................................................................................407
Chapter 12ARM Cortex A9 MPCore Platform (ARM)
12.1 Overview.......................................................................................................................................................................409
12.2 External Signals............................................................................................................................................................409
12.3 Platform configuration..................................................................................................................................................411
12.3.1 Platform and SCU configuration..................................................................................................................411
12.3.2 Core configuration.......................................................................................................................................411
12.3.3 PL310 L2 Cache configuration....................................................................................................................412
12.3.4 Endian Modes..............................................................................................................................................412
12.3.5 Memory Parity error support .......................................................................................................................413
12.4 Performance and Power................................................................................................................................................413
12.4.1 Low-Power design.......................................................................................................................................413
12.4.1.1 SRPG (State Retention Power Gating)....................................................................................413
12.4.1.2 Dynamic Voltage and Frequency Scaling (DVFS)..................................................................414
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12.4.2 Clocks, frequency goals...............................................................................................................................414
12.4.2.1 ARM Clock..............................................................................................................................414
12.4.2.2 Bus Clocks...............................................................................................................................414
12.4.2.3 Debug Clocks...........................................................................................................................414
12.5 Core Platform Sub-Blocks details.................................................................................................................................415
12.5.1 ARM Cortex A9 MPCore Processor............................................................................................................415
12.5.2 Media Processing Engine (MPE - NEON)..................................................................................................415
12.5.3 Generic Interrupt Controller (GIC)..............................................................................................................416
12.5.3.1 Interrupt Controller Features....................................................................................................416
12.5.3.2 About the Interrupt Controller.................................................................................................416
12.5.3.3 Interrupt Controller Clock frequency.......................................................................................416
12.5.3.4 TrustZone support....................................................................................................................416
12.5.4 Instruction and data caches (L1)..................................................................................................................417
12.5.4.1 L1 features................................................................................................................................417
12.5.5 L2 Cache and controller (PL310).................................................................................................................417
12.6 Debug and Trace Sub-blocks (CoreSight components)................................................................................................417
12.6.1 Debug Access Port (DAP) ..........................................................................................................................418
12.6.2 Program Trace Macrocell (PTM).................................................................................................................418
12.6.2.1 Program Flow Trace (PFT)......................................................................................................419
12.6.3 Cross Trigger Interface (CTI)......................................................................................................................420
12.6.4 Embedded Trace Buffer (ETB)....................................................................................................................420
12.6.4.1 AMBA Trace Bus (ATB) Replicator ......................................................................................420
Chapter 13AHB to IP Bridge (AIPSTZ)
13.1 Overview.......................................................................................................................................................................421
13.1.1 Features........................................................................................................................................................421
13.2 Clocks...........................................................................................................................................................................421
13.3 General Operation.........................................................................................................................................................422
13.4 Functional Description..................................................................................................................................................423
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13.5 Access Protections........................................................................................................................................................423
13.6 Access Support..............................................................................................................................................................423
13.7 Initialization Information..............................................................................................................................................424
13.7.1 Security Block..............................................................................................................................................424
13.8 AIPSTZ Memory Map/Register Definition..................................................................................................................425
13.8.1 Master Priviledge Registers (AIPSTZx_MPR)............................................................................................426
13.8.2 Off-Platform Peripheral Access Control Registers (AIPSTZx_OPACR)....................................................428
13.8.3 Off-Platform Peripheral Access Control Registers (AIPSTZx_OPACR1)..................................................431
13.8.4 Off-Platform Peripheral Access Control Registers (AIPSTZx_OPACR2)..................................................434
13.8.5 Off-Platform Peripheral Access Control Registers (AIPSTZx_OPACR3)..................................................437
13.8.6 Off-Platform Peripheral Access Control Registers (AIPSTZx_OPACR4)..................................................440
Chapter 14Digital Audio Multiplexer (AUDMUX)
14.1 Overview.......................................................................................................................................................................443
14.1.1 Features........................................................................................................................................................445
14.1.2 Modes and Operations.................................................................................................................................445
14.2 External Signals............................................................................................................................................................445
14.3 Clocks...........................................................................................................................................................................447
14.3.1 Clock Inputs.................................................................................................................................................447
14.3.2 Clock Diagram.............................................................................................................................................447
14.3.3 Clocking Restrictions...................................................................................................................................448
14.4 Default Register Configuration.....................................................................................................................................448
14.4.1 Default Port Configuration...........................................................................................................................448
14.5 Functional Description..................................................................................................................................................449
14.5.1 Operating Modes..........................................................................................................................................449
14.5.1.1 Port Receive Data Modes.........................................................................................................450
14.5.1.1.1 Normal Mode....................................................................................................451
14.5.1.1.2 Internal Network Mode.....................................................................................452
14.5.1.1.3 Transmit Data Output Enable Assertion...........................................................458
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14.5.1.2 Tx/Rx Switch and External Network Mode.............................................................................459
14.5.1.3 Timing Modes..........................................................................................................................460
14.5.1.3.1 Synchronous Mode (4-Wire Interface).............................................................460
14.5.1.3.2 Asynchronous Mode (6-Wire Interface)...........................................................462
14.5.2 Connectivity Between Ports.........................................................................................................................465
14.5.2.1 Internal Port to External Port Connectivity..............................................................................466
14.5.2.2 External Port to External Port Connectivity............................................................................467
14.5.2.3 Internal Port to Internal Port Connectivity...............................................................................467
14.5.2.4 Loopback Connectivity............................................................................................................468
14.6 AUDMUX Memory Map/Register Definition..............................................................................................................468
14.6.1 Port Timing Control Register 1 (AUDMUX_PTCR1)................................................................................469
14.6.2 Port Data Control Register 1 (AUDMUX_PDCR1)....................................................................................471
14.6.3 Port Timing Control Register 2 (AUDMUX_PTCR2)................................................................................472
14.6.4 Port Data Control Register 2 (AUDMUX_PDCR2)....................................................................................474
14.6.5 Port Timing Control Register 3 (AUDMUX_PTCR3)................................................................................475
14.6.6 Port Data Control Register 3 (AUDMUX_PDCR3)....................................................................................477
14.6.7 Port Timing Control Register 4 (AUDMUX_PTCR4)................................................................................478
14.6.8 Port Data Control Register 4 (AUDMUX_PDCR4)....................................................................................480
14.6.9 Port Timing Control Register 5 (AUDMUX_PTCR5)................................................................................481
14.6.10 Port Data Control Register 5 (AUDMUX_PDCR5)....................................................................................483
14.6.11 Port Timing Control Register 6 (AUDMUX_PTCR6)................................................................................484
14.6.12 Port Data Control Register 6 (AUDMUX_PDCR6)....................................................................................486
14.6.13 Port Timing Control Register 7 (AUDMUX_PTCR7)................................................................................487
14.6.14 Port Data Control Register 7 (AUDMUX_PDCR7)....................................................................................489
Chapter 15Clock Controller Module (CCM)
15.1 Overview.......................................................................................................................................................................491
15.1.1 Features........................................................................................................................................................491
15.1.2 CCM Block Diagram...................................................................................................................................492
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15.2 External Signals............................................................................................................................................................494
15.3 CCM Clock Tree...........................................................................................................................................................494
15.4 System Clocks...............................................................................................................................................................496
15.5 Functional Description..................................................................................................................................................500
15.5.1 Clock Generation.........................................................................................................................................501
15.5.1.1 External Low Frequency Clock - CKIL ..................................................................................501
15.5.1.1.1 CKIL synchronizing to IPG_CLK....................................................................501
15.5.1.2 External High Frequency Clock - CKIH and internal oscillator..............................................501
15.5.1.3 PLL reference clock.................................................................................................................501
15.5.1.3.1 ARM PLL.........................................................................................................502
15.5.1.3.2 USB PLLs.........................................................................................................502
15.5.1.3.3 System PLL.......................................................................................................502
15.5.1.3.4 Audio / Video PLL............................................................................................502
15.5.1.3.5 Ethernet PLL.....................................................................................................502
15.5.1.4 Phase Fractional Dividers (PFD).............................................................................................503
15.5.1.5 CCM internal clock generation................................................................................................504
15.5.1.5.1 Clock Switcher..................................................................................................504
15.5.1.5.2 PLL bypass procedure.......................................................................................506
15.5.1.5.3 PLL clock change.............................................................................................506
15.5.1.5.4 Clock Root Generator.......................................................................................506
15.5.1.5.5 Initial values controlled by the System JTAG Controller (SJC).......................516
15.5.1.5.6 Divider change handshake................................................................................517
15.5.1.6 Disabling / Enabling PLLs.......................................................................................................517
15.5.1.7 Low Power Clock Gating module (LPCG)..............................................................................517
15.5.1.7.1 MMDC handshake............................................................................................519
15.5.2 DVFS support..............................................................................................................................................520
15.5.3 Power modes................................................................................................................................................520
15.5.3.1 RUN mode...............................................................................................................................520
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15.5.3.2 WAIT mode.............................................................................................................................520
15.5.3.2.1 Entering WAIT mode ......................................................................................520
15.5.3.2.2 Exiting WAIT mode ........................................................................................521
15.5.3.3 STOP mode..............................................................................................................................521
15.5.3.3.1 Entering STOP mode .......................................................................................521
15.5.3.3.2 Exiting STOP mode..........................................................................................522
15.6 CCM Memory Map/Register Definition.......................................................................................................................523
15.6.1 CCM Control Register (CCM_CCR)...........................................................................................................524
15.6.2 CCM Control Divider Register (CCM_CCDR)...........................................................................................526
15.6.3 CCM Status Register (CCM_CSR)..............................................................................................................527
15.6.4 CCM Clock Swither Register (CCM_CCSR)..............................................................................................528
15.6.5 CCM Arm Clock Root Register (CCM_CACRR).......................................................................................530
15.6.6 CCM Bus Clock Divider Register (CCM_CBCDR)...................................................................................531
15.6.7 CCM Bus Clock Multiplexer Register (CCM_CBCMR)............................................................................533
15.6.8 CCM Serial Clock Multiplexer Register 1 (CCM_CSCMR1)....................................................................536
15.6.9 CCM Serial Clock Multiplexer Register 2 (CCM_CSCMR2)....................................................................539
15.6.10 CCM Serial Clock Divider Register 1 (CCM_CSCDR1)............................................................................539
15.6.11 CCM SSI1 Clock Divider Register (CCM_CS1CDR)................................................................................542
15.6.12 CCM SSI2 Clock Divider Register (CCM_CS2CDR)................................................................................544
15.6.13 CCM D1 Clock Divider Register (CCM_CDCDR)....................................................................................545
15.6.14 CCM HSC Clock Divider Register (CCM_CHSCCDR).............................................................................547
15.6.15 CCM Serial Clock Divider Register 2 (CCM_CSCDR2)............................................................................548
15.6.16 CCM Serial Clock Divider Register 3 (CCM_CSCDR3)............................................................................550
15.6.17 CCM Divider Handshake In-Process Register (CCM_CDHIPR)...............................................................552
15.6.18 CCM Low Power Control Register (CCM_CLPCR)..................................................................................555
15.6.19 CCM Interrupt Status Register (CCM_CISR).............................................................................................558
15.6.20 CCM Interrupt Mask Register (CCM_CIMR).............................................................................................561
15.6.21 CCM Clock Output Source Register (CCM_CCOSR)................................................................................564
15.6.22 CCM General Purpose Register (CCM_CGPR)..........................................................................................566
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15.6.23 CCM Clock Gating Register 0 (CCM_CCGR0)..........................................................................................567
15.6.24 CCM Clock Gating Register 1 (CCM_CCGR1)..........................................................................................569
15.6.25 CCM Clock Gating Register 2 (CCM_CCGR2)..........................................................................................570
15.6.26 CCM Clock Gating Register 3 (CCM_CCGR3)..........................................................................................572
15.6.27 CCM Clock Gating Register 4 (CCM_CCGR4)..........................................................................................573
15.6.28 CCM Clock Gating Register 5 (CCM_CCGR5)..........................................................................................574
15.6.29 CCM Clock Gating Register 6 (CCM_CCGR6)..........................................................................................576
15.6.30 CCM Module Enable Overide Register (CCM_CMEOR)..........................................................................577
15.7 CCM Analog Memory Map/Register Definition..........................................................................................................578
15.7.1 Analog ARM PLL control Register (CCM_ANALOG_PLL_ARMn).......................................................581
15.7.2 Analog USB1 480MHz PLL Control Register (CCM_ANALOG_PLL_USB1n)......................................583
15.7.3 Analog USB2 480MHz PLL Control Register (CCM_ANALOG_PLL_USB2n)......................................585
15.7.4 Analog System PLL Control Register (CCM_ANALOG_PLL_SYSn)......................................................587
15.7.5 Analog Audio PLL control Register (CCM_ANALOG_PLL_AUDIOn)...................................................589
15.7.6 Numerator of Audio PLL Fractional Loop Divider Register (CCM_ANALOG_PLL_AUDIO_NUM)....591
15.7.7 Denominator of Audio PLL Fractional Loop Divider Register
(CCM_ANALOG_PLL_AUDIO_DENOM)...............................................................................................592
15.7.8 Analog Video PLL control Register (CCM_ANALOG_PLL_VIDEOn)...................................................593
15.7.9 Numerator of Video PLL Fractional Loop Divider Register (CCM_ANALOG_PLL_VIDEO_NUM).....595
15.7.10 Denominator of Video PLL Fractional Loop Divider Register
(CCM_ANALOG_PLL_VIDEO_DENOM)...............................................................................................596
15.7.11 Analog ENET PLL Control Register (CCM_ANALOG_PLL_ENETn)....................................................597
15.7.12 480MHz Clock (from PLL_USB2) Phase Fractional Divider Control Register
(CCM_ANALOG_PFD_480n)....................................................................................................................599
15.7.13 528MHz Clock (From PLL_SYS) Phase Fractional Divider Control Register
(CCM_ANALOG_PFD_528n)....................................................................................................................601
15.7.14 Miscellaneous Control Register (CCM_ANALOG_MISC0n)....................................................................603
15.7.15 Miscellaneous Control Register (CCM_ANALOG_MISC2n)....................................................................604
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Chapter 16CMOS Sensor Interface (CSI)
16.1 Overview.......................................................................................................................................................................609
16.2 External Signals............................................................................................................................................................610
16.3 Clocks...........................................................................................................................................................................611
16.4 Principles of Operation.................................................................................................................................................612
16.4.1 Data Transfer With The Embedded DMA Controllers................................................................................612
16.4.2 Gated Clock Mode.......................................................................................................................................613
16.4.3 Non-Gated Clock Mode...............................................................................................................................614
16.4.4 CCIR656 Interlace Mode.............................................................................................................................614
16.4.5 CCIR656 Progressive Mode........................................................................................................................616
16.4.6 Error Correction for CCIR656 Coding........................................................................................................617
16.5 Interrupt Generation......................................................................................................................................................618
16.5.1 Start Of Frame Interrupt (SOF_INT)...........................................................................................................618
16.5.2 End Of Frame Interrupt (EOF_INT)............................................................................................................618
16.5.3 Change Of Field Interrupt (COF_INT)........................................................................................................618
16.5.4 CCIR Error Interrupt (ECC_INT)................................................................................................................619
16.5.5 RxFIFO Full Interrupt (RxFF_INT)............................................................................................................619
16.5.6 Statistic FIFO Full Interrupt (STATFF_INT)..............................................................................................619
16.5.7 RxFIFO Overrun Interrupt (RFF_OR_INT)................................................................................................619
16.5.8 Statistic FIFO Overrun Interrupt (SFF_OR_INT).......................................................................................619
16.5.9 Frame Buffer1 DMA Transfer Done Interrupt (DMA_TSF_DONE_FB1).................................................619
16.5.10 Frame Buffer2 DMA Transfer Done Interrupt (DMA_TSF_DONE_FB2).................................................620
16.5.11 Statistic FIFO DMA Transfer Done Interrupt (DMA_TSF_DONE_SFF)..................................................620
16.5.12 AHB Bus Response Error Interrupt (HRESP_ERR_INT)...........................................................................620
16.6 Data Packing Style........................................................................................................................................................620
16.6.1 RX FIFO Path..............................................................................................................................................621
16.6.1.1 Bayer Data................................................................................................................................621
16.6.1.2 RGB565 Data...........................................................................................................................621
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16.6.1.3 RGB888 Data...........................................................................................................................622
16.6.2 STAT FIFO Path..........................................................................................................................................624
16.7 CSI Memory Map/Register Definition.........................................................................................................................624
16.7.1 CSI Control Register 1 (CSI_CSICR1).......................................................................................................625
16.7.2 CSI Control Register 2 (CSI_CSICR2).......................................................................................................629
16.7.3 CSI Control Register 3 (CSI_CSICR3).......................................................................................................631
16.7.4 CSI Statistic FIFO Register (CSI_CSISTATFIFO).....................................................................................633
16.7.5 CSI RX FIFO Register (CSI_CSIRFIFO)...................................................................................................634
16.7.6 CSI RX Count Register (CSI_CSIRXCNT)................................................................................................634
16.7.7 CSI Status Register (CSI_CSISR)...............................................................................................................635
16.7.8 CSI DMA Start Address Register - for STATFIFO (CSI_CSIDMASA_STATFIFO)...............................638
16.7.9 CSI DMA Transfer Size Register - for STATFIFO (CSI_CSIDMATS_STATFIFO)................................638
16.7.10 CSI DMA Start Address Register - for Frame Buffer1 (CSI_CSIDMASA_FB1)......................................639
16.7.11 CSI DMA Transfer Size Register - for Frame Buffer2 (CSI_CSIDMASA_FB2)......................................640
16.7.12 CSI Frame Buffer Parameter Register (CSI_CSIFBUF_PARA)................................................................640
16.7.13 CSI Image Parameter Register (CSI_CSIIMAG_PARA)...........................................................................641
Chapter 17Debug Monitor (DBGMON)
17.1 Overview.......................................................................................................................................................................643
17.1.1 Features Summary........................................................................................................................................644
17.1.2 Functional Description.................................................................................................................................644
17.1.3 Application...................................................................................................................................................644
17.2 DBGMON Memory Map/Register Definition..............................................................................................................645
17.2.1 HW_DBGMON_CTRL (DBGMON_HW_DBGMON_CTRL).................................................................646
17.2.2 HW_DBGMON_MASTER_EN (DBGMON_HW_DBGMON_MASTER_EN)......................................648
17.2.3 HW_DBGMON_IRQ (DBGMON_HW_DBGMON_IRQ)........................................................................649
17.2.4 HW_DBGMON_TRAP_ADDR_LOW (DBGMON_HW_DBGMON_TRAP_ADDR_LOW)................650
17.2.5 HW_DBGMON_TRAP_ADDR_HIGH (DBGMON_HW_DBGMON_TRAP_ADDR_HIGH)..............651
17.2.6 HW_DBGMON_TRAP_ID (DBGMON_HW_DBGMON_TRAP_ID)....................................................651
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17.2.7 HW_DBGMON_SNVS_ADDR (DBGMON_HW_DBGMON_SNVS_ADDR)......................................651
17.2.8 HW_DBGMON_SNVS_DATA (DBGMON_HW_DBGMON_SNVS_DATA).......................................652
17.2.9 HW_DBGMON_SNVS_INFO (DBGMON_HW_DBGMON_SNVS_INFO)..........................................653
17.2.10 HW_DBGMON_VERSION (DBGMON_HW_DBGMON_VERSION)...................................................654
Chapter 18Data Co-Processor (DCP)
18.1 Overview.......................................................................................................................................................................655
18.1.1 DCP Limitations for Software.....................................................................................................................657
18.2 Clocks...........................................................................................................................................................................658
18.3 Operation.......................................................................................................................................................................658
18.3.1 Memory Copy, Blit, and Fill Functionality..................................................................................................659
18.3.2 Advanced Encryption Standard (AES)........................................................................................................659
18.3.2.1 Key Storage..............................................................................................................................659
18.3.2.2 AES OTP Key..........................................................................................................................660
18.3.2.3 Encryption Modes....................................................................................................................660
18.3.3 Hashing........................................................................................................................................................662
18.3.4 One Time Programmable (OTP) Key..........................................................................................................663
18.3.5 Managing DCP Channel Arbitration and Performance...............................................................................663
18.3.5.1 DCP Arbitration.......................................................................................................................664
18.3.5.2 Channel Recovery Timers........................................................................................................664
18.3.6 Programming Channel Operations...............................................................................................................665
18.3.6.1 Virtual Channels......................................................................................................................665
18.3.6.2 Context Switching....................................................................................................................666
18.3.6.3 Working with Semaphores.......................................................................................................667
18.3.6.4 Work Packet Structure.............................................................................................................668
18.3.6.4.1 Next Command Address Field..........................................................................668
18.3.6.4.2 Control0 Field...................................................................................................669
18.3.6.4.3 Control1 Field...................................................................................................671
18.3.6.4.4 Source Buffer....................................................................................................672
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18.3.6.4.5 Destination Buffer.............................................................................................672
18.3.6.4.6 Buffer Size Field...............................................................................................673
18.3.6.4.7 Payload Pointer.................................................................................................673
18.3.6.4.8 Status.................................................................................................................673
18.3.6.4.9 Payload..............................................................................................................675
18.3.7 Programming DCP Functions......................................................................................................................676
18.3.7.1 Basic Memory Copy Programming Example..........................................................................676
18.3.7.2 Basic Hash Operation Programming Example........................................................................677
18.3.7.3 Basic Cipher Operation Programming Example......................................................................679
18.3.7.4 Multi-Buffer Scatter/Gather Cipher and Hash Operation Programming Example..................680
18.4 DCP Memory Map/Register Definition........................................................................................................................683
18.4.1 DCP Control Register 0 (DCP_CTRL)........................................................................................................684
18.4.2 DCP Status Register (DCP_STAT).............................................................................................................687
18.4.3 DCP Channel Control Register (DCP_CHANNELCTRL).........................................................................689
18.4.4 DCP Capability 0 Register (DCP_CAPABILITY0)....................................................................................691
18.4.5 DCP Capability 1 Register (DCP_CAPABILITY1)....................................................................................692
18.4.6 DCP Context Buffer Pointer (DCP_CONTEXT)........................................................................................693
18.4.7 DCP Key Index (DCP_KEY)......................................................................................................................693
18.4.8 DCP Key Data (DCP_KEYDATA).............................................................................................................694
18.4.9 DCP Work Packet 0 Status Register (DCP_PACKET0).............................................................................695
18.4.10 DCP Work Packet 1 Status Register (DCP_PACKET1).............................................................................695
18.4.11 DCP Work Packet 2 Status Register (DCP_PACKET2).............................................................................699
18.4.12 DCP Work Packet 3 Status Register (DCP_PACKET3).............................................................................700
18.4.13 DCP Work Packet 4 Status Register (DCP_PACKET4).............................................................................700
18.4.14 DCP Work Packet 5 Status Register (DCP_PACKET5).............................................................................701
18.4.15 DCP Work Packet 6 Status Register (DCP_PACKET6).............................................................................701
18.4.16 DCP Channel 0 Command Pointer Address Register (DCP_CH0CMDPTR)............................................702
18.4.17 DCP Channel 0 Semaphore Register (DCP_CH0SEMA)...........................................................................703
18.4.18 DCP Channel 0 Status Register (DCP_CH0STAT)....................................................................................704
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18.4.19 DCP Channel 0 Options Register (DCP_CH0OPTS)..................................................................................706
18.4.20 DCP Channel 1 Command Pointer Address Register (DCP_CH1CMDPTR)............................................707
18.4.21 DCP Channel 1 Semaphore Register (DCP_CH1SEMA)...........................................................................708
18.4.22 DCP Channel 1 Status Register (DCP_CH1STAT)....................................................................................709
18.4.23 DCP Channel 1 Options Register (DCP_CH1OPTS)..................................................................................711
18.4.24 DCP Channel 2 Command Pointer Address Register (DCP_CH2CMDPTR)............................................712
18.4.25 DCP Channel 2 Semaphore Register (DCP_CH2SEMA)...........................................................................713
18.4.26 DCP Channel 2 Status Register (DCP_CH2STAT)....................................................................................714
18.4.27 DCP Channel 2 Options Register (DCP_CH2OPTS)..................................................................................716
18.4.28 DCP Channel 3 Command Pointer Address Register (DCP_CH3CMDPTR)............................................717
18.4.29 DCP Channel 3 Semaphore Register (DCP_CH3SEMA)...........................................................................718
18.4.30 DCP Channel 3 Status Register (DCP_CH3STAT)....................................................................................719
18.4.31 DCP Channel 3 Options Register (DCP_CH3OPTS)..................................................................................721
18.4.32 DCP Debug Select Register (DCP_DBGSELECT).....................................................................................721
18.4.33 DCP Debug Data Register (DCP_DBGDATA)..........................................................................................722
18.4.34 DCP Page Table Register (DCP_PAGETABLE)........................................................................................722
18.4.35 DCP Version Register (DCP_VERSION)...................................................................................................723
Chapter 19Enhanced Configurable SPI (ECSPI)
19.1 Overview.......................................................................................................................................................................725
19.1.1 Features........................................................................................................................................................726
19.1.2 Modes and Operations.................................................................................................................................726
19.2 External Signals............................................................................................................................................................727
19.3 Clocks...........................................................................................................................................................................730
19.4 Functional Description..................................................................................................................................................730
19.4.1 Master Mode................................................................................................................................................731
19.4.2 Slave Mode..................................................................................................................................................731
19.4.3 Low Power Modes.......................................................................................................................................732
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19.4.4 Operations....................................................................................................................................................732
19.4.4.1 Typical Master Mode...............................................................................................................732
19.4.4.1.1 Master Mode with SPI_RDY............................................................................733
19.4.4.1.2 Master Mode with Wait States..........................................................................735
19.4.4.1.3 Master Mode with SS_CTL[3:0] Control.........................................................735
19.4.4.1.4 Master Mode with Phase Control.....................................................................736
19.4.4.2 Typical Slave Mode.................................................................................................................737
19.4.5 Reset.............................................................................................................................................................738
19.4.6 Interrupts......................................................................................................................................................738
19.4.7 DMA ...........................................................................................................................................................739
19.4.8 Byte Order....................................................................................................................................................740
19.5 Initialization..................................................................................................................................................................741
19.6 Applications..................................................................................................................................................................741
19.7 ECSPI Memory Map/Register Definition.....................................................................................................................742
19.7.1 Receive Data Register (ECSPIx_RXDATA)...............................................................................................744
19.7.2 Transmit Data Register (ECSPIx_TXDATA)..............................................................................................745
19.7.3 Control Register (ECSPIx_CONREG)........................................................................................................745
19.7.4 Config Register (ECSPIx_CONFIGREG)...................................................................................................748
19.7.5 Interrupt Control Register (ECSPIx_INTREG)...........................................................................................750
19.7.6 DMA Control Register (ECSPIx_DMAREG).............................................................................................751
19.7.7 Status Register (ECSPIx_STATREG).........................................................................................................753
19.7.8 Sample Period Control Register (ECSPIx_PERIODREG)..........................................................................754
19.7.9 Test Control Register (ECSPIx_TESTREG)...............................................................................................756
19.7.10 Message Data Register (ECSPIx_MSGDATA)...........................................................................................757
Chapter 20External Interface Module (EIM)
20.1 Overview.......................................................................................................................................................................759
20.1.1 Features........................................................................................................................................................761
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20.1.2 Modes of Operation.....................................................................................................................................761
20.1.2.1 Asynchronous Mode................................................................................................................762
20.1.2.2 Asynchronous Page Read Mode..............................................................................................762
20.1.2.3 Multiplexed Address/Data Mode.............................................................................................762
20.1.2.4 Burst Clock Mode....................................................................................................................763
20.1.2.5 Low Power Modes...................................................................................................................764
20.1.2.6 Boot Mode...................................................................................................
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