This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
For the 56G and the forthcoming 112G PAM4 systems, it is no longer feasible to rely on SerDes
alone to transmit data through channels up to 30dB in insertion loss to achieve the desired BER. FEC becomes mandatory to work jointly with the SerDes to achieve the post-FEC BER better than
a designed target, e.g., 1e-15.
This paper starts with the less-adequate approaches adopted in the industry and with some standard
bodies today for FEC capability assessment. First, a large number of data based on the 28G generation KR4 FEC performance analysis and the lab test is presented to show that simply
specifying a pre-FEC BER is not enough for the FEC to help achieve the desired BER. Then a novel FEC post-processing method based on voltage bathtub curves is discussed. Recursive
models for both PAM4 DFE burst error probability and KP4-FEC BER estimation are derived and applied to some system link simulation examples. The methodology should help the industry to
gain better insight into the system BER requirement when FEC is applied.
Authors Biographies
Amanda (Xiaoqing) Dong joined Huawei Technologies in 2006 as a high speed serial link research
engineer. She has been working on high speed system link simulation and measurement technologies. She received her bachelor and master degrees in Communications and Information
System from Harbin Institute of Technology, China, for research in Information and Communication Engineering.
Nick (Chunxing) Huang is currently responsible for leading the development of High-frequency
Auto test equipment and solutions for Shenzhen Zhongzeling Electronics Co., Ltd. Prior to joining ZZL Electronics, he worked at Huawei Technologies from 2004 to 2013. He is responsible for
high speed end-to-end interconnection simulation and measurement techniques within High speed Interconnect Research Group. He received his Master degree in communications and information system from Nanjing University of Science &Technology in 2004.
Geoff (Geoffrey) Zhang received his Ph.D. in 1997 in microwave engineering and signal processing from Iowa State University, Ames, Iowa. He joined Xilinx Inc. in June, 2013. Geoff
is currently a Distinguished Engineer and Supervisor of Transceiver Architecture and Modeling Team, under SerDes Technology Group. Prior to joining Xilinx Geoff has employment
experiences with HiSilicon, Huawei Technologies, LSI, Agere Systems, Lucent Technologies, and Texas Instruments. His current interest is in transceiver architecture modeling and system level
end-to-end simulation, both electrical and optical.
1. Introduction
In 56Gbps PAM4 systems, FEC is mandatory to assure backplane transmissions with net BER
better than 1e-15. The standard bodies specified a pre-FEC BER (a.k.a. raw BER) in hope of the
post-FEC performance is guaranteed. However, FEC performance is strongly coupled with both
SerDes design and system topology such that any criterion without details of the system could be
inadequate, thus unreliable. For example, FEC system gain (SG) in compensating insertion loss
and in improving crosstalk tolerance behaves rather differently as will be clear in Section 2.
This paper introduces an engineering analysis method for more accurately predicting the FEC SG.
The method supports handling discriminately the impact from link insertion loss and from system
crosstalk, as well as the interactions between them. This is the key in terms of correctly assessing
FEC performance. After presenting the shortcomings of current approach, a testing method for
FEC SG is proposed based on the large amount of prior work in a 28G generation system. The
analysis shows that FEC SG from the insertion loss perspective is more limited than that from the
crosstalk tolerance perspective. Consequently, the effective pre-FEC BER for the same post-FEC
BER is different for the two mechanisms. Furthermore, the optimal TX FFE settings in terms of
lowest BER are different depending on whether FEC is applied. The underlying physics is
discussed and the method to simulate FEC SG is introduced.
A recursive analytical model for PAM4 FEC SG is presented. This recursive analysis algorithm
serves as the basis for quantifying PAM4 FEC SG. It supports a flexible multi-tap DFE error
propagation probability calculation for a PAM4 system where a single error could impact 2 bits;
the calculation depth for a single burst length is no less than 200 bits. Furthermore, the probability
of all possible symbol error patterns induced by burst errors in a single FEC frame is calculated.
This ensures that no error pattern is neglected. Algorithm optimization is performed to assure
calculation efficiency.
In practical engineering applications, where hundreds to thousands of backplane channels are
required for FEC SG analysis, the reference of “a given pre-FEC BER criteria will achieve a given
post-FEC BER target” is insufficient and could be many orders off. To solve this problem, a PAM4
FEC SG simulation method based on voltage bathtub curves is presented. The algorithm is based
on the DFE burst error probability recursive model for PAM4, and the Reed-Solomon (RS) FEC
BER performance recursive analysis for PAM4. Thus, the approach for FEC engineering SG is
quantified more accurately based on channel characteristics, simulated/measured DFE coefficients,
and voltage bathtub curves.
In summary, after highlighting the shortcoming of today’s approach in assessing FEC capability,
and after providing engineering application guidelines based on the KR4 FEC performance
analysis and test validation for the 28G generation system, a novel FEC post processing method
based on voltage bathtub curves is presented. Both recursive models for PAM4 DFE burst error
probability and RS FEC BER simulations are derived.
2. Issues with FEC Applications for 28Gbps NRZ
KR4 FEC, RS(528, 514, 7), adopted in IEEE 802.3bj, is able to improve link BER from 1e-5 to
<1e-12 for a compliant channel of up to 35dB. It has also been indicated that the KR4 FEC can
help the target compliant channel insertion loss increase from 30dB to 35dB at 12.89GHz,
providing 5dB insertion loss compensation capability can be safely achieved at the target BER.
However, the KR4 FEC capability strongly depends on the error distribution signatures of the
‘1e-5’ data stream before applying FEC, and depends on the assumption of pre-FEC “link
performance linearity”, which means for example, if 30-35dB already falls outside a SerDes
linear compensation region, the 5dB gain in channel insertion loss would prove too optimistic.
The basic idea is illustrated in Figure 1.
Figure 1. “Linearity” curve illustration for link performance.
Even assuming the above FEC gain can be obtained, we are still facing two problems for a
practical system design, which will be analyzed in more details below.
What is the necessary pre-FEC BER when the target post-FEC BER is more stringent than
1e-12 for a practical backplane system? A backplane system typically is self-defined for a
system house, thus the single lane BER target is not necessarily equal to the definition in
802.3bj standard, because many factors are involved, such as the number of channels in a
system, data packet drop rate requirement, etc. On the other hand, determining pre-FEC BER
is important for link system end-to-end simulations as well as the evaluation of a SerDes
driving capability for both 28Gbps NRZ system and 56Gbps PAM4 system.
FEC engineering SG also depends on the link error signatures, which is related to the
characteristics of the link system. At a given targeted BER, will the FEC SG from insertion
loss compensation capability and from crosstalk immunity be equivalent? The answer is key
to the evaluation of a link system for achieving maximal FEC SG performance.
2.1 FEC System Gain Test for 28Gbps Systems
To address the above questions we set up a system evaluation test bench for a 28Gbps link, as
shown in Figure 2. The post-FEC BER is set to 1e-15; for confidence level >63% it requires a
test time of longer than 10.8 hours (11 hours). Other test conditions include:
30dB 35dB
1E-12
1E-05
IL
Pre-FEC raw BER Order
0
?
SerDes IP from Company A, running at 25.78125Gbps, with PRBS31 data pattern, NRZ
Single lane RS(528, 514) implemented in FPGA (not 4-lane combined FEC defined in KR4)
Link section ① and ② are ensured to be error free in the whole FEC test process
SerDes TX FFE is manually tuned through the Green-Box sweep when FEC is off
BER target: 1e-15 (only 11 hour error-free test is acceptable for this evaluation)
Figure 2. 28G NRZ FEC performance test setup.
It is hoped that, with this test, we shall be able to address the following: for the given post-FEC
BER, if the required pre-FEC BER is more stringent than the standard for different link
impairment factors, specifically for the impact of link insertion loss and of system crosstalk,
which are recognized to be two major impairments of a link system.
Figure 3. The s-parameter representation of the test setup.
IL profile XTK PSXT profile
Link type A
Link type B
Link type C
Two test cases are designed:
(1) Insertion loss enhancement from FEC under certain BER and certain crosstalk target;
(2) Crosstalk tolerance enhancement from FEC under certain BER and insertion loss target.
The link system contains 3 insertion loss and crosstalk profiles. Link impedance mismatches are
controlled within +/-10%. The s-parameter representation of the test setup is shown in Figure 3.
The test results under the above conditions are summarized in Table 1.
Table 1. Input BER test under various conditions.
Note1: For the given test time, the BER after applying FEC should be in the order of 1e-15.
Note2: The input BER is defined as the ratio of the total number of erred bits over the total
number of bits in the same time period; this represents the pre-FEC BER.
Note3: “Stress in IL (or in XTK)” means to stress the link by increasing insertion loss (or
crosstalk) while keeping link crosstalk (or insertion loss) unchanged until link loss (or crosstalk)
reaches a status that uncorrectable errors will occur if increase the stress factor by one more step.
Now, why do we see in some cases the input BER is in the order of 1e-9/-10, while others in the
order of 1e-5/-6? In the test, if the insertion loss or crosstalk is increased, the post-FEC BER
cannot meet the error free requirement within 11 hours.
The following observations can be made from the SerDes RX status summarized in Table 2
It is seen that for the samples whose input BER around 1e-9/-10, the DFE first tap, H1, has
much bigger values than that when the input BER is around 1e-6. This is also true for the
absolute sum of all the DFE tap coefficients.
The average positive/negative signal amplitude (hsA) remains almost the same for both the 1e-
9/-10 and the 1e-6 samples.
Inner eye height (zpk) is not very stable, but remains almost the same for both test cases.
Compared to the 1e-6 samples, probability of random error induced bursts for the 1e-9/-10
samples should be much larger for this subset.
TxFFE Ball to ball loss Link Xtalk Pre FEC BER Test time
1 Link type B: Stress in IL 0d240f 46.6dB 0 3.70E-09 19h0
2 Link type B: Stress in IL 0d250e 42.82dB 0.363mVrms 3.40E-09 12h30min0
3 Link type A: Stress in IL 0c2311 47.34dB 0 1.70E-09 15h0
4 Link type A: Stress in IL 0c250f 42.79dB 0.633mVrms 2.20E-10 11h0
5 Link type A: Stress in IL 0c270d 41.48dB 0.633mVrms 8.60E-09 15h0
6 Link type C: Stress in XTK no FFE 16.4dB 12.954mVrms 1.50E-09 12h0
7 Link type B: Stress in XTK 0d240f 39.8dB 1.678mVrms 4.10E-06 15h0
8 Link type A: Stress in XTK 0c260e 35.1dB 3.174mVrms 1.30E-06 12h30min0
9 Link type A: Stress in IL 0c2113 46.6dB 0.633mVrms 9.00E-07 16h0
10 Link type C: Stress in XTK 0b2411 29.4dB 4.471mVrms 6.50E-06 15h0
11 Link type C: Stress in XTK 0b2312 31.8dB 3.639mVrms 1.40E-05 11h20min0
12 Link type C: Stress in XTK 0b2213 33.4dB 2.901mVrms 2.40E-06 12h0
13 Link type C: Stress in XTK 0b2213 34.2dB 2.749mVrms 3.60E-06 11h0
Table 2. SerDes RX equalization status.
Comparing two samples 4 and 9, whose input BER is 1e-10 and 1e-6, separately, Sample 4
(input BER=1e-10) and Sample 9 (input BER=1e-6) actually used the same passive link type
(Type A); the only difference is with the TX FFE settings. Further analysis, shown in Figure 4
(horizontal axis: consecutive error length before FEC; vertical axis: the proportion of certain
length error to the total error numbers in 11 hours, before FEC), showed that the probability of
consecutive errors for the 1e-10 sample is higher than that for the 1e-6 sample, while the single
bit error probability of the 1e-6 sample is slightly higher.
Figure 4. Link type-A samples: pre-FEC error statistics in 10 hours.
2.2 The Cause of FEC Gain Difference for 28Gbps Systems
It can be summarized over the above 13 tested samples that there exist two cases:
Case 1:With fixed amount of crosstalk while gradually increasing channel loss such as the
post-FEC BER reaches 1e-15, the pre-FEC BER is on the order of 1e-9/-10;
Case 2: With fixed amount of insertion loss while gradually increasing the crosstalk amount
until post-FEC BER reaches 1e-15, the pre-FEC BER is on the order of 1e-6.
TxFFE Pre FEC BER H1 H2 H3 H4 H5 sumH hsA zpk zpk/hsA
1 Link type B: Stress in IL 0d240f 3.70E-09 -0.48~-0.36 0.04~0.09 -0.09~-0.04 -0.14~-0.10 -0.12~-0.1 1.32~1.67 23~25 11~16 0.46~0.70
2 Link type B: Stress in IL 0d250e 3.40E-09 -0.35~-0.25 0.07~0.12 -0.08~-0.04 -0.12~-0.10 -0.10~-0.07 1.12~1.33 26~29 12~17 0.43~0.63
3 Link type A: Stress in IL 0c2311 1.70E-09 -0.53~-0.38 0.10~0.20 -0.05~0 -0.12~-0.11 -0.11~-0.08 1.27~1.59 19~21 10~13 0.48~0.67
4 Link type A: Stress in IL 0c250f 2.20E-10 -0.50~-0.40 0.03~0.1 -0.10~-0.06 -0.14~-0.11 -0.12~-0.08 1.36~1.57 29~31 14~20 0.47~0.68
5 Link type A: Stress in IL 0c270d 8.60E-09 -0.62~-0.49 0~0.03 -0.14~-0.09 -0.16~-0.12 -0.14~-0.10 1.53~1.87 33~36 17~23 0.49~0.66
6 Link type C: Stress in XTK no FFE 1.50E-09 -0.53~-0.42 -0.02~0.04 -0.13~-0.08 -0.12~-0.08 -0.10~-0.06 1.07~1.30 47~50 17~25 0.35~0.53
7 Link type B: Stress in XTK 0d240f 4.10E-06 -0.25~-0.15 0.11~0.18 -0.09~-0.03 -0.10~-0.07 -0.08~-0.06 0.84~1.12 32~34 12~19 0.36~0.62
8 Link type A: Stress in XTK 0c260e 1.30E-06 -0.20~-0.12 0.10~0.14 -0.10~-0.06 -0.10~-0.08 -0.07~-0.05 0.79~0.99 49~51 23~31 0.45~0.62
9 Link type A: Stress in IL 0c2113 9.00E-07 -0.24~-0.11 0.26~0.39 0.05~0.12 -0.07~-0.03 -0.03~0 0.74~1.07 17~20 6~12 0.33~0.65
10 Link type C: Stress in XTK 0b2411 6.50E-06 -0.38~-0.24 0.06~0.12 -0.09~-0.03 -0.10~-0.08 -0.08~-0.06 0.96~1.19 32~35 11~20 0.33~0.61
11 Link type C: Stress in XTK 0b2312 1.40E-05 -0.26~-0.14 0.10~0.15 -0.07~-0.03 -0.08~-0.06 -0.06~-0.04 0.80~1.02 27~29 9~16 0.32~0.61
12 Link type C: Stress in XTK 0b2213 2.40E-06 -0.22~-0.12 0.16~0.22 -0.04~0 -0.06~-0.03 -0.03~-0.02 0.63~0.84 23~27 10~15 0.38~0.62
13 Link type C: Stress in XTK 0b2213 3.60E-06 -0.25~-0.13 0.16~0.23 -0.05~0.04 -0.06~-0.03 -0.05~-0.01 0.69~0.89 22~25 8~14 0.35~0.61
This can largely be explained, with the help of DFE coefficients and inner eye height parameters hsA and zpk. For case 1: Increasing channel insertion loss will ask for the increase of DFE tap
coefficients to compensate for the increased ISI. When the insertion loss reaches a certain level (the equalizer capability boundary), data dependent ISI caused error becomes dominant. This is
especially true when testing with PRBS pattern so the errors are more deterministic. This kind of errors (and the induced burst errors) are more prone to exceed FEC correction capability. Unless
something is done to enhance the SerDes capability, FEC can hardly reach the post-FEC BER requirement in this case.
For case 2:A medium loss channel is used. The pre-FEC BER can be around 1e-6 with
increased crosstalk. This is true because of the following reasons: (1) When crosstalk is increased to a certain level, the errors are caused more due to crosstalk. For a real system
typically containing at least 5-8 crosstalk aggressors, the crosstalk impact can be treated as random, as shown in Figure 5. (2) When the insertion loss is within the SerDes equalization
range, increasing crosstalk will not increase DFE tap weights; thus, error propagation probability is relatively small. (3) When random errors occur relatively uniformly and burst errors occur
with relatively low probability, the pre-FEC BER at 1e-6 suffices for the post-FEC BER of 1e-15. This is in agreement with assumption in the theoretical analysis.
Figure 5. Crosstalk noise pdf that approaches Gaussian.
2.3 Further Analysis for FEC SG
In the above test and analysis the FEC BER performance is studied when the link is stressed from insertion loss and from system crosstalk. Now, for a practical system, the insertion loss is
around 30dB at the Nyquist frequency and the crosstalk amount is reasonably well controlled, it is not straightforward to distinguish the dominant factor for error, insertion loss or crosstalk.
However, one thing for sure is that in order for the FEC to achieve good error correction capability, insertion loss has to be paid attention to.
For 28Gbps NRZ systems, it is workable to test FEC SG in terms of insertion loss compensation and crosstalk tolerance capabilities perspectives, under the same BER target, with and without
FEC, for further address of the above analysis.
1. FEC SG – Relatively Small DFE Coefficients
The channel insertion loss gain for the given crosstalk amount is shown in Figure 6. The pre-FEC BER is less than 1e-9. The insertion loss gain is between 5.10dB and 6.43dB. The pre-FEC
BER signature shows mostly single bit errors, burst errors occur rarely. The crosstalk amount
gain for the given insertion loss is shown in Figure7. In general, pre-FEC BER is on the order of 1e-6; the crosstalk amount gain for the three types of channels is around 1.50~2.26mVrms. An
example of error signature is recorded and shown in Figure 8.
Figure 6. Insertion loss gain for given crosstalk. Figure7. Crosstalk gain for given insertion loss.
Figure 8. Error signature example.
2. FEC SG – Relatively Large DFE Coefficients (1)
For the given crosstalk, the insertion loss gain is shown in Figure 9. For pre-FEC BER around
1e-9/-10 the insertion loss gain for the test channel is around 4~4.9dB. Concurrently, the raw
BER signature took obvious changes: single errors became less while burst errors become more,
which can be seen in Figure 10.
Figure 9. insertion loss gain vs. crosstalk. Figure 10. Pre-FEC error signatures
Figure 11 shows crosstalk handling capability for given channel losses. The pre-FEC BER is on the order of 1e-7. The crosstalk gain for the three types of channels is around 1~1.7mVrms.
Figure 11. Insertion loss vs. crosstalk for relatively large DFE coefficients (setup 1).
3. FEC SG – Relatively Large DFE Coefficients (2)
Figure 12 shows the link performance gain under the same link conditions while TX FFE values
are re-optimized. With FEC enabled, the increased TX FFE post-cursor leads to reduced DFE tap
weights, the link performance is obviously improved (the green curve). Still, when the link
channel makes the SerDes work close to its equalization limit, the FEC gain is reduced.
Henceforth, it is ultimately important to identify the SerDes “safe zone” for a given link system
in order to take full advantage of the FEC capability.
Figure 12. Insertion loss vs. crosstalk for relatively large DFE coefficients (setup 2).
In Section 2.3, for the above test cases where FEC is disabled, test channel insertion loss and
crosstalk are controlled in a range that representing a practical link system working conditions.
From the above test data, we can see that for such kind of practical link system conditions,
insertion loss is still constraining FEC SG compared to crosstalk.
For 56G PAM4 systems, it is unrealistic to achieve BER 1e-15 without FEC in backplane links.
Still, similar experiments show that, pre-FEC BER deteriorates faster if stressing the channel
from insertion loss perspective than to stress the channel from crosstalk perspective. FEC SG is
still more constrained by channel insertion loss for 56G PAM4 systems.
2.4 FEC SG Summary
FEC is playing an ever bigger role for link systems at and beyond 25Gbps. FEC serves as a
complement to the SerDes, and together they deliver the required link performance. A summary
is provided below from the work introduced above.
(1) Error signatures for most high speed links show a combination of uniformly occurred and
concentrated errors before FEC, especially in ISI dominated systems, which would provide
less coding gain than the standard specifies. Furthermore, FEC performance is strongly
coupled with the SerDes working conditions, which must be an integral part of the FEC
capability analysis. By the same token, SerDes with different architectures may cause the
same FEC to deliver different levels of performance.
(2) The channel insertion loss gain by FEC strongly depends on SerDes capability. In a
practical application, FEC performance for insertion loss gain would compromise when the
SerDes works close to the equalization limit, i.e., the “nonlinear zone”. Thus, understanding
the SerDes capability and its “safe working zone” will allow the system engineers accurately
estimate the FEC SG. Also, when SerDes DFE coefficients are considered too large (when it
is beyond 0.5-0.75 for NRZ with respect to the main peak value), channel insertion loss gain
by FEC is also compromised. Allowing DFE to do more work is surely a double edged
sword. On the one hand, the increased DFE tap weights will increase channel equalization
capability for more insertion loss and reflections. On the other, this practice will sacrifice the
FEC performance. To balance the two requires careful considerations in link system
budgeting analysis.
(3) For a given link channel and SerDes IP, the following is suggested in order to maximize
FEC performance. 1) Identifying optimal TX FFE coefficients with FEC enabled, using
Green-Box or equivalent method, rather than identifying the TX FFE then let FEC work
with the same TX FFE coefficients. 2) For the conventional NRZ RX equalization
architecture, CTLE plus multi-tap DFE, slightly more TX post-cursor is preferred. Doing so
will help randomize error distribution as well as reduce DFE tap coefficients, to achieve
better FEC link performances.
3. Simulation model for FEC System Gain Analysis
For assessing FEC SG in terms of enhancing BER performance or improving link insertion loss
compensation or crosstalk tolerance capabilities under target post-FEC BER, a recursive
analytical model for PAM4 FEC SG is discussed in this section. A PAM4 FEC SG simulation
method based on voltage bathtub curves is presented with an IBIS-AMI simulation example.
3.1 Analytical Model for a Single Burst Error
Typically, a high speed link has both random and burst errors. DFE is one of the key contributors
to the burst portion of the error. Theoretically, for a NRZ system, once a single random error
takes place, there is a maximal 50% chance that the following bit is also wrong. The process
could continue for many bits, which creates error propagations. As shown in Figure 13, the DFE
output is based on the previous M bits, where M is the number of taps in a DFE. If any of the
previous M bit is wrong, the current bit will be affected, increasing its error probability.
(1)
Figure 13. A simplified DFE model.
Figure 14. Error voltage introduce in the DFE feedback for NRZ.
DFE feedback error is illustrated in Figure 14. The error voltage from tap i is 2xDFE(i). Both the
number of errors and the error locations will affect the decision correctness of the current bit. For
M DFE registers, there exist 2^M combinations. Each combination represents a certain
probability for inducing error voltage to the current bit. The error voltage varies with each
combination. This is represented in the equation below.
)_(P
0Verr(i) else DFE(i)]*[2Verr(i) error bit ith when
)(]|_[
Bathtubj
1
j
M
ijj
errVsumP
iVerrPerrVsum
(2)
Where, athtubBP is the probability from the voltage bathtub and Vsum_err has 2^M possible
values. DFE error propagation is illustrated in Figure 15.
Figure 15. DFE error propagation.
The burst error probability can be expressed as [1]
rllmax2 for bits), of error (burst))(( iipiEWp (3)
When rll = n-1 burst error probability is known, the error probability for rll = n can be
computed in a recursive manner:
)11bit_pad( )1ones(
)11bit_pad( )1(_
:M-K,
:M-K,zerospadbit
)11bit_pad( )1ones(_ :M-K,patternbit
Where, )1,(Kzeros and )1,(Kones are vectors, representing the error status of the newly
came-in bit to the length of M. K is the number of rows in the bit_pattern matrix. padbit _
is used to store the Bit Error Patterns in DFE loopback registers. Its length is always equal to
M, the length of the DFE.
Based on the Bit Error Pattern of DFE loopback registers stored in padbit _ , we can
calculate the DFE error feedback voltage according to DFE coefficients, and get the n-th bit
error occurrence probability nPe through looking up the voltage bathtub curve. Then, under
the condition that n-th bit error has occurred, we calculate the probability that no further burst
error occurs in the following M bits,
1
1i
)1(M
rlliPe . For the probability rlliPe that
representing each bit is erred in the following M bits, we also need to get DFE error feedback
voltage according to DFE coefficients and bit error pattern stored in patternbit _ , and look
up the voltage bathtub curve to get rlliPe . In this way, we can obtain the probability that no
error has occurred in the following M bits, rlliPe -1 .
Burst error probability with rll = n is calculated, according to the following equation:
M
i
rllMNrllin PenstackPPePeWeightsumnrllp
11)1(*)1(_*)1(*)1(()(
Where, stackP _ is used to store the probability of all bit error patterns when rll equals to n-
1, and to serve as recursive calculation matrix.
)1(_
)1(_)1()(_
1-n
1-n
nstackPPe
nstackPPenstackP
3.2 Assumptions for Multi-Level Signaling Error Recursive Modeling
In order to make the recursive error model applicable to PAM4, while keeping the computation
reasonably manageable, the following assumptions are made:
1. If two bit errors in an error pattern are separated by more than the order of DFE, M,
without any errors in between, as shown in Figure 16, the two bit errors are treated as
independent events.
Figure 16. The distance between 2 bit errors is larger than M.
2. We can reasonably assume that errors only occur between neighboring levels, i.e., “skip
level” type of errors can be ignored. Thus, for PAM4, errors only occur between levels
{1, 1/3}, {1/3, -1/3}, and {-1/3, -1}. Error voltage is also restricted to 2/3 of the DFE
coefficients. That is to say that the error voltage coefficient is 2/3, not 2 as in NRZ case.
Figure 17. Error probability for PAM4 levels.
3. Gray coding, as specified by all relevant standards, is adopted. Thus, only one bit error
for every symbol error.
4. Single burst calculation length of at least 200 bits should be considered, given that the
correctable symbol number reaches 15 for RS(544, 514). Thus, 150 bits can be corrected,
shorter length in single burst error probability calculation could lead to big deviation in
the post-FEC BER results. Figure 18 shows one example of single burst error
probabilities under different burst length, up to 200bits.
Figure 18. Probability of burst error length (12-tap DFE).
3.3 Computation Model for Symbol Error Probability in a FEC block
Above we discussed the analytical model for PAM4 single burst error. However, the RS FEC
uses the symbol as a unit to correct the error bits. We need to translate the location of single burst
errors, burst length and its probabilities into the corresponding symbol error ratio (SER).