Implementing MATLAB and Simulink Algorithms on FPGAs · Automotive Biotech and ... LTE physical layer, verify the FPGA implementation, and analyze test results Results Internal test
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10:00 Reduce FPGA Development Time with Model-Based Designp g
11:00 Break
11:15 Integrated HDL Verification
12:00 Xilinx Target-optimized FPGA Design Using MATLAB and Simulink
13:15 Lunch
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13:15 Lunch
14:15 FPGA Design Optimization Techniques
15:45 Q&A, Summary and Wrap-up
9/21/2011
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Introducing The Speakers
Xilinx:
Daniele Bagni Daniele BagniDSP Specialist EMEA
MathWorks:
Stefano OlvieriSenior Application Engineer
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Signal Processing and Communication
Marco VisintiniSales Account Manager
MathWorks and Xilinx Goals
MathWorks: accelerate the pace of engineering and science by providing best in class Software for:
De elopment and erification of algorithms and control logic– Development and verification of algorithms and control logic
– Embedded Systems implementation
Xilinx: providing best in class Silicon including FPGAs and embedded system hardware platforms :– Offers FPGAs and Zynq – an Extensible Processing Platform
P t ith M thW k t id i t t d kfl
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– Partner with MathWorks to provide an integrated workflow
Purpose of the joint seminar: – to demonstrate a Model-Based Design workflow for FPGAs -
from first idea down to the Hardware.
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MathWorks at a Glance
Headquarters:N ti k M h tt USNatick, Massachusetts US
Other US Locations: California, Michigan, Texas, Washington DC
Europe:France, Germany, Italy, Spain, the Netherlands, Sweden, Switzerland, UK
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Asia-Pacific:Australia, China, India,Japan, Korea
Worldwide trainingand consulting
Distributors in 25 countries
Earth’s topography on an equidistant cylindrical projection,
created with MATLAB and Mapping Toolbox.
MathWorks Today
Revenues ~$600M in 2010
Privately held Privately held
More than 2000 employees worldwide
Worldwide revenue balance:45% North America, 55% international
More than 1 million users in 175+ countries
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1984 1989 1994 1999 2004 2009
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Key Industries
Aerospace and Defense
Automotive
Biotech and Pharmaceutical
Communications
Education
Electronics and Semiconductors
Energy Production
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Financial Services
Industrial Automation andMachinery
Who is Who???
Who is a System Engineer?
Wh i FPGA d i ? Who is an FPGA designers ?
Who is using MATLAB?
Who is using Simulink?
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9/21/2011
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Your Expectations Beyond the Agenda...
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Corner Detection in Video Mosaicking(A Brief Example)
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Use Model-Based Design to provide an integrated workflow
Things to remember ….
DESIGN
Speed up algorithm development with a unified design environment
Automate manual steps in FPGA implementation to enableshorter iteration cycles
AlgorithmDevelopment
MATLABSimulinkStateflow
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y
Integrate FPGA development tools to reduce verification time
Agenda
9:45 Welcome
10:00 Reduce FPGA Development Time with Model-Based Designp g
11:00 Break
11:15 Integrated HDL Verification
12:00 Xilinx Target-optimized FPGA Design Using MATLAB and Simulink
13:15 Lunch
15
13:15 Lunch
14:15 FPGA Design Optimization Techniques
15:45 Q&A, Summary and Wrap-up
9/21/2011
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Memory
Customized interfaces to peripherals
Memory
We are going to focus on
Why do we use FPGAs?
Analog I/O
Digital I/O
ARM
Bridge
MemoryMemory
Memory High-speed communication
interfaces to other processors
Finite state machines, digital logic, timing and memory control
FPGAAnalog I/O
Digital I/O
ARM
Bridge
MemoryMemory
Memoryto focus on this use case today
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DSP
High speed, highly parallel DSP Algorithms or Control Algorithms
DSPAlgorithms
FPGA DesignerSystem Designer
Algorithm Design System Test Bench RTL Design Verification
Separate Views of DSP Implementation
Algorithm Design
Fixed-Point
Timing / Control Logic
Architecture Exploration
Algorithms / IP
System Test Bench
Environment Models
Algorithms / IP
Analog Models
Digital Models
RTL Design
IP Interfaces
HW Architecture
Verification
Functional Simulation
Static Timing Analysis
Timing Simulation
Behavioral Simulation
Back AnnotationImplement Design
Map
SynthesisFPGA Requirements
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Map
Place & Route FPGA HardwareHardware Specification
Test Stimulus
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Where do you spend most of your time?
Simulating designs?
Creating designs and test benches?
Algorithm Design System Test Bench
System Designer
Analyzing and combining results from multiple tools?
Exploring implementation ideas and architectures?
Floating point to fixed-point?
Writing HW specifications?
Algorithm Design
Fixed-Point
Timing / Control Logic
Architecture Exploration
Algorithms / IP
System Test Bench
Environment Models
Algorithms / IP
Analog Models
Digital Models
FPGA Requirements
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Iterating over designs with the FPGA designer?
Blaming the FPGA designer?
Hardware Specification
Test Stimulus
FPGA Designer
Where do you spend most of your time?
Simulating designs and validating against HW specs?
Creating designs and writing test RTL Design Verification
benches?
Hardware architecture design?
Writing interfaces to existing IP?
Synthesis, Map, PAR cycles?
Iterating over designs with the system designer?
RTL Design
IP Interfaces
Hardware Architecture
Verification
Functional Simulation
Static Timing Analysis
Timing Simulation
Behavioral Simulation
Back AnnotationImplement Design
Map
Synthesis
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system designer?
Blaming the system designer?
ap
Place & Route FPGA Hardware
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1. Increase simulation speed
2. Simplify design entry, system test harness
A Few Ways to Reduce Development Time
creation, and exploration
3. Shorter iteration cycles required for RTL design & verification
4. Integrate the separate workflows to facilitate collaboration, re-use, and prototyping
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Model-Based Design for Implementation
Algorithm Design System Test Bench RTL Design Verification
MATLABMATLAB® ® andand SimulinkSimulink®®
Algorithm and System DesignAlgorithm and System Design
Algorithm Design
Fixed-Point
Timing / Control Logic
Architecture Exploration
Algorithms / IP
System Test Bench
Environment Models
Algorithms / IP
Analog Models
Digital Models
RTL Design
IP Interfaces
Hardware Architecture
Verification
Functional Simulation
Static Timing Analysis
Timing Simulation
Behavioral Simulation
Back AnnotationImplement Design
Map
SynthesisFPGA Requirements
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Map
Place & Route FPGA HardwareHardware Specification
Test Stimulus
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MATLABMATLAB® ® andand SimulinkSimulink®®
Algorithm and System DesignAlgorithm and System DesignModel Refinement for HardwareModel Refinement for Hardware
Flexible Design EnvironmentDesign, Simulation and Implementation
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Choice of best modeling methods (Simulink, MATLAB and Stateflow)
Integrate with MATLAB Algorithm Design
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Fixed Point AnalysisCorner Detection
Convert floating point to optimized fixed point models– Automatic tracking of signal range (also intermediate quantities)Automatic tracking of signal range (also intermediate quantities)
– Word / Fraction lengths recommendation
Bit-true models in the same environment
Automatically identify and solve fixed point issues
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Automatic HDL Code GenerationCorner Detection
Full bi-directional traceability!!
Automatically generate bit true, cycle accurate HDL code from
Simulink, MATLAB and Stateflow
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Requirements
traceability!!
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Simulink Library Support for HDLHDL Supported Blocks
170 blocks supported
Core Simulink Blocks– Basic and Array Arithmetic, Look-Up Tables,
Signal Routing (Mux/Demux, Delays, Selectors), Logic & Bit Operations, Dual and single port RAMs, FIFOs, CORDICs
Signal Processing Blocks– NCOs, FFTs, Digital Filters (FIR, IIR, Multi-
10:00 Reduce FPGA Development Time with Model-Based Designp g
11:00 Break
11:15 Integrated HDL Verification
12:00 Xilinx Target-optimized FPGA Design Using MATLAB and Simulink
13:15 Lunch
91
13:15 Lunch
14:15 FPGA Design Optimization Techniques
15:45 Q&A, Summary and Wrap-up
9/21/2011
43
Agenda
9:45 Welcome
10:00 Reduce FPGA Development Time with Model-Based Designp g
11:00 Break
11:15 Integrated HDL Verification
12:00 Xilinx Target-optimized FPGA Design Using MATLAB and Simulink
13:15 Lunch
92
13:15 Lunch
14:15 FPGA Design Optimization Techniques
15:45 Q&A, Summary and Wrap-up
Agenda
9:45 Welcome
10:00 Reduce FPGA Development Time with Model-Based Designp g
11:00 Break
11:15 Integrated HDL Verification
12:00 Xilinx Target-optimized FPGA Design Using MATLAB and Simulink
13:15 Lunch
93
13:15 Lunch
14:15 FPGA Design Optimization Techniques
15:45 Q&A, Summary and Wrap-up
9/21/2011
44
Use Model-Based Design to provide an integrated workflow
Things to remember ….
DESIGN
Speed up algorithm development with a unified design environment
Automate manual steps in FPGA implementation to enableshorter iteration cycles
AlgorithmDevelopment
MATLABSimulinkStateflow
94
y
Integrate FPGA development tools to reduce verification time
Shorter implementation time by 48% (total project 33%)
Reduced FPGA prototype development schedule by 47%
ROI: Customer Adoption Of Model-Based DesignTime spent on FPGA/ASIC implementation
Shorter design iteration cycle by 80%
1st FPGA Prototype 2nd FPGA Prototype
1st FPGA Prototype
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How to adopt MathWorks technologies?
MathWorks tools provide a technology to speed up p gy p pdevelopment
MathWorks services provide the support to roll out this technology in your organization
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Example MathWorks Services
MathWorks Training– Private training “Simulink HDL Coder”
– Public training “Signal Processing with MATLAB/Simulink”Public training Signal Processing with MATLAB/SimulinkFundamental trainings for uniform knowledge, quick ramp up
MathWorks Consulting – Jumpstart service to get you up and running quickly with
Simulink HDL Coder
– Advisory service for ongoing expert advice during technology adoption
– Based on industry experience, assistance with tailoring workflow
On site expert customization / optimization of your workflow
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– On site expert customization / optimization of your workflow
Technical Support– Comprehensive, product-specific Web support resources
– 70% cases solved within 24 hours
– Included in Software Maintenance Service
9/21/2011
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Were Your Expectations Met?
Please complete and return seminar survey forms
Your comments and feedback are very important to us
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1. Visit www.mathworks.com/fpga
Next Steps …
pgfor more information
2. Visit www.xilinx.com/dspfor more information
3. Watch our FPGA webinars:
th k / / t / bi
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– www.mathworks.com/company/events/webinars
4. Contact your local sales reps for a trial of our FPGA tools