Implementing Digital Signal Processing Algorithms in Actel’s RT54SX-S Family

Ken Stevens 1 MAPLD 2005 / Poster Session #158

Ken Stevens

Laboratory for Atmospheric and Space Physics

University of Colorado, Boulder

MAPLD 2005 Presentation

Implementing Digital Signal Processing Algorithms in Actel’s

RT54SX-S Family


Background• FPGAs allow the designer to optimize between performance and power by

precisely tailoring the processing logic to mission requirements. This is especially true when implementing custom DSP functions.

• The tool flow for Actel’s RT54SX-S family does not inherently support translation from a high-level analysis tool to gate-level implementation.

• To provide reasonable algorithm performance with the resources available in the RT54SX-S family often requires a highly-optimized VHDL-based implementation.

• As designs provide more functionality, significant attention must be devoted to expedient verification of the algorithms in addition to the emphasis on VHDL coding style, board-level issues, etc.

Problem Statement• Given the combination of advantages and constraints described above, a

methodology that effectively combines the use of a high-level analysis tool for algorithm characterization and refinement with VHDL simulation and in-circuit testing of the FPGA logic implementation is essential. This presentation describes such a methodology that was used to successfully develop the FPGA-based digital signal processing functions on NASA’s THEMIS project.

Problem Definition


Search CoilMagnetometer

(SCM)

Sphere Voltagesfrom Radial andAxial Booms (V)

AnalogFiltering

andSelection

Analog toDigital

Conversion

Digital SignalProcessingFPGA Logic

Digital Fields Board

DigitalControlBoard

Flux-GateMagnetometer (B)

Commands

Telemetry

• Functions Required– Digital Filtering– Vector Rotations to Align Instrument Coordinate Systems– Extraction of parallel & perpendicular signal components– Spectral Analysis using Fourier Transform

THEMIS Project Background


Spin-fit Filters- V1, V2, V3, V4,E12, E34, E56- 50 Hz Filter- 128 S/s output

Efit (ID80)

FB #1 (6 bands)

Vfit (ID80)

VAFS (ID65)VBFS (ID66)

EFS (ID67)SCMFS (ID68)

VAPB (ID69)VBPB (ID70)

EPB (ID71)SCMPB (ID72)

VAWB (ID73)VBWB (ID74)EWB (ID75)

SCMWB (ID76)

Analog Selection

Normal mode- 8kS/s to ADC #1- 16kS/s to ADC #2

ADC #1 only mode- All to ADC #1

ADC #2 only mode- All to ADC #2

8kS/s AnalogQuantitiesV1, V2, V3,V4, V5, V6,E12DC, E34DC,E56DC, SCM1,SCM2, SCM3,E12HF

ADC #1128kS/s

ADC #2128kS/s

SignalRouting256kS/s

Filter Banks- Any two inputsexcept E12HF- 11 frequencies- output from 1/16to 16 S/s

E12HF Processing- Peak Detect- Average

8-bit Psuedo-logCompressor

19 bits 8 bits

DerivedQuantities- ExB- EdotB- SCMxB- SCMdotB

Fast Survey Filters- All V, E, SCM- 0.8 - 100 Hz Filter- 2 -256 S/s

Particle Burst Filters- All V, E, SCM- 0.8 - 100 Hz Filter- 2 -256 S/s

Wave Burst Filters- All V, E, SCM- 200 - 4/8 kHz Filter- 512 S/s - 8/16 kS/s

Spectra Generation- All V, E, SCM,Derived Quantities- Hanning Window- 1k/2k point FFT- Calculate power- Create 16, 32, or64 pseudo-logspaced bins

Spec2 (ID78)Spec1 (ID78)




HFAve (ID81)

HFPeak (ID81)

Fbank1 (ID64)

Fbank2 (ID64)

FbankT2 (ID81)

FbankT1 (ID81)

FB #2 (6 bands)

FB #1 (11 bands)

FB #2 (11 bands)

On During FastSurvey Only.

Always On.

EDER (ID75)

SCMDER (ID76)

8-bit Psuedo-logCompressor34 bits 8 bits

Acquisition Processing Telemetry

16kS/s AnalogQuantitiesE12AC, E34AC,E56AC

Take 8 MSBs

HFAve (ID64)

HFPeak (ID64)

DSP Functions and Data Products


ADC Interface(ADI)

ADC#1

ADC#2

ADCInterface

ADCInterface

Fast FourierTransform

(FFT)

Digital Filters(FIL)

Command &TelemetryController

(CTC)

Memory AccessController (MAC)

SRAM128k x 32

DFB FPGA Logic Boundary

Calculation ofDerived

Quantities(DER)

FGE Interface

SRAMInterface

AnalogSelection

Logic

V1V2V3V4V5V6

E12DCE34DCE56DCSCM1SCM2SCM3

E12ACE34ACE56ACE12HF

Analog Selection Interface

FFT ConfigurationDigital Filters Configuration

Derived Quantities ConfigurationADC Interface Configuration

Command/DataInterface

to/fromDigitalControlBoard

FPGA Infrastructure Elements

FPGA Algorithm Elements

External Elements

MAC Synchronization

• Algorithms– FIL - Digital Filtering– DER - Coordinate System

Alignment and Cross/Dot Product Calculation

– FFT - Spectral Analysis using Fourier Transforms

Digital Signal Processing Architecture

• Infrastructure– ADI - Control of Analog to

Digital Conversion– MAC - SRAM Interface– CTC - Post-processing and

compression of data products– CTC - Command and

Telemetry interface controller


• Quality– Multiple verification and test paths to maximize coverage– Maximize the “time on the hardware”

• Visibility– Good schedule visibility – Want to know immediately if the design gets off track– Maintain a “working” board at all times

• Efficiency– Development multiple DSP Algorithms in parallel– Identify and resolve board-level issues early– Identify and resolve algorithm issues early– Smooth integration of sub-components into the system

• Collaboration– Encourage interaction between the science and engineering

teams– Natural synchronization of team efforts

Development Process Objectives


Develop & VerifyCommon Data

HandlingInfrastructure

Develop IdealAlgorithm #1

Implement andVerify HW-constrainedAlgorithm #1

IntegrateAlgorithm(s)

into CommonData HandlingInfrastructure

Develop IdealAlgorithm #N

Implement andVerify HW-constrained

Algorithm #N

Prototype andDebug

FPGA-basedSystem

ScienceRequirementsand Objectives

Verified FPGAAnalysis of

HW-constrainedAlgorithm #1

Analysis ofHW-constrained

Algorithm #N

• After algorithm analysis and design, data-handling infrastructure (and PCB design) can be pursued in parallel with the algorithms.

– Isolates external interfaces and timing issues to the infrastructure elements to help identify board-level issues early.

– Infrastructure provides a kernel to which the algorithm packages can be attached using a well-defined interface.

– Allows incremental development for good schedule visibility and reduces undesirable interactions between components.

• Pitfall: Because this methodology implies a conscious decision to pursue the FPGA infrastructure and the algorithm development as discrete, parallel items it is especially important to maintain a common, clear specification of the interface between the two or system integration will be painful and time-consuming!

Development Process Overview


Develop &Verify IdealAlgorithmusing IDL

Ideal AlgorithmScience

Requirementsand Objectives

Test CasesDevelopTest Cases

• Start with Science Requirements and Objectives• Produce the ideal algorithm and relevant test/use cases.• Test cases are carried forward through all subsequent

phases of the development process and so the file formats should be compatible with all simulation and test environments.

Development of Ideal Algorithm


Determine& Apply

HW-imposedConstraints

YesIdeal Algorithm

HW-constrainedAlgorithm

AcceptAlgorithm?

ProposedHW-constrained

Algorithm

No

• Constraints– Clock frequency– Logic resources available– Algorithm RAM usage/bandwidth – RTSX parts don’t have onboard RAM– Logic optimization trade-offs – clock cycles vs. size

• HW-constrained algorithm– Number formatting - floating vs. fixed point, bit width, round-off error, etc.– Generate initial logic estimates– RAM map for data storage– Arbitration scheme if more than one algorithm shares the RAM storage

• Is performance acceptable and can the algorithm be implemented in the target technology?

Design of HW-constrained Algorithm


• The ideal and HW-constrained algorithms can differ significantly and still provide a valid comparison. For instance…

• FFT data is much easier to interpret if it is in a field-aligned coordinate system.• Once the power spectrum is performed, the data cannot be re-rotated• FPGA rotates the vectors prior to the FFT

• Want two components: 1 field-aligned 1 perpendicular, in spin plane

B

Spin plane




• On the ground, the easiest way to find the parallel and perpendicular components is:

• Problem: expensive in logic, especially square roots– Can provide the same result with CORDIC rotations

using a fraction of the logic.

222

222||

][

zyx

xyyx

zyx

BBB

BEBEE

BBB

BEE


2 rotations are required:

1. Rotate about spin axis. 2. Rotate about E34' .

B

E12

E34E56

E12'

E34'

E_par

BE56

E34'B

E_perp



?=

SimulationLog Files

Test Cases

HW-constrainedVHDL Model of

Algorithm

FunctionalVHDL

Simulation

IDLProcessing

HW-constrainedIDL Model

of Algorithm

Model HW-constrainedAlgorithm in

VHDL

Model HW-constrainedAlgorithm

in IDL

FunctionallyVerified HW

Algorithm

IDLProcessing

?=

Yes

No

No

Yes

HW-constrainedAlgorithm

IdealAlgorithm

EquivalencyCheck

• Simulation testbench for this component replicates the data-handling infrastructure interface to ensure easy integration.

• Use functional simulation to identify and fix algorithm errors.

Implement & Verify HW-constrained Algorithm


• Simulation log files of each processing stage allow fast debug of issues.

• Tight coupling between design and IDL routines comes in handy…– VHDL simulations checked

directly against IDL– Bit-level testing available– Discrimination between

algorithmic and implementation bugs

– Fast feedback

• Example: This IDL/VHDL interaction was used to quickly identify an error in the power calculation algorithm by plotting the IDL and VHDL results to ensure that they match…

Implement & Verify HW-constrained Algorithm


FunctionallyVerified HW

Algorithm

Verified DataHandling

Infrastructure

IntegrateAlgorithm(s) &Data HandlingInfrastructure

FunctionallyVerified FPGA

DesignYes

PrototypeFPGA Design

HW-constrainedIDL Model of

Algorithm

SimulationLog Files

FunctionalVHDL

Simulation

IDLProcessing

?=

UseSimulation toDiagnose andFix Issue(s)

No

Test Cases

• Since the data-handling infrastructure was developed and verified separately, it is available for board-level testing in parallel with algorithm simulations.

Develop Functionally Verified FPGA


PrototypeFPGA

Test UsingLabview

Testbench

Pass-throughWaveforms

IDLProcessing

?=

YesVerified Flight

FPGA

3 Iterations1. Reprogammable FPGA2. SXA parts3. SXS parts

Timing analysis and simulation becomes progressivelymore stringent as you get closer to flight...balancesimulation and lab testing to optimize coverage.

FunctionallyVerified FPGA

Design

PerformTiming

Analysis andSimulation

Synthesize,Place & Route

FPGA

FlightFPGA?

Yes

Use Appropriate Testing& Simulation to Diagnose

and Fix Issue(s)No

Test Cases

Verified FPGA

Change tonext higheriteration of

FPGA

No

Telemetry LogFiles

• Reprogrammable Prototype ASX RTSX• Timing analysis and simulation become progressively more stringent the closer you

get to flight…balance simulation and lab testing to optimize coverage.• Iterations do not mean to use a “code and fix” methodology.• Pitfall: Due to schedule concerns, there is often a desire to “go to flight form-factor”

before the reprogrammable prototype has been thoroughly tested and appropriate lessons have been learned. Doing so can impose unnecessary overhead that actually exacerbates schedule concerns, especially when the issues being addressed are purely functional or algorithmic in nature.

FPGA Development Iterations


• Files are the same format as simulation, allowing yet another cross-check of the test cases.

• Top-level VHDL test-bench logic emulates test fixture which means that simulation equals real world as much as possible.

CMD TLM FGE ADI

IDL Processing

CMD FileManager

TLM FileManager

FGE FileManager

ADI FileManager

CMDLabViewInterface

CDI TXLogic

TLMLabViewInterface

CDI RXLogic

FGELabViewInterface

FGE TXLogic

ADILabViewInterface

ADC &Selection

LogicEmulation

DFB_DUT (Devices Under Test)

CLKPPS

ResetControl

Clocks AfterReset (CAR)

Counter

Global Reset

8MHz Clock

Control

Data

dfb_tb.vhd

LabVIEWComponents

BackplaneSimulatorFPGA

Not Used

Files to DefineTest Cases...

LabVIEW Test Fixture for In-Circuit Test


Fourier Transform Pass-through Analysis

IDL Result

FPGA Result

Difference

• A logarithmic chirp waveform from a signal generator is passed through the system unaltered and is processed using IDL.• The IDL result is automatically compared against the FPGA generated data product and the difference is computed.


• This example shows a set of inputs that results in extracted parallel and perpendicular components that are an amplitude modulated chirp signal.

• A pass/fail metric of error (in bits) between ideal and HW-constrained algorithms was applied in this case.

• Another noteworthy test was a Monte Carlo mode to really stress out the algorithms (especially the vector interpolation algorithm) and provide comprehensive coverage of the 3-dimensional space.

Derived Quantities Pass-through Analysis


• The Board and Flight FPGAs have been delivered to THEMIS project for integration into the rest of the system.

• Perhaps the most desirable result of the process was the collaboration between the science and engineering teams.

Conclusion

Implementing Digital Signal Processing Algorithms in Actel’s RT54SX-S Family

Documents