Abstract—This paper presents a discussion of methods to solve partitioning problems and advocates the use of multi-way partitioning algorithms. The paper gives an implementation of a multi-way partitioning algorithm based on partitioning without size constraint and iterative improvement. A top-down clustering technique is employed to deal with the local minima problems faced in common heuristics and a primal-dual approach is used to enhance the iterative improvement. The Fiduccia-Mattheyses (FM) algorithm has been taken as the core algorithm which has been subjected to iterations, clustering and primal-dual iterations. The algorithm has been implemented in a way that it gives netlist files for each partitioned block. These netlists can further be used to implement actual hardware or detailed analysis. The results obtained were compared to the results obtained from the traditional FM algorithm. The results show good improvements. Index Terms—Benchmarks, Cells, Clustering, Hypergraph, Net, Netlist, Nodes, Pads, Partitioning, Primal-Dual. I. INTRODUCTION The Electronic Design Automation (EDA) involves automation of all those tasks that are used in fabrication of electronic circuits on silicon. Circuit designers specify their circuit requirements in programming languages like Hardware Description Languages (HDL) (Commonly used languages are VHDL, Verilog and Analog VHDL). Specifications are analyzed and modifications are made based on varying requirements. Once the requirements are complete, the HDL based codes are synthesized into gate-level netlist. The netlist mainly contains gates (such as AND gates, OR gates etc.) widely called as cells, and the interconnecting wires (that interconnect gates) widely called as nets. This netlist is then subjected to physical design automation (back-end flow), where cells are assigned different areas on actual silicon (placement) and the actual routes or paths that each connection (interconnecting wire) should take to connect the cells are identified (routing). During the placement various factors like wire length, path delay, congestion (when a local region contains more nets than the available routing tracks the region is said to be congested) etc. are considered. Most of these factors can be resolved using various hypergraph partitioning algorithms. Consider a system; partitioning will divide the whole circuit from the system level to the board level, from the board level to the chip level, and from the chip level to the macro-cell level. At each level, circuits are further divided Manuscript received August 14, 2012; revised September 20, 2012. Kulpreet S. Sikand and Sandeep S. Gill are with the Guru Nanak Dev Engg. College, Ludhiana, Punjab, India (e-mail: [email protected], [email protected]). R. Chandel and A. Chandel are with the NIT Hamirpur, Hamirpur, India (e-mail: [email protected], [email protected]). into smaller sub-circuits. A good partitioning will work to significantly reduce the complexity of the problem and improve both the reliability and the timing performance of the system. Historic research data reveals that the choice of the objective function is usually set to minimize the number of nets connecting the two final subsets (called blocks i.e in case of a bi-partitioning method). In case of different designs of multiple blocks partitioning, often the demand is for a different objective function or functions. For example if we consider silicon physical layout, the partitioning of a circuit must guarantee that the resultant sub-circuits have a number of IO pins (or pads etc.) that are within the physical limit requirements. So, to ensure a feasible implementation one objective function could be to minimize the maximum number of IO pins. A second objective function that can be considered for physical layout is to simplify the routing problem. For example if a net is connected exactly to say x blocks, then the cost function can be assigned a value of x. The objective function in this case is to minimize the sum of all costs assigned to each net. A third possible objective function for silicon physical layout from the architectural point of view is to have minimal interface signals among the blocks resulting from partitioning. So, clearly the objective function in this case is to minimize the number of nets connecting more than two blocks. Many more objective functions can be derived from the variable requirements and problems. As all these problems and requirements optimize on different objective functions the traditional two-way partitioning algorithms cannot be applied directly to solve them. Hence the need for multi-way and multi-objective partitioning algorithm is evident. In this paper an attempt has been made to advocate the use of multi-way partitioning algorithms over the two-way partitioning algorithms based on their performance. The only addition to the existing multi-way partitioning algorithm which this paper proposes is the addition of pads to the output netlist files to make them self-revealing standalone files, this easies further analysis of these files. The organization of the paper is as follows: Section 2 gives a brief review of previous research. Section 3 introduces a formal definition of the problem. This section presents an iterative improvement algorithm for partitioning. The algorithm utilizes a top-down clustering technique and a Primal-Dual iteration to enhance the partitioning result. Section 4 contains experimental results & discussions. Section 5 contains the conclusion. II. PREVIOUS WORK Attempts have been made to solve graph and network related partitioning problems with specified bound on the Implementation of Multi-Way Partitioning Algorithm Kulpreet S. Sikand, Sandeep S. Gill, R. Chandel, and A. Chandel International Journal of Computer and Communication Engineering, Vol. 2, No. 1, January 2013 28
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Implementation of Multi-Way Partitioning Algorithm · Fiduccia-Mattheyses (FM) algorithm has been taken as the core algorithm which has been subjected to iterations, clustering and
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Abstract—This paper presents a discussion of methods to
solve partitioning problems and advocates the use of multi-way
partitioning algorithms. The paper gives an implementation of
a multi-way partitioning algorithm based on partitioning
without size constraint and iterative improvement. A top-down
clustering technique is employed to deal with the local minima
problems faced in common heuristics and a primal-dual
approach is used to enhance the iterative improvement. The
Fiduccia-Mattheyses (FM) algorithm has been taken as the core
algorithm which has been subjected to iterations, clustering and
primal-dual iterations. The algorithm has been implemented in
a way that it gives netlist files for each partitioned block. These
netlists can further be used to implement actual hardware or
detailed analysis. The results obtained were compared to the
results obtained from the traditional FM algorithm. The results
show good improvements.
Index Terms—Benchmarks, Cells, Clustering, Hypergraph,