Chapter I Reed Solomon encoder 1.1 Introduction Reed– Solomon (RS) codes are non-binary cyclic error- correcting codes invented in 1960; Irving Reed and Gus Solomon published a paper in the Journal of the Society for Industrial and Applied Mathematics. They described a systematic way of building codes that could detect and correct multiple random symbol errors. Reed-Solomon coding is a type of forward-error correction that is used in data transmission (vulnerable to channel noise) plus data-storage and retrieval systems. Reed- Solomon code’s (encoders/decoders) can detect and correct errors within blocks of data. Reed-Solomon code’s operate on blocks of data, these codes are generally designated as (n, K) block codes, K is the number of information symbols input per block, and n is the number of symbols per block that the encoder outputs. Reed Solomon Decoder is useful in correcting burst noise; it replaces the whole word if it is not a valid code word. This Reed Solomon Decoder is designed according to CCSDS Standards. Reed-Solomon codes are used to perform Forward Error Correction (FEC). FEC introduces redundancy in the data before it is transmitted. The redundant data (check symbols) are transmitted with the original data to the receiver. For example, a Reed-Solomon decoder is used to help recover any error data.
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Chapter I
Reed Solomon encoder
1.1 Introduction
Reed– Solomon (RS) codes are non-binary cyclic error-correcting codes invented in
1960; Irving Reed and Gus Solomon published a paper in the Journal of the Society for Industrial
and Applied Mathematics. They described a systematic way of building codes that could detect
and correct multiple random symbol errors. Reed-Solomon coding is a type of forward-error
correction that is used in data transmission (vulnerable to channel noise) plus data-storage and
retrieval systems. Reed- Solomon code’s (encoders/decoders) can detect and correct errors
within blocks of data. Reed-Solomon code’s operate on blocks of data, these codes are generally
designated as (n, K) block codes, K is the number of information symbols input per block, and n
is the number of symbols per block that the encoder outputs. Reed Solomon Decoder is useful in
correcting burst noise; it replaces the whole word if it is not a valid code word. This Reed
Solomon Decoder is designed according to CCSDS Standards.
Reed-Solomon codes are used to perform Forward Error Correction (FEC). FEC
introduces redundancy in the data before it is transmitted. The redundant data (check symbols)
are transmitted with the original data to the receiver. For example, a Reed-Solomon decoder is
used to help recover any error data. The codes are referred to in the format RS (n,k) where k is
the number of s-bit wide information (data) symbols and n is the total number of s-bit wide
symbols in a codeword. The Reed-Solomon encoder generates a code such that the first k
symbols output from the encoder are the information symbols and the next n-k symbols from the
encoder are the check symbols added for error correction.
1.2 Features
Scaling factor for the generator polynomial root index:1
Number of information or data symbols in a code block: 223
Clock Period Waveform Attrs Sources--------------------------------------------------------------------------master_clock 2.50 {0 1.25} {clkin}--------------------------------------------------------------------------
Rise Fall Min Rise Min fall UncertaintyObject Delay Delay Delay Delay Plus Minus--------------------------------------------------------------------------master_clock 0.60 0.60 0.60 0.60 0.12 0.25
UTILIZATION RATIOS------------------Chip area : 28200.96Core Area : 15852.96SiteRow area : 14832.72Non-SiteRow area : 1020.24Cell/Core Ratio : 50.7221%Cell/Chip Ratio : 28.5131%
3.3 Floorplanning and PG network
VDD railW_vertical – Metal 8 = 8 micronsW_horizontal – Metal 9 = 8 microns
VSS rail:W_vertical – Metal 8 = 8 micronsW_horizontal – Metal 9 = 8 microns
Core to IO clearance width = 21 microns
Core Area IO Pads
Power (VDD) andGround (VSS) rails
3.4 Placement
Power and Ground pins
3.5 Clock tree synthesis information
Timing report before clock tree synthesis
----------------------------------------------------------- data required time 2.31 data arrival time -2.37 ----------------------------------------------------------- slack (VIOLATED) -0.06
Clock distribution before clock tree synthesis
Power straps
Clock distribution after CTS
Timing report after CTS
----------------------------------------------------------- data required time 2.36 data arrival time -2.28 ----------------------------------------------------------- slack (MET) 0.08
Startpoint: b15/out_reg[2] (rising edge-triggered flip-flop clocked by master_clock)Endpoint: b8/out_reg[5] (rising edge-triggered flip-flop clocked by master_clock)Path Group: master_clockPath Type: max ----------------------------------------------------------- data required time 2.36 data arrival time -2.28 ----------------------------------------------------------- slack (MET) 0.08
Operating Conditions: BCCOM Library: tcbn65lpbcWire Load Model Mode: segmented
Design Wire Load Model Library------------------------------------------------rs_encode ZeroWireload tcbn65lpwc
Global Operating Voltage = 1.32 Power-specific unit information :Voltage Units = 1VCapacitance Units = 1.000000pfTime Units = 1nsDynamic Power Units = 1mW (derived from V,C,T units)Leakage Power Units = 1nW
Cell Internal Power = 1.1041 mW (80%)Net Switching Power = 283.2232 uW (20%) ---------Total Dynamic Power = 1.3873 mW (100%)
Cell Leakage Power = 2.4163 uW
Chapter V
Results and Conclusion
5.1 Results
Achieved frequency is 400 MHz
Slack is met with the value 0.08
The logic area is 51%
Width Height Area
o Core 130.800 121.200 15852.960
o Chip 172.800 163.200 28200.960
Chip width is 131 microns
Chip height is 121 microns
Power and Ground rail width of 8 microns
Timing is met with the skew of 0.08 after CTS
Routing is done with 9 layer metal
The design is free from all DRC violations except the Met 1 violations
The total dynamic power of the chip after routing is 1.3873 mw with the leakage power
of 2.4163 um
5.2 Conclusion
Implementation of the High speed Reed Solomon encoder using Synopsys IC compiler is
successfully completed meeting all design specifications.
The design is successfully implemented .to work with the operating frequency of 400
Mhz with the supply voltage of 1.32v.
The timing constraint of the design is met with the positive slack of 0.08 ns.
The total dynamic power achieved is 1.3873 mw which is within the range of dynamic
power specified (i.e. 2 mw).
The total area of the chip is 28200.960 microns out of wich 51% of the area is occupied