Implementation Characterstics of Interconnect Mechanisms in Clustered VLIW Architectures Anup Gangwar Embedded Systems Group, Department of Computer Science and Engineering, Indian Institute of Technology Delhi http://embedded.cse.iitd.ernet.in August 12, 2004 (Joint work with M. Balakrishnan, Preeti R. Panda and Anshul Kumar) Ph.D. Thursday Seminar Series http://embedded.cse.iitd.ernet.in Slide 1/32
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Implementation Characterstics of InterconnectMechanisms in Clustered VLIW Architectures
Anup Gangwar
Embedded Systems Group,Department of Computer Science and Engineering,
Indian Institute of Technology Delhihttp://embedded.cse.iitd.ernet.in
August 12, 2004
(Joint work with M. Balakrishnan, Preeti R. Panda and Anshul Kumar)
Ph.D. Thursday Seminar Series http://embedded.cse.iitd.ernet.in Slide 1/32
Outline
VLIW Features and Typical Datapath Organization
Clustered VLIW Processors and Performance Evaluation of
Interconnects
Objectives of Clock-period Evaluation Excercise
Architecture of Modeled Processors
Clock-period Evaluation Flow
Experimental Results
Conclusions
Future work
Ph.D. Thursday Seminar Series http://embedded.cse.iitd.ernet.in Slide 2/32
VLIW Architecture and Features
Compiler extracts parallelism, these have evolved fromhorizontal microcoded architectures
Latest industry coined acronym, EPIC for Explicitly ParallelInstruction Computing
Commercial Architectures:
General Purpose Computing: Intel Itanium
Embedded Computing: TriMedia, TiC6x, Sun’s MAJC etc.
Ph.D. Thursday Seminar Series http://embedded.cse.iitd.ernet.in Slide 26/32
Outline
VLIW Features and Typical Datapath Organization
Clustered VLIW Processors and Performance Evaluation of
Interconnects
Objectives of Clock-period Evaluation Excercise
Architecture of Modeled Processors
Clock-period Evaluation Flow
Experimental Results
Conclusions
Future work
Ph.D. Thursday Seminar Series http://embedded.cse.iitd.ernet.in Slide 27/32
Conclusions
The increase in clock period for RF-to-RF architectures isvery high
For other interconnect architectures, the variation acrossdifferent interconnect mechanisms is negligible.
There is a small increase in clock period with an increase innumber of clusters for interconnect mechanisms other thanRF-to-RF.
Bidirectional connectivity architectures, WA.2 and RA.2,lose out somewhat in terms of clock period as compared totheir unidirectional connectivity architectures and this impactis more in smaller cluster configurations.
Ph.D. Thursday Seminar Series http://embedded.cse.iitd.ernet.in Slide 28/32
Conclusions (contd...)
While the interconnect lengths do vary in case ofunidirectional and bidirectional architectures this increase isin proportion to the increase in logic area.
The variation in interconnect area even with an increase innumber of cluster is not much. This is due to acorresponding increase in the logic area. Basically theinterconnect area per cluster is more of less constant.
Ph.D. Thursday Seminar Series http://embedded.cse.iitd.ernet.in Slide 29/32
Outline
VLIW Features and Typical Datapath Organization
Clustered VLIW Processors and Performance Evaluation of
Interconnects
Objectives of Clock-period Evaluation Excercise
Architecture of Modeled Processors
Clock-period Evaluation Flow
Experimental Results
Conclusions
Future work
Ph.D. Thursday Seminar Series http://embedded.cse.iitd.ernet.in Slide 30/32
Future Work
What could be done to bus based architectures to improveperformance: Multicycle and Pipelined buses
Development of fast performance estimation techniques
Search for an architecture which on the average gives goodperformance
Ph.D. Thursday Seminar Series http://embedded.cse.iitd.ernet.in Slide 31/32
Thank You
Thank You
Ph.D. Thursday Seminar Series http://embedded.cse.iitd.ernet.in Slide 32/32