Image Compression With Discrete Cosine Transforms Initial Project Proposal – (9/21/99) David Oltmanns Delayne Vaughn John Hill.

Image Compression Image Compression With Discrete Cosine TransformsWith Discrete Cosine Transforms

Initial Project Proposal – (9/21/99)

David OltmannsDelayne Vaughn

John Hill

Project ObjectivesProject Objectives DeliverableDeliverable Project Background in BriefProject Background in Brief Hardware/Software Component DescriptionHardware/Software Component Description Subsystems Development DecompositionSubsystems Development Decomposition TimelineTimeline Team Member ResponsibilitiesTeam Member Responsibilities ComponentsComponents PricingPricing Special Testing EnvironmentsSpecial Testing Environments Hardware, Software CollaborationsHardware, Software Collaborations ReferencesReferences

ContentsContents

Image Compression With Discrete Cosine Transforms

Our design will use a Connectix QuickCam and PC Our design will use a Connectix QuickCam and PC interfaced to a Xilinx FPGA. We hope to achieve interfaced to a Xilinx FPGA. We hope to achieve the following goals:the following goals:

Capture the imageCapture the image using QuickCam using QuickCam Compress the imageCompress the image using FPGA-based 2-D using FPGA-based 2-D

Discrete Cosine Transform (DCT) on a Xilinx FPGADiscrete Cosine Transform (DCT) on a Xilinx FPGA Decompress the imageDecompress the image using Inverse DCT (IDCT) using Inverse DCT (IDCT) Display decompressed imageDisplay decompressed image on a PC using a on a PC using a

serial port as the interfaceserial port as the interface

Project ObjectivesProject Objectives


DeliverablesDeliverablesOur final deliverable will be a compression/decompression system utilizing a FPGA interfaced with a Connectix Quickcam and a PC. The system will allow an image to be captured by the camera, compressed and decompressed by the modules built on the FPGA, and finally returned to the PC. The FPGA will be outfitted with 2-D DCT logic and also incorporate a serial interface, camera interface, and memory control module. Reference figure left.


2-D Discrete Cosine transfer2-D Discrete Cosine transfer

2-D Inverse Discrete Cosine transfer2-D Inverse Discrete Cosine transfer

Project Background in BriefProject Background in Brief


Project Background in BriefProject Background in Brief

2-D Fast Discrete Cosine Transform

Signal Flow diagram (right)


Complete SystemComplete System Compression/Decompression Module(s)Compression/Decompression Module(s) Digital Camera/Camera Interface – Digital Camera/Camera Interface –

(Connectix QuickCam)(Connectix QuickCam) SRAM and Memory Control ModuleSRAM and Memory Control Module Serial Interface Module for FPGASerial Interface Module for FPGA

Hardware/Software DescriptionHardware/Software Description


Complete SystemComplete System Compression/Decompression Compression/Decompression

Module(s)Module(s) Digital Camera/Camera Digital Camera/Camera

Interface Interface SRAM and Memory Control SRAM and Memory Control

ModuleModule Serial Interface Module for Serial Interface Module for

FPGAFPGA

Hardware/Software Hardware/Software DescriptionDescription



Module(s)Module(s) Digital Camera/Camera Interface Digital Camera/Camera Interface SRAM and Memory Control SRAM and Memory Control

ModuleModule Serial Interface Module for FPGASerial Interface Module for FPGA


Component location is system (left)

Compression, Compression, Decompression Decompression

Module (right)Module (right)




InterfaceInterface SRAM and Memory Control SRAM and Memory Control


FPGAFPGA


This figure shows the subset of a

previous groups design that

interfaces with the camera. We

plan on deploying a

similar configuration.






FPGAFPGA







FPGAFPGA


We plan to take existing serial knowledge that has been developed by previous students and integrate it with the rest of our design. One such source is the PDACS project (Spring 1999). Figure 6 shows one scenario that this group used in their project.


Subsystems Development Subsystems Development Decomposition Decomposition

Software SimulationSoftware Simulation FPGA CompressionFPGA Compression FPGA DecompressionFPGA Decompression FPGA Module Integration with QuickCamFPGA Module Integration with QuickCam


Software SimulationSoftware Simulation FPGA CompressionFPGA Compression FPGA DecompressionFPGA Decompression FPGA Module FPGA Module

Integration with Integration with QuickCamQuickCam

Subsystems Development Subsystems Development DecompositionDecomposition






Software SimulationSoftware Simulation FPGA CompressionFPGA Compression FPGA DecompressionFPGA Decompression FPGA Module Integration FPGA Module Integration

with QuickCamwith QuickCam







TimelineTimelineWeek Three Week Three Sept. 12 - 18 Sept. 12 - 18

Research DCT and sub-systemsResearch DCT and sub-systemsBegin ProposalBegin Proposal

Week FourWeek Four Sept. 19 - 25 Sept. 19 - 25

Finalize ProposalFinalize Proposal

Present Proposal (Sept. 21)Present Proposal (Sept. 21)Begin Software Implementation of Compression AlgorithmBegin Software Implementation of Compression Algorithm

Week FiveWeek Five Sept. 26 - Oct. 2Sept. 26 - Oct. 2

Finish Software Compression AlgorithmFinish Software Compression AlgorithmBegin Software Decompression AlgorithmBegin Software Decompression AlgorithmIntegrate Compression/Decompression Software Integrate Compression/Decompression Software ComponentsComponentsBegin Serial Interface ModuleBegin Serial Interface Module

Week Six Week Six Oct. 3 - 9Oct. 3 - 9

Continue Serial Interface ModuleContinue Serial Interface ModuleBegin SRAM Control ModuleBegin SRAM Control Module

Biweekly Report 1 (Oct. 7)Biweekly Report 1 (Oct. 7)

Week SevenWeek Seven Oct. 10 - 16Oct. 10 - 16

Finish Serial Interface ModuleFinish Serial Interface ModuleFinish SRAM Control ModuleFinish SRAM Control ModuleBegin FPGA Compression ModuleBegin FPGA Compression Module

Week EightWeek Eight Oct. 17 - 23Oct. 17 - 23

Finish FPGA Compression ModuleFinish FPGA Compression ModuleIntegrate SRAM, Serial Interface, and Compression Integrate SRAM, Serial Interface, and Compression ModulesModules

Biweekly Report 2 (Oct. 21)Biweekly Report 2 (Oct. 21)

Week Nine Oct. 24 - 30

Benchmark: Test Integrated FPGA Compression Begin FPGA Decompression ModuleBegin Camera InterfaceBegin Mid-term Presentation

Week Ten Oct. 31 - Nov. 6

Finish FPGA Decompression ModuleMid-term Presentation (Nov. 4)Integrate Decompression and Compression Modules

Week Eleven Nov. 7 - 13

Finish Camera InterfaceIntegrate Camera Interface with Existing Modules

Week Twelve Nov. 14 - 20

Benchmark: Camera Interface with Existing ModulesExisting ModulesBiweekly Report 3 (Nov. 18)

Week Thirteen Nov. 21 - 27

Begin Final PresentationThanksgiving

Week Fourteen Nov. 28 - Dec. 3

Overflow (Unforeseen Tasks)Finalize Presentation

Week Fifteen Dec. 4 - 10

Final Presentation (Dec. 7)

Team Member ResponsibilitiesTeam Member Responsibilities

Research DCT and sub-systems Research DCT and sub-systems John, David, DelayneJohn, David, Delayne Prepare Proposal Prepare Proposal John, David, DelayneJohn, David, Delayne Present Proposal (Sept. 21) Present Proposal (Sept. 21) John, David, DelayneJohn, David, Delayne Software Implementation of Compression Algorithm Software Implementation of Compression Algorithm David, DelayneDavid, Delayne Software Implementation of Decompression Algorithm Software Implementation of Decompression Algorithm David, DelayneDavid, Delayne Integrate Compression/Decompression Software Components Integrate Compression/Decompression Software Components David, DelayneDavid, Delayne Serial Interface Module Serial Interface Module JohnJohn SRAM Control Module SRAM Control Module JohnJohn Biweekly Report 1 (Oct. 7) Biweekly Report 1 (Oct. 7) John, David, DelayneJohn, David, Delayne FPGA Compression Module FPGA Compression Module John, David, DelayneJohn, David, Delayne Integrate SRAM, Serial Interface, and Compression Modules Integrate SRAM, Serial Interface, and Compression Modules John, DavidJohn, David Biweekly Report 2 (Oct. 21) Biweekly Report 2 (Oct. 21) John, David, DelayneJohn, David, Delayne Benchmark: Test Integrated FPGA Compression Benchmark: Test Integrated FPGA Compression John, DavidJohn, David FPGA Decompression Module FPGA Decompression Module DelayneDelayne Camera Interface Camera Interface DavidDavid Prepare Mid-term Presentation Prepare Mid-term Presentation John, David, DelayneJohn, David, Delayne Mid-term Presentation (Nov. 4) Mid-term Presentation (Nov. 4) John, David, DelayneJohn, David, Delayne Integrate FPGA Decompression and Compression Modules Integrate FPGA Decompression and Compression Modules DelayneDelayne Integrate Camera Interface with Existing Modules Integrate Camera Interface with Existing Modules John, DavidJohn, David Benchmark: Camera Interface with Existing Modules Benchmark: Camera Interface with Existing Modules John, David, DelayneJohn, David, Delayne Biweekly Report 3 (Nov. 18) Biweekly Report 3 (Nov. 18) John, David, DelayneJohn, David, Delayne Prepare Final Presentation Prepare Final Presentation John, David, DelayneJohn, David, Delayne Final Presentation (Dec. 7) Final Presentation (Dec. 7) John, David, DelayneJohn, David, Delayne


ComponentsComponents


ComputerComputer Software including: Xilinx Software including: Xilinx

Foundation Series, LabVIEWFoundation Series, LabVIEW FPGA(s)FPGA(s) SRAMSRAM Project Board/Power SupplyProject Board/Power Supply Xilinx Interface CableXilinx Interface Cable

PricingPricing Xilinx XC4010E PC84 FPGAXilinx XC4010E PC84 FPGA $62.35 (each)$62.35 (each) Connectix QuickCamConnectix QuickCam $49.95$49.95 WINBOND W24257AX-15 SRAMWINBOND W24257AX-15 SRAM

Hardware, Software CollaborationsHardware, Software Collaborations

System Hardware Software Breakdown

HARDWARE SOFTWARE

Both hardware and software components are vitally important to the development and implementation of our system.


N. Ahmed, T. Natarajan, and K.R. Rao, "Discrete cosine N. Ahmed, T. Natarajan, and K.R. Rao, "Discrete cosine transform," IEEE transform," IEEE Trans. Comput., vol. C-23, pp. 90-93. Jan. 1974.Trans. Comput., vol. C-23, pp. 90-93. Jan. 1974. K. Aldrich, D. Brandenberger, C. Chilek, and B. K. Aldrich, D. Brandenberger, C. Chilek, and B. Raymond, "Sign Language Raymond, "Sign Language Aquisition and Recognition System," Aquisition and Recognition System," www.cs.tamu.edu/course-info/cpsc483/common/99b/www.cs.tamu.edu/course-info/cpsc483/common/99b/g3/Final.htm (Sept. 20, 1999)g3/Final.htm (Sept. 20, 1999) M. Berger, J. Curtin, T. Griffin, A. King, M. Nordfelt, M. Berger, J. Curtin, T. Griffin, A. King, M. Nordfelt, and J. Whitted, and J. Whitted, "Portable Digital Compression/Decompression System," "Portable Digital Compression/Decompression System," www.cs.tamu.edu/course-info/cpsc483/common/99a/www.cs.tamu.edu/course-info/cpsc483/common/99a/g5/g5.html (Sept. 20, 1999)g5/g5.html (Sept. 20, 1999) J. Berglund, R. Cuaycong, W. Day, A. Fikes, and K. J. Berglund, R. Cuaycong, W. Day, A. Fikes, and K. Shah, "Autonomous Shah, "Autonomous Tracking Unit," Tracking Unit," www.cs.tamu.edu/course-info/cpsc483/common/99a/g1/www.cs.tamu.edu/course-info/cpsc483/common/99a/g1/g1.html g1.html (Sept. 20, 1999)(Sept. 20, 1999)

N.I. Cho and S.U. Lee, "Fast algorithm and N.I. Cho and S.U. Lee, "Fast algorithm and implementation of 2-D discrete implementation of 2-D discrete cosine transform," IEEE Trans. CAS, Mar. 1991, pp. cosine transform," IEEE Trans. CAS, Mar. 1991, pp. 297-305 297-305

N.I. Cho and I.D. Yun, and S.U. Lee, "On the regular N.I. Cho and I.D. Yun, and S.U. Lee, "On the regular structure for the fast structure for the fast 2D DCT algorithm," IEEE Trans. CAS, Apr. 1993, 2D DCT algorithm," IEEE Trans. CAS, Apr. 1993, pp.259-266pp.259-266 S.C. Chan and K.L. Ho, "A new 2D fast cosine S.C. Chan and K.L. Ho, "A new 2D fast cosine transform algorithm," IEEE transform algorithm," IEEE Trans. SP, Feb. 1991, pp.481-485Trans. SP, Feb. 1991, pp.481-485 H.S. Hou, "A fast recursive algorithm for computing H.S. Hou, "A fast recursive algorithm for computing the discrete cosine the discrete cosine transform," IEEE Trans. ASSP, Oct. 1987, pp. 1455-transform," IEEE Trans. ASSP, Oct. 1987, pp. 1455-1461.1461. C.W. Kok, "Fast Algorithm for Computing 2D Discrete C.W. Kok, "Fast Algorithm for Computing 2D Discrete Cosine Transform," Cosine Transform," Unpublished article, pp. 1-4Unpublished article, pp. 1-4 R. Mahapatra, A. Kumar, and B. Chatterji, R. Mahapatra, A. Kumar, and B. Chatterji, "Performance Analysis of 2-D "Performance Analysis of 2-D Inverse Fast Cosine Transform Employing Inverse Fast Cosine Transform Employing Multiprocessors," Article, pp. 1-31Multiprocessors," Article, pp. 1-31

References References


Image Compression With Discrete Cosine Transforms Initial Project Proposal – (9/21/99) David Oltmanns Delayne Vaughn John Hill.

Documents

brief2d fast discrete

briefimage compression

d dct logic

system leftcompression

serial port

existing serial knowledge

xilinx fpgadecompress

previous groups