-
IJECT Vol. 6, IssuE 4, oCT - DEC 2015
w w w . i j e c t . o r g InternatIonal Journal of electronIcs
& communIcatIon technology 9
ISSN : 2230-7109 (Online) | ISSN : 2230-9543 (Print)
An Improved Low Power Johnson Counter Design with Clock
Gating
1Saumya Pandey, 2Sarita Uniyal, 3Dr. Nidhi Goel 1,2,3Dept. of
Electronics and Communication Engineering, IGDTUW Delhi, India
AbstractThis paper presents an improved low power design of a
4-bit Johnson Counter which is designed using pulse-triggered flip
flop and GDI based clock gated logic. The proposed design shows a
power reduction of 66.73% as compared to the conventional Johnson
counter & 44.76% as compared to the clock gated Johnson
counter. Pulse triggered flip flop employed in the proposed design
can save power up to 39.67% as compared to the Master Slave Flip
flop of the conventional design. All the simulations were carried
out using Tanner EDA in 90nm CMOS technology.
KeywordsClock Gating; Johnson Counter; Pulse-Triggered; GDI;
Sequential Circuit.
I. IntroductionPower minimization has become the main design
issue in the VLSI circuits with the downscaling of the chip sizes
& higher operational frequencies of the devices [1]. In digital
circuits, all the operations are executed on the transition edges
of the clock (positive or negative clock edge) and at every clock
transition, there will always be short circuit current dissipation
which contributes almost 15- 45% of the total power dissipation in
the system [2].The existing clock gated Johnson counter design
reduces power dissipation to a great extend by eliminating
unnecessary clock transitions and generating clock pulse sequences
only when an operation needs to be performed. In this paper, the
proposed Johnson counter is designed using pulse-triggered flip
flops and Gate Diffusion Input based clock gated logic which
enables lesser transistor count and hence ensures lower power
dissipation as compared to the clock gated counter design.
This paper is divided into six sections. Section II describes
short circuit power dissipation in sequential circuits. Section III
explains clock gated Johnson counter design. Section IV presents
the proposed design. Section V shows simulations & VI concludes
the paper.
II. Short Circuit Power Dissipation In Sequential CircuitsIn
sequential circuits, short circuit current dissipation occurs at
each clock transition. Fig.1 and Fig.2 shows the schematic of a
CMOS inverter and the short circuit current dissipation at every
clock transition respectively. Every clock pulse has a certain rise
& fall time which is very small as compared to the period of
the clock but cannot be neglected when measuring the power
dissipation in the system. At certain point of clock transition,
both NMOS and PMOS are conducting simultaneously, creating a short
circuit path between VDD and ground. Therefore, comparatively large
amount of current flows for a very short period of time through
that path causing short circuit power dissipation which occurs at
every clock transition [3].
Fig. 1: Schematic of a CMOS Inverter
Fig. 2: Short Circuit Current (µA) at Every Clock Transition
III. Clock Gated Johnson Counter DesignThe conventional Johnson
counter design contains many unwanted clock transitions which
results in larger power dissipation. From the data sequence of
Johnson counter as shown in Table I, it can be observed that each
flip flop output changes only at 2 clock pulses in one complete
cycle (8 clock pulses).So instead of providing 8 clock pulses, only
2 clock pulses for each flip flop are required to be generated
which is possible using a proper clock management system where
clock pulse sequences are generated only when data switching occurs
and ineffective clock transitions are eliminated from the system
[3-4].
-
IJECT Vol. 6, IssuE 4, oCT - DEC 2015 ISSN : 2230-7109 (Online)
| ISSN : 2230-9543 (Print)
w w w . i j e c t . o r g 10 InternatIonal Journal of
electronIcs & communIcatIon technology
Table 1: Truth Table of 4-Bit Johnson Counter
Fig. 3: 4-bit Clock Gated Johnson Counter
Fig. 3 shows schematic for the clock gated Johnson counter where
clock pulse sequences are generated only when a particular device
is required to perform an operation according to some observed
logic as stated in the following equations.
where Clkmaster represents master clock of the system which
provide necessary clock pulse sequences to the different segments
of the system.
IV. Proposed DesignThe proposed design of Johnson counter uses
Pulse-triggered T flip flop instead of conventional Master-Slave
flip flop & GDI technique based clock gated logic function (XOR
and XNOR gates) that enables lesser transistor count and hence
ensures lower power dissipation.
Fig. 4: Proposed Johnson Counter Design
A. Pulse-Triggered Flip-Flop DesignPulse-triggered flip flop
consists of a pulse generator for generating a short pulse of very
narrow pulse width around the rising (or falling) edge of the clock
which acts as clock input to the latch. Inverters I4 & I5 form
a latch for data storage. Two NMOS transistors N2 & N3 are
connected in parallel to form a two-input pass transistor logic
based AND gate which controls the discharge of transistor N1. As
inputs to the AND logic are always complementary except during the
transition edges of the clock so transistors N2 and N3 gets turned
ON at the rising edges of the clock and passes a weak logic High to
node A, due to which transistor N1 gets turned ON for the time
determined by the inverter I1 delay & a short pulse of very
narrow pulse width is generated around the rising (falling) edge of
the clock.
Fig. 5 shows a Pulse-triggered flip flop where PMOS transistor
P3 is incorporated to enhance pull down strength of transistor
N1when there is a longer discharging path i.e. when input data is
logic ‘1’and Qbar is also ‘1’.Transistor P3 also provide
enhancement to the width of the discharging pulse so that the
transistor sizes in the pulse generation circuit can be maintained
minimum [5].
Fig. 5: Pulse-triggered Flip Flop Old Design
-
IJECT Vol. 6, IssuE 4, oCT - DEC 2015
w w w . i j e c t . o r g InternatIonal Journal of electronIcs
& communIcatIon technology 11
ISSN : 2230-7109 (Online) | ISSN : 2230-9543 (Print)
Fig. 6: Modified Pulse-triggered Flip Flop Design Used in the
Proposed Johnson Counter
In the modified Pulse-triggered flip flop, PMOS transistor P3
has been removed and pulses with sufficient width has been
generated by increasing the sizes of transistors N2 and N3 and by
adjusting delay of the inverter I1 so that correct data can be
captured by the latch. Also, as the clock pulses are generated only
when output of the flip flop toggles according to the data sequence
of the Johnson counter so transistor N5 has been eliminated since
it is just operating as a resistor in the toggle mode and data
input is always connected to logic ‘1’.
B. GDI based clock gated logicA basic GDI (Gate Diffusion Input)
cell contains four terminals - G (the common gate input of NMOS and
PMOS transistors), N (outer diffusion node of NMOS), P (outer
diffusion node of PMOS) and D (common diffusion node of both NMOS
& PMOS) as shown in Fig.7. Different Boolean functions can be
expressed at output D depending on the various configurations of
the inputs P, N and G [6]. Some logic functions that can be
implemented using a basic GDI cell are stated in TABLE 2.
Fig. 7: A basic GDI cell
Table 2: Some Logic Functions Implemented With A GDI Cell
N P G D FUNCTION
1 B A A + B OR
B 0 A AB AND
0 1 A A’ INVERTERB’ B A AB’+A’B XORB B’ A AB+A’B’ XNOR
GDI technique enables low power design of a digital circuit with
reduced delay, area while maintaining lower complexity of the
design [6-7]. XOR & XNOR gates designed using GDI technique
contains 8 & 6 transistors respectively whereas conventional
CMOS logic based XOR & XNOR gates contain 13 &11transistors
respectively.
V. Simulation ResultsFig. 8 shows the simulation waveforms which
verifies the functionality of the clock gated Johnson counter where
clock pulses are generated only when the flip flop data toggles and
thereby eliminating unnecessary clock transitions.
Fig. 8: Simulation Waveforms of Clock Gated Johnson Counter
-
IJECT Vol. 6, IssuE 4, oCT - DEC 2015 ISSN : 2230-7109 (Online)
| ISSN : 2230-9543 (Print)
w w w . i j e c t . o r g 12 InternatIonal Journal of
electronIcs & communIcatIon technology
Fig. 9: Simulation Waveforms of Proposed Johnson Counter
Fig. 9 shows the simulation waveforms of the proposed Johnson
counter design where short pulses of very narrow pulse width are
generated around the rising (falling) edge of the clock (i.e. when
data toggles) which acts as clock input to the latch.
Fig. 10: Power Dissipation Comparison of the Proposed Design Vs
Conventional and Clock Gated Design at Different Values of
Frequency
Fig. 11: Comparison of Power Dissipation Between Proposed and
Conventional Flip Flop Designs
VI. ConclusionA 4-bit Johnson counter implemented using
pulse-triggered flip flop & GDI based clock gated system has
been presented. The simulation results verifies a power reduction
upto 66.73% as compared to conventional design & 44.76% as
compared to the clock gated design. The power dissipation of
proposed design ranges from 36.68µW to 54.69µW for frequency
ranging from 600MHz to 1GHz.Also, pulse-triggered flip flop used in
the proposed design can save power up to 39.67% as compared to the
Conventional Master Slave flip flop. The techniques used in the
proposed system can be extended to any sequential circuit design
where power minimization is an important constraint.
References[1] Neil H.E. Weste, David Harris, Ayan Banerjee,"CMOS
VLSI
Design", 3rd edition, Dorling Kindersley Pvt.Ltd., 2006.[2] M.
Pedram,“Power minimization in IC design: Principles
and applications”, ACM Trans. Design Automation, Vol. 1, No. 1,
pp. 3-56,Jan. 1996.
[3] S.M.Ismail, A B M Saadmaan Rahman, F.T. Islam,“Low Power
Design of Johnson Counter Using Clock Gating”, 15th IEEE
international conference on Computer and Information Technology
(ICCIT), 2012.
[4] Q.Wu, Pedram M., X. Wu,“Clock gating and its application to
low power design of sequential circuits”, IEEE Trans. on Circuits
and System I: Fundamental Theory and Applications, March 2000.
[5] Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu,“Low Power
Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement
Scheme”, IEEE transc. on VLSI systems, Vol. 20, No. 2, February
2012.
[6] Soheil Ziabakhsh, Meysam Zoghi,“Design of a Low-Power High-
Speed T-Flip-Flop Using the Gate-Diffusion Input Technique”,17th
Telecommunications forum TELFOR, Serbia, Belgrade, Nov. 24-26,
2009.
[7] A. Morgenshtein, A. Fish, I.A. Wagner,“Gate-Diffusion Input
(GDI) – A Power Efficient Method for Digital Combinatorial
Circuits”, IEEE Trans. VLSI, Vol. 10, No. 5, pp. 566-581, October
2002.
-
IJECT Vol. 6, IssuE 4, oCT - DEC 2015
w w w . i j e c t . o r g InternatIonal Journal of electronIcs
& communIcatIon technology 13
ISSN : 2230-7109 (Online) | ISSN : 2230-9543 (Print)
Saumya Pandey has received her B.Tech degree in Electronics
& Communication from Mody Institute of Technology & Science
in 2009 & M.Tech degree in VLSI Design from Indira Gandhi Delhi
Technical University for Women in 2015. Her areas of Interest
include Digital design, Low Power VLSI design.
Dr. Nidhi Goel is working as an Associate Professor in
Department of Electronics and Communication Engineering, IGDTUW.
She has done her Ph.D from IIT Roorkee, M.Tech in Digital
Communication, B.E. in Electronics & Communication. Her areas
of Interest includes Digital System Design, ASIC, Embedded Systems,
Multimedia security, Computer vision, Soft Computing
Techniques.