iitRACE: A Memory Efficient Engine for Fast Incremental Timing Analysis and Clock Pessimism Removal Chaitanya Peddawad, Aman Goel, Dheeraj B, Nitin Chandrachoodan Department of Electrical Engineering Indian Institute of Technology Madras, India 2015 IEEE/ACM International Conference on Computer Aided Design Peddawad et al. iitRACE 1 / 37
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iitRACE: A Memory Efficient Engine for Fast IncrementalTiming Analysis and Clock Pessimism Removal
Chaitanya Peddawad, Aman Goel, Dheeraj B, Nitin Chandrachoodan
Department of Electrical EngineeringIndian Institute of Technology Madras, India
2015 IEEE/ACM International Conference on Computer Aided Design
Peddawad et al. iitRACE 1 / 37
Outline
1 RecapIntroduction: STA, Incremental Timing and CPPRProblem Formulation
2 AlgorithmIncremental Timing: Identifying Incremental Cones and ResolvingDependenciesBlock-based topologically guided CPPR and Path Extraction UsingDynamic Path Reduction
3 Experimental ResultsAccuracy and Memory EfficiencyTest Coverage and Pin CoverageChallenges & Improvements
4 Conclusion
Peddawad et al. iitRACE 2 / 37
IntroductionSTA, Incremental Timing, CPPR
Faster turnaround time for timing analysis in presence of designchanges
Clock network as a source of pessimism: Need to updatepessimism-free timing information (CPPR) incrementally
Figure: Example for CPPR and incremental changes to the designPeddawad et al. iitRACE 3 / 37
IntroductionProblem Formulation
Given a circuit in standard file formats (.v , .lib , .spef , .timing)The task is to perform incremental changes to the circuit (specified in.ops) and perform timing analysis & CPPR in the affected regions usingleast time and resources
Peddawad et al. iitRACE 4 / 37
AlgorithmFlow Chart
Perform Incremental Changes
Incremental Timing :Identify Incremental ConesResolve DependenciesPre-CPPR Timing Propagation
Block Based CPPR :
Back TraversalFind CreditFront TraversalBuild NegPinList
Path Extraction
Post-CPPR Timing Propagation
Peddawad et al. iitRACE 5 / 37
AlgorithmIncremental Timing: Identifying Incremental Cones and Resolving Dependencies
Peddawad et al. iitRACE 6 / 37
Cone-end PointsEvery cone in the circuit can be associated with a unique primary outputor flip-flop input pin, henceforth referred to as Cone-end point (CEP)
u1u2
u3
u4
u5FF1
FF2 FF3
inp1 out1D Q
D QD Q
ab
ab
z a za z
a za za z
a z
buf3buf2
buf1
inv1
z
clk
a zu7
ab z
inp2
Figure: Cone-end Points: out1, FF3:D
AlgorithmIncremental Timing: Identifying Incremental Cones and Resolving Dependencies
Identifying Incremental CEPs
u1u2
u3
u4
u5FF1
FF2 FF3
inp1 out1D Q
D QD Q
ab
ab
z a za z
a za za z
a z
buf3buf2
buf1
inv1
z
clk
inp2
a zu7
ab z
Figure: Adding a gate to the circuit
Peddawad et al. iitRACE 7 / 37
AlgorithmIncremental Timing: Identifying Incremental Cones and Resolving Dependencies
Identifying Incremental CEPs
u1u2
u3
u4
u5FF1
FF2 FF3
inp1 out1D Q
D QD Q
ab
ab
z a za z
a za za z
a z
buf3buf2
buf1
inv1
z
clk
inp2
a zu7
ab z
Figure: Adding a gate to the circuit: Disconnect net from u4:z
Peddawad et al. iitRACE 8 / 37
AlgorithmIncremental Timing: Identifying Incremental Cones and Resolving Dependencies
Identifying Incremental CEPs
u1u2
u3
u4
u5FF1
FF2 FF3
inp1 out1D Q
D QD Q
ab
ab
z a za z
a za za z
a z
buf3buf2
buf1
inv1
z
clk
inp2
a zu7
ab z
u6a z
Figure: Adding a gate to the circuit: insert u6
Peddawad et al. iitRACE 9 / 37
AlgorithmIncremental Timing: Identifying Incremental Cones and Resolving Dependencies
Identifying Incremental Nets
u1u2
u3
u4
u5FF1
FF2 FF3
inp1 out1D Q
D QD Q
ab
ab
z a za z
a za za z
a z
buf3buf2
buf1
inv1
z
clk
inp2
a zu7
ab z
u6a z
31
2
Figure: Adding a gate to the circuit: insert net 3 & connect net 3 to u4:z
Peddawad et al. iitRACE 10 / 37
AlgorithmIncremental Timing: Identifying Incremental Cones and Resolving Dependencies
Peddawad et al. iitRACE 11 / 37
Identifying Incremental Nets
A net and associated timing information at its i/o pins may bedependent on the parameters of another incremental net
Updating the values is only possible once we resolve thedependencies between incremental nets
ab z
u6
ab a zz
original incremental change
XOR2_X1
u1u2
u3
u4
u5
u6
FF1
FF2 FF3
inp1 out1D Q
D QD Q
ab
ab a z
z a za z
a za za z
a z
buf3buf2
buf1
inv1
z
clk
inp2
a zu7
12 3
ICC
ab z
XOR2_X1
Figure: Incremental Nets
AlgorithmIncremental Timing: Identifying Incremental Cones and Resolving Dependencies
Peddawad et al. iitRACE 12 / 37
Resolving Dependencies
Find a set of incrementally affected & independent nets: Based on amodified version of Breadth-First Search Algorithm
Identify net 1 & 2 as independent nets & FF3:D as incremental CEP
Cone of FF3:D is hence an incremental cone of change (ICC)
ab z
u6
ab a zz
original incremental change
XOR2_X1
u1u2
u3
u4
u5
u6
FF1
FF2 FF3
inp1 out1D Q
D QD Q
ab
ab a z
z a za z
a za za z
a z
buf3buf2
buf1
inv1
z
clk
inp2
a zu7
12 3
ICC
ab z
XOR2_X1
Figure: Nets 1, 2, 3: Incremental Nets 1 & 2: Dependencies resolved
AlgorithmIncremental Timing: Incremental AT/RAT/Slack Update
Peddawad et al. iitRACE 13 / 37
Pre-CPPR Timing Propagation in ICC
Update AT by single block-based front traversal: start with net 1 & 2
Update RAT/Slack by back traversal from incremental CEPs (FF3:D)
Static run (full circuit) vs incremental run (only ICC)
ab z
u6
ab a zz
original incremental change
XOR2_X1
u1u2
u3
u4
u5
u6
FF1
FF2 FF3
inp1 out1D Q
D QD Q
ab
ab a z
z a za z
a za za z
a z
buf3buf2
buf1
inv1
z
clk
inp2
a zu7
12 3
ICC
ab z
XOR2_X1
Figure: Timing propagation in ICC
AlgorithmBlock-based topologically guided CPPR
Peddawad et al. iitRACE 14 / 37
Step 1 - Back Traversal
Block based levelised back traversal from a CEP till a FF or PI
Concept of criticalAT & criticalRAT
Setting RAT (pre-CPPR) and criticalRAT at pins encountered andmarking the cone
u2
u3
u4
u5
u6
FF1
FF2
FF3
inp1
out1
D Qabc
z D Q
D Q
ab
ab a z
z
a z
a za za z
a z
buf3buf2
buf1
inv1
z
clkcp13
cp23
ck
ck
ck
ab z
u1
Figure: CPPR Algorithm - Back traversal from FF3:D
AlgorithmBlock-based topologically guided CPPR
Peddawad et al. iitRACE 15 / 37
Step 1 - Back Traversal
Block based levelised back traversal from a CEP till a FF or PI
Concept of criticalAT & criticalRAT
Setting RAT (pre-CPPR) and criticalRAT at pins encountered andmarking the cone
u2
u3
u4
u5
u6
FF1
FF2
FF3
inp1
out1
D Qabc
z D Q
D Q
ab
ab a z
z
a z
a za za z
a z
buf3buf2
buf1
inv1
z
clkcp13
cp23
ck
ck
ck
ab z
u1
Figure: CPPR Algorithm - Back traversal from FF3:D
AlgorithmBlock-based topologically guided CPPR
Peddawad et al. iitRACE 16 / 37
Step 2 - Identifying Common Points & Finding Credits
Identifying common point of data path and clock path for each pairof launching and capturing FFs: cp13, cp23
u2
u3
u4
u5
u6
FF1
FF2
FF3
inp1
out1
D Qabc
z D Q
D Q
ab
ab a z
z
a z
a za za z
a z
buf3buf2
buf1
inv1
z
clkcp13
cp23
ck
ck
ck
ab z
u1
Figure: CPPR Algorithm - Identifying Common Points
AlgorithmBlock-based topologically guided CPPR
Peddawad et al. iitRACE 17 / 37
Step 2 - Identifying Common Points & Finding Credits
Credit at a launching FF can be found using eqn -
credithold = atLcp − atEcp
creditsetup = atLcp − atEcp − (atLclk src − atEclk src)
u2
u3
u4
u5
u6
FF1
FF2
FF3
inp1
out1
D Qabc
z D Q
D Q
ab
ab a z
z
a z
a za za z
a z
buf3buf2
buf1
inv1
z
clkcp13
cp23
ck
ck
ck
ab z
u1
Figure: CPPR Algorithm - Finding Credits
AlgorithmBlock-based topologically guided CPPR
Peddawad et al. iitRACE 18 / 37
Step 3 - Updating fakeAT
fakeAT: Adjust AT values to carry credit information at a pin
fake atL(E)FF :Q = at
L(E)FF :Q ∓ creditL(E)
u2
u3
u4
u5
u6
FF1
FF2
FF3
inp1
out1
D Qabc
z D Q
D Q
ab
ab a z
z
a z
a za za z
a z
buf3buf2
buf1
inv1
z
clkcp13
cp23
ck
ck
ck
ab z
u1
Figure: CPPR Algorithm - Setting fakeAT at output of launching FFs
AlgorithmBlock-based topologically guided CPPR
Peddawad et al. iitRACE 19 / 37
Step 4 - Front Traversal
Block-based levelised front traversal within the colored cone
Propagate fakeAT with setting criticalAT
fakeAT propagation ensures propagation of worst post-CPPR slack
u2
u3
u4
u5
u6
FF1
FF2
FF3
inp1
out1
D Qabc
z D Q
D Q
ab
ab
a z
z
a z
a za za z
a z
buf3buf2
buf1
inv1
z
clkcp13
cp23
ck
ck
ck
a
bz
u1
Figure: CPPR Algorithm - Front Traversal
AlgorithmBlock-based topologically guided CPPR
Peddawad et al. iitRACE 20 / 37
Step 4.1 - Building NegPinList During Front Traversal
Find the updated slacks using fakeAT and RAT values
NegPinList & Global Path Table (GPT): Initially empty !
Add failing pins to NegPinList
NegPinListPins Slack
u1:aL -33
u1:bL -25
u4:bL -15
u2
u3
u4
u5
u6
FF1
FF2
FF3
inp1
out1
D Qabc
z D Q
D Q
ab
ab
a z
z
a z
a za za z
a z
buf3buf2
buf1
inv1
z
clkcp13
cp23
ck
ck
ck
a
bz
u1
Figure: CPPR Algorithm - Building NegPinList
AlgorithmBlock-based topologically guided CPPR
Peddawad et al. iitRACE 21 / 37
Step 4.1 - Building NegPinList During Front Traversal
Find the updated slacks using fakeAT and RAT values
NegPinList & Global Path Table (GPT): Initially empty !
Add failing pins to NegPinList
NegPinListPins Slack
u1:aL -33
u1:bL -25
u4:bL -15
u2:bL -28
u2:aE -13
u3:aL -23
u4:aL -33
u5:aL -28
u5:aE -13
u5:bL -23
u5:cL -33
FF3:DL -33
FF3:DE -13
u2
u3
u4
u5
u6
FF1
FF2
FF3
inp1
out1
D Qa
b
c
z D Q
D Q
ab
a
ba z
z
az
a za za z
a z
buf3buf2
buf1
inv1
z
clkcp13
cp23
ck
ck
ck
a
bz
u1
Figure: CPPR Algorithm - Building NegPinList
AlgorithmPath Extraction from NegPinList of a cone
Peddawad et al. iitRACE 22 / 37
Step 5 - Extract Paths from NegPinList
u2
u3
u4
u5
u6
FF1
FF2
FF3
inp1
out1
D Qa
b
c
z D Q
D Q
ab
a
ba z
z
az
a za za z
a z
buf3buf2
buf1
inv1
z
clkcp13
cp23
ck
ck
ck
a
bz
u1
Step Path NegPinList
0 -
FF3:DL, u5:cL, u4:aL, u1:aL, u5:aL, u2:bL, u1:bL,
u5:bL, u3:aL, u4:bL, FF3:DE , u5:aE , u2:aE
AlgorithmPath Extraction from NegPinList of a cone
Peddawad et al. iitRACE 23 / 37
Step 5 - Extract Paths from NegPinList
u2
u3
u4
u5
u6
FF1
FF2
FF3
inp1
out1
D Qa
b
c
z D Q
D Q
ab
a
ba z
z
az
a za za z
a z
buf3buf2
buf1
inv1
z
clkcp13
cp23
ck
ck
ck
a
bz
u1
Step Path NegPinList
1 P1
FF3:DL, u5:cL, u4:aL, u1:aL, u5:aL, u2:bL, u1:bL,
u5:bL, u3:aL, u4:bL, FF3:DE , u5:aE , u2:aE
AlgorithmPath Extraction from NegPinList of a cone
Peddawad et al. iitRACE 24 / 37
Step 5 - Extract Paths from NegPinList
u2
u3
u4
u5
u6
FF1
FF2
FF3
inp1
out1
D Qa
b
c
z D Q
D Q
ab
a
ba z
z
az
a za za z
a z
buf3buf2
buf1
inv1
z
clkcp13
cp23
ck
ck
ck
a
bz
u1
Step Path NegPinList
2 P2
FF3:DL, u5:cL, u4:aL, u1:aL, u5:aL, u2:bL, u1:bL,
u5:bL, u3:aL, u4:bL, FF3:DE , u5:aE , u2:aE
AlgorithmPath Extraction from NegPinList of a cone
Peddawad et al. iitRACE 25 / 37
Step 5 - Extract Paths from NegPinList
u2
u3
u4
u5
u6
FF1
FF2
FF3
inp1
out1
D Qa
b
c
z D Q
D Q
ab
a
ba z
z
az
a za za z
a z
buf3buf2
buf1
inv1
z
clkcp13
cp23
ck
ck
ck
a
bz
u1
Step Path NegPinList
3 P3
FF3:DL, u5:cL, u4:aL, u1:aL, u5:aL, u2:bL, u1:bL,
u5:bL, u3:aL, u4:bL, FF3:DE , u5:aE , u2:aE
AlgorithmPath Extraction from NegPinList of a cone
Peddawad et al. iitRACE 26 / 37
Step 5 - Extract Paths from NegPinList
u2
u3
u4
u5
u6
FF1
FF2
FF3
inp1
out1
D Qa
bc
z D Q
D Q
ab
a
ba z
z
az
a za za z
a z
buf3buf2
buf1
inv1
z
clkcp13
cp23
ck
ck
ck
a
bz
u1
Step Path NegPinList
4 P4
FF3:DL, u5:cL, u4:aL, u1:aL, u5:aL, u2:bL, u1:bL,
u5:bL, u3:aL, u4:bL, FF3:DE , u5:aE , u2:aE
AlgorithmPath Extraction from NegPinList of a cone
Peddawad et al. iitRACE 27 / 37
Step 5 - Extract Paths from NegPinList
u2
u3
u4
u5
u6
FF1
FF2
FF3
inp1
out1
D Qa
b
c
z D Q
D Q
ab
a
ba z
z
az
a za za z
a z
buf3buf2
buf1
inv1
z
clkcp13
cp23
ck
ck
ck
a
bz
u1
Step Path NegPinList
5 P5
FF3:DL, u5:cL, u4:aL, u1:aL, u5:aL, u2:bL, u1:bL,
u5:bL, u3:aL, u4:bL, FF3:DE , u5:aE , u2:aE
AlgorithmPath Extraction from NegPinList of a cone
Peddawad et al. iitRACE 28 / 37
Step 5 - Extract Paths from NegPinList
u2
u3
u4
u5
u6
FF1
FF2
FF3
inp1
out1
D Qa
b
c
z D Q
D Q
ab
a
ba z
z
az
a za za z
a z
buf3buf2
buf1
inv1
z
clkcp13
cp23
ck
ck
ck
a
bz
u1
Step Path NegPinList
6 P6
FF3:DL, u5:cL, u4:aL, u1:aL, u5:aL, u2:bL, u1:bL,
u5:bL, u3:aL, u4:bL, FF3:DE , u5:aE , u2:aE
AlgorithmPath Extraction from NegPinList of a cone
Peddawad et al. iitRACE 29 / 37
Paths Skipped
Name Slack Mode Path
P7 -20 LFF2:Q→u1:b→u1:z→u2:b→u2:z→ u5:a→u5:z→FF3:D
P8 -15 LFF2:Q→u1:b→u1:z→u3:a→u3:z→ u5:b→u5:z→FF3:D
u2
u3
u4
u5
u6
FF1
FF2
FF3
inp1
out1
D Qa
b
c
z D Q
D Q
ab
a
ba z
z
az
a za za z
a z
buf3buf2
buf1
inv1
z
clkcp13
cp23
ck
ck
ck
a
bz
u1
P7
P8
Figure: Path Extraction - Paths skipped
AlgorithmPath Extraction from NegPinList of a cone
Peddawad et al. iitRACE 30 / 37
Paths Extraction: Redundant Paths
None of the pins in path P7 (or P8) have P7 (P8) as worst paththrough them in the cone under consideration
It is highly probable that correcting only the reported paths (P1 toP6) would correct the skipped paths (P7 and P8) as well
u2
u3
u4
u5
u6
FF1
FF2
FF3
inp1
out1
D Qa
b
c
z D Q
D Q
ab
a
ba z
z
az
a za za z
a z
buf3buf2
buf1
inv1
z
clkcp13
cp23
ck
ck
ck
a
bz
u1
P7
P8
Figure: Path Extraction - Paths skipped
AlgorithmPath Extraction from NegPinList of a cone
Peddawad et al. iitRACE 31 / 37
Paths Extraction: Redundant PathsMost importantly, our proposed algorithm ensures that for every path thatis reported, this path is the most critical for some pin in the path, forsome logic cone in the circuit. This is not ensured by regular algorithmsthat report the N worst paths in a circuit, due to which such algorithmstypically report many paths that are in some sense redundant
u2
u3
u4
u5
u6
FF1
FF2
FF3
inp1
out1
D Qa
b
c
z D Q
D Q
ab
a
ba z
z
az
a za za z
a z
buf3buf2
buf1
inv1
z
clkcp13
cp23
ck
ck
ck
a
bz
u1
P7
P8
Figure: Path Extraction - Paths skipped
Experimental ResultsAccuracy and Memory Efficiency
Peddawad et al. iitRACE 32 / 37
TAU Results: Comparison of iitRACE With Other Academic Timers
Average value accuracy 99% with the least memory requirement !(Average 2X lower than the first place timer)
478
3585
3771
5
3815
8
45.3K
138.9K
139.5K
147.6K
161.7K
171.3K
255.3K
259.1
1247
.8K
1496
.7K
1616
.4K
#Gates
0
5
10
15
20
25
30
35
40
45
50
Mem
ory
(GB)
Memory (GB) vs #GatesiitRACEUI-Timer 2.0iTimerC 2.0
Figure: Memory Usage Comparison
Memory peaks: corner cases
On the fly interconnect delaycomputation
Pin slack, criticalAT,criticalRAT as the only implicitrepresentation of path
Experimental ResultsTest Coverage
Coverage
A measure of the number of unique CEPs among the pins in the setof worst paths
Higher coverage: Our algorithm typically captures a much largernumber of such CEPs than the actual N worst paths in the circuit
Beneficial in identifying all the failing cones
Peddawad et al. iitRACE 33 / 37
Experimental ResultsTest Coverage
10 50 100 500 1K 5K 10KPath Count
01020304050607080
# U
nique CEPs
b19
iitRACEiTimerC 2.0
10 50 100 500 1K 5K 10KPath Count
01020304050607080
# U
nique CEPs
cordic
iitRACEiTimerC 2.0
10 50 100 500 1K 5K 10KPath Count
0
50
100
150
200
250
300
# U
nique CEPs
des_perf
iitRACEiTimerC 2.0
10 50 100 500 1K 5K 10KPath Count
01020304050607080
# U
nique CEPs
mgc_edit_dist
iitRACEiTimerC 2.0
#Unique CEPs vs #Paths
Figure: Test coverage comparison against actual top N worst paths
Higher coverage of pins: aid to identify critical regions
Peddawad et al. iitRACE 34 / 37
Experimental ResultsPost-contest Improvements in Performance Without Compromising the Accuracy
Post-Contest Speed-up: 10X !
MMR (GB) CPU (s)Benchmark C Post-C C Post-C
b19 3.02 3.33 426 132cordic 0.87 0.84 60 31des perf 4.19 1.74 189 94edit dist 1.98 2.16 562 84fft 2.38 0.63 44 26leon2 9.92 12.4 13800 582leon3mp 8.20 10.17 4920 463mgc edit dist 1.82 2.14 566 79mgc matrix mult 2.01 2.37 239 82netcard 9.33 11.6 3800 516tau cordic core 0.27 0.21 8 7tau crc32d16N 0.11 0.11 1 1tau softusb navre 0.19 0.2 13 7tau tip master 0.63 0.65 39 18vga lcd 1 13.22 2.76 742 409vga lcd 2 1.54 1.76 243 64Total 59.68 53.07 25680 2590
MMR: Maximum Memory Requirement, CPU: Runtime (s)C: Contest, Post-C: Post-Contest
Resolved the memory peaks:corner cases
Cut-off technique: search spacereduction
Algorithmic optimization: sparsetable implementation for findinglowest common ancestor(common point), improvementin incremental circuit connection
Multithreading: parallelprocessing of the cones
Peddawad et al. iitRACE 35 / 37
Conclusion
Proposed a novel memory efficient incremental timing analysistechnique with block-based CPPR framework
The approach is rooted from a highly practical perspective, in whichwe accurately report only non-redundant critical paths
Significantly higher coverage of cone-end points corresponding tocritical paths than regular algorithms for worst path reporting. Thiscan be used by the designers as an additional aid to identify criticalareas in the circuit from a path correction perspective
Future extensions: static/incremental statistical timing analysis
Peddawad et al. iitRACE 36 / 37
Acknowledgements
TAU 2015 Contest Organizers- Jin Hu, IBM Corp.- Greg Schaeffer, IBM Corp.- Vibhor Garg, Cadence
We would also like to thank the authors of UI-Timer 2.0 and iTimerC2.0 for sharing their timer binaries of TAU 2015 Contest
Peddawad et al. iitRACE 37 / 37
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