III-V’s: III V s: From THz HEMT to CMOS J. A. del Alamo and D.-H. Kim 1 Microsystems Technology Laboratories, MIT 1 presently with Teledyne Scientific 2009 Topical Workshop on Heterostructure Microelectronics Sponsors: Intel, FCRP-MSD Acknowledgements: August 25-28, 2009 1 Acknowledgements: Niamh Waldron, Tae-Woo Kim, Donghyun Jin, Ling Xia, Dimitri Antoniadis, Robert Chau MTL, NSL, SEBL
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III-V’s:III V s: From THz HEMT to CMOS
J. A. del Alamo and D.-H. Kim1
Microsystems Technology Laboratories, MIT1presently with Teledyne Scientific
2009 Topical Workshop on Heterostructure Microelectronics
Sponsors: Intel, FCRP-MSD
Acknowledgements:
August 25-28, 2009
1
Acknowledgements:
Niamh Waldron, Tae-Woo Kim, Donghyun Jin, Ling Xia,
Dimitri Antoniadis, Robert Chau
MTL, NSL, SEBL
Outline
• Introduction
• Near-THz III-V HEMTs
• Logic characteristics of III-V HEMTs
• III-V CMOS
• Conclusions
2
The High Electron Mobility Transistor
3Mimura, JJAPL 1980
Modulation doping
• High electron mobility in modulation-doped AlGaAs/GaAs heterostructures
• 2 DEG at AlGaAs/GaAs interface
Dingle, APL 1978Stormer, Solid St
4
Comm 1979
HEMT circuits
27-stage ring oscillator
E/D logic
“The switching delay of 17 1 ps is the lowest of all17.1 ps is the lowest of all the semiconductor logic technologies reported thus f ”
5
Mimura, JJAPL 1981far.”
HEMTs in other material systems
InAlAs/InGaAs on InP AlGaAs/InGaAs PHEMT
K tt EDL 19851982 Ketterson, EDL 1985Kastalsky, APL 1982
Also in AlGaN/GaN, Si/SiGe, AlSb/InAs, etc
6
Also with holes in many heterojunction systems
HEMT Electronics: “You’ve come a long way baby!”ou e co e a o g ay baby
77
Near THz HEMTs
• fT vs time:800
800
800
800800
800
800
800 Kim EDL 2008
600
GH
z] 600
GH
z] 600
GH
z] 600
GH
z]III-V HBTs
III-V HEMTs600
GH
z] 600
GH
z] 600
GH
z] 600
GH
z]III-V HBTs
III-V HEMTs
400
eque
ncy
[G
400
eque
ncy
[G
400
eque
ncy
[G
400
eque
ncy
[G
400
eque
ncy
[G
400
eque
ncy
[G
400
eque
ncy
[G
400
eque
ncy
[G
200
Cut
off F
re
200
Cut
off F
re
200
Cut
off F
re
200
Cut
off F
re
SiGe HBTs
200
Cut
off F
re
200
Cut
off F
re
200
Cut
off F
re
200
Cut
off F
re
SiGe HBTs
1985 1990 1995 2000 2005 20100
Year1985 1990 1995 2000 2005 20100
Year1985 1990 1995 2000 2005 20100
Year1985 1990 1995 2000 2005 20100
Year
Si CMOSSiGe HBTs
1985 1990 1995 2000 2005 20100
Year1985 1990 1995 2000 2005 20100
Year1985 1990 1995 2000 2005 20100
Year1985 1990 1995 2000 2005 20100
Year
Si CMOSSiGe HBTs
8
YearYearYearYearYearYearYearYear
For over 20 years, fT (III-V’s) > fT (Si)
Near THz HEMTs
• fT vs fmax:1000
max ffτ
300 400 500 600 700 = favg =
800
1000 MIT HEMTs III-V HEMTs III-V HBTs
maxτavg
400
600
ax [
GH
z ] Kim IEDM 2008
200
400f m
0 200 400 600 800 10000
fT [ GHz ]
9III-V HEMT: only device with ft, fmax>600 GHz
III-Vs for CMOS?
• Si scaling running into increasing difficulties:
3
< Historical >< Extrapolated >
33
< Historical >< Extrapolated >
The scaled Si CMOS “performance gap”
3
< Historical >< Extrapolated >
33
< Historical >< Extrapolated >
33
< Historical >< Extrapolated >
33
< Historical >< Extrapolated >
The scaled Si CMOS “performance gap”Courtesy of Dimitri Antoniadis (MIT)x 10-15
n)
GS D
1 5
2
2.5
Del
ay (p
s)
< Historical >< Extrapolated >
1 5
2
2.5
Del
ay (p
s)
1 5
2
2.5
Del
ay (p
s)
< Historical >< Extrapolated >
1 5
2
2.5
Del
ay (p
s)
< Historical >< Extrapolated >
1 5
2
2.5
Del
ay (p
s)
1 5
2
2.5
Del
ay (p
s)
< Historical >< Extrapolated >
1 5
2
2.5
Del
ay (p
s)
1 5
2
2.5
Del
ay (p
s)
< Historical >< Extrapolated >
1 5
2
2.5
Del
ay (p
s)
1 5
2
2.5
Del
ay (p
s)
< Historical >< Extrapolated >
1
rge
(C/m
icro
“parasitic” charge
“15 nm” target0.5
1
1.5
Intr
insi
c
“15 nm” target0.5
1
1.5
Intr
insi
c
0.5
1
1.5
Intr
insi
c
“15 nm” target0.5
1
1.5
Intr
insi
c
“15 nm” target0.5
1
1.5
Intr
insi
c
0.5
1
1.5
Intr
insi
c
“15 nm” target0.5
1
1.5
Intr
insi
c
0.5
1
1.5
Intr
insi
c
“15 nm” target0.5
1
1.5
Intr
insi
c
0.5
1
1.5
Intr
insi
c
0.5
Gat
e C
hachannel charge
15 nm target
0 20 40 60 80 100 1200
CMOS Generation (nm)
15 nm target
0 20 40 60 80 100 1200
CMOS Generation (nm)0 20 40 60 80 100 120
0
CMOS Generation (nm)
15 nm target
0 20 40 60 80 100 1200
CMOS Generation (nm)
15 nm target
0 20 40 60 80 100 1200
CMOS Generation (nm)0 20 40 60 80 100 120
0
CMOS Generation (nm)
15 nm target
0 20 40 60 80 100 1200
CMOS Generation (nm)0 20 40 60 80 100 120
0
CMOS Generation (nm)
15 nm target
0 20 40 60 80 100 1200
CMOS Generation (nm)0 20 40 60 80 100 120
0
CMOS Generation (nm)0 20 40 60 80 100 1200
CMOS Generation (nm)
10
Parasitics becoming overwhelming need higher current
Transistor as switchIn logic applications transistor operates as switch
Interested in:
• ON current (ION)
• OFF current (IOFF)( OFF)
• VT
• VT dependence on Lgg
• VT dependence on VDS (DIBL)
• Subthreshold swing (S)
• Device footprint
• Gate capacitance
1111
• Operating voltage (VDD)
How Do III-V FETs Look for Logic?
Logic Characteristics of InGaAs High-Electron Mobility Transistor
Kim, IEDM 2006
Lg ~ 60 nm
Source Drainsource draingateSubstrate is InPSource
• Can we make 15 nm-class III-V MOSFETs with higher performance than equivalent Si devices?
Wh t i t d b t th t d i ?• What are we going to do about the p-type devices?
• Will III-V MOSFETs be reliable?• Will III-V MOSFETs be reliable?
• Will III-V CMOS be ready on time?y
3737
Conclusions
• III-Vs attractive for CMOS
• III-V CMOS will strongly leverage Sirather than “beyond Silicon” a III V channel will be an add on to Sirather than beyond Silicon , a III-V channel will be an add-on to Si
technology (as Cu, strain and high-K dielectrics have been in the past)
• Great challenges ahead: – Growth of III-V heterostructures on Si with thin buffer layers– Stable and reliable high-K/III-V interface with high interfacial qualityg g q y– Nanometer-scale, self-aligned, E-mode FET architecture– High quality p-channel device