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1898 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 53, NO. 6, DECEMBER 2006

Research on Hybrid-ClampedMultilevel-Inverter Topologies

Alian Chen and Xiangning He, Senior Member, IEEE

AbstractThe concept of hybrid clamped is proposed inmultilevel-inverter topologies, and a hybrid-clamped multilevel-inverter topology comprising active and passive clamping devicesis presented in this paper. In this topology, the dc-link capacitorvoltages can be balanced without additional circuitry or separateddc voltage sources, regardless of load characteristics. It can beused in real and reactive power conversion applications. Thetopology structure, operating principle, and self-voltage balancingability are analyzed. In addition, the validity is confirmed bysimulations and experiments based on a five-level inverter. Finally,the functions of different clamping devices are compared.

Index TermsHybrid clamped, multilevel inverter, neutral-

point voltage balancing, topology.

I. INTRODUCTION

MULTILEVEL inverters have been a research hotspot

in high-voltage and high-power applications in recent

years. Generally speaking, diode-clamped, flying-capacitor,

and cascaded multilevel converters are three basic multilevel

topologies [1], [2]. To synthesize multilevel output, voltage

clamping is one of the most important issues. The meaning

of clamping is to limit the switchs terminal voltage in a

suitable range by using clamping devices. In the three ex-

isting multilevel-inverter topologies, it can be seen through

their names that voltages are clamped by diodes in thediode-clamped multilevel inverter, by capacitors in the flying-

capacitor multilevel inverter, and by separated voltage sources

in the cascaded multilevel topology with separated voltage

sources. However, the three topologies have some disadvan-

tages in real applications.

The diode-clamped multilevel inverter needs separated dc

sources or complex control methods when a real power is

delivered [2], [3]. Although the flying-capacitor inverter can

be used in both real and reactive power conversions, it is

difficult to balance the capacitor voltages when it is used

for reactive power compensation [4]. The cascaded multilevel

inverter needs separated voltage sources; therefore, they aremore suitable for renewable energy sources such as fuel cell,

photovoltaic, biomass, etc.

To overcome the above disadvantages, it is an instructive idea

to find new multilevel-inverter topologies with higher perfor-

Manuscript received December 23, 2004; revised June 14, 2005. Abstractpublished on the Internet September 15, 2006. This work was supported by theNational Nature Science Foundation of China (50277035). Parts of this paperwere presented at IEEE PESC, Aachen, Germany, June 2004.

The authors are with the College of Electrical Engineering, ZhejiangUniversity, Hangzhou 310027, China (e-mail: [email protected];[email protected]).

Digital Object Identifier 10.1109/TIE.2006.885154

Fig. 1. Five-level circuit proposed in [5].

mance by changing clamping devices. All the three existingmultilevel inverters use only one type of clamping devices in

one topology. If two or more types of clamping devices are used

in one topology, a series of new multilevel-inverter topologies

can be derived. This is also the concept of the hybrid-clamped

method.

II. EXISTING HYBRID-C LAMPED

MULTILEVEL-I NVERTER TOPOLOGIES

A topology clamped by diodes and capacitors was proposed

in [5], and one leg of a five-level topology is shown in Fig. 1.

The purpose of the topology is to solve the problems of dc-link

capacitor voltages unbalancing and higher blocked voltagesof the inner switches in traditional diode-clamped multilevel

inverters. Compared with the diode-clamped multilevel-inverter

topology, the functions of the added clamping capacitors are as

follows: 1) providing blocked voltages for the inner switches

at turn-off; 2) providing bidirectional current paths; and

3) realizing the dc-link capacitor voltage balancing. This topol-

ogy is similar to the flying-capacitor topology in which the

clamping capacitors contribute to the voltage synthesis. Both

of the two topologies use redundant switching states of the

middle voltage levels to balance the capacitor voltages. For the

same reason as the flying-capacitor multilevel converter, this

hybrid-clamped multilevel converter topology cannot keep the

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CHEN AND HE: RESEARCH ON HYBRID-CLAMPED MULTILEVEL-INVERTER TOPOLOGIES 1899

Fig. 2. Generalized five-level circuit proposed in [6].

capacitor voltages balancing in pure reactive conversions and is

not suitable for reactive power compensation.

A generalized multilevel converter topology with self-

voltage balancing shown in Fig. 2 was proposed in [6]. This

topology is clamped by active and passive devices, and it can be

used in real and reactive power conversions regardless of load

characteristics. However, it requires a large number of devices.

A novel topology with neutral-point voltage balancing ability

is proposed in this paper, which has the same advantages as

the topology shown in Fig. 2, but requires much fewer devices.

Fig. 3 shows one leg of the proposed five-level topology.

This paper analyzes the structure characteristics and operating

principle of the proposed topology in detail and discusses

the realization of the neutral-point voltage balancing. Also,

the clamping mechanism of switching devices and diodes is

analyzed. Finally, the functions of different clamping devices

are summarized.

III. STRUCTURE CHARACTERISTICS AND

OPERATING PRINCIPLE

A. Structure Characteristics

Fig. 3 shows one leg of the proposed hybrid-clamped five-

level inverter. In this topology, switching devices Sa1Sa4 and

Sa1Sa4 are the main switching devices used to produce thedesired output voltage. Sc1Sc6 are the clamping switching

devices, and Dc1Dc12 are the clamping diodes. The switching

devices Sc1Sc6 and the auxiliary capacitors C5C7 maintain

the dc-link capacitor voltages in balance. It can be seen fromFig. 3 that only the clamping devices nearest to the dc side are

Fig. 3. One leg of the proposed hybrid-clamped five-level inverter.

active switches with antiparalleled diodes, while others are only

diodes. Also, only the flying capacitors nearest to dc side are

remained. This topology is easy to be expanded to any voltagelevels. For one leg of this M-level topology, (M 1) dc-link

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TABLE IRELATIONSHIP BETWEEN OUTPUT VOLTAGE UO AN D SWITCHING STATES

capacitors, 2(M 1) main switching devices, 2(M 2)clamping switching devices, (M 1) (M 2) clampingdiodes, and (M 2) auxiliary capacitors are needed. All thecapacitors sustain the same voltage, and all the switching

devices and diodes have the same voltage stresses.

B. Multilevel Synthesis Principle

Similar to the topology in Fig. 2, redundant switching states

exist for middle voltage levels in the proposed hybrid-clamped

topology. The multilevel synthesis principle is explained with

a five-level circuit as an example. The dc bus negative pointis taken for reference. Five voltage levels are produced by the

following switching states correspondingly.

1) For voltage level U1 = 0Udc, turn on four main switchesSa4, Sa3, Sa2, Sa1 and three clamping switches Sc1,Sc3, Sc5.

2) For voltage level U2 = 1Udc, the following are the twoswitching states.

a) Turn on four main switches Sa4, Sa4, Sa3, Sa1 andthree clamping switches Sc1, Sc3, Sc5.

b) Turn on four main switches Sa1, Sa4, Sa3, Sa2 andthree clamping switches Sc2, Sc4, Sc6.

3) For voltage level U3 = 2Udc, the following are the twoswitching states.a) Turn on four main switches Sa3, Sa4, Sa4, Sa1 and

three clamping switches Sc1, Sc3, Sc5.


4) For voltage level U4 = 3Udc, the following are the twoswitching states.

a) Turn on four main switches Sa2, Sa3, Sa4, Sa1 andthree clamping switches Sc1, Sc3, Sc5.


5) For voltage level U5 = 4Udc, turn on four main switches

Sa1, Sa2, Sa3, Sa4 and three clamping switches Sc2,Sc4, Sc6.

Because (Sa1, Sc1), (Sc1, Sc2), (Sc2, Sc3), (Sc3, Sc4), (Sc4,

Sc5), (Sc5, Sc6), and (Sc6, Sa1) are in parallel with capacitorsC1, C5, C2, C6, C3, C7, and C4, respectively, they should be

complementary switching pairs, i.e., when one switch is on, the

other is off, and vice versa. The relationship between output

voltage uo and switching states is shown in Table I. Fig. 4shows bidirectional current paths corresponding to each voltage

level (only one switching state is given for redundant switching

states).

It can be seen from the above analysis that the switching

operation of a hybrid-clamped five-level inverter must comply

with the following rules.

1) For each switching state, there must be four main switch-

ing devices and three clamping switching devices on.

2) Sa1 is complementary with Sa1. Except for Sa1 and Sa1,any three adjacent main switching devices are on or off

simultaneously. Therefore, (Sa1, Sa1), (Sa2, Sa4), (Sa3,Sa3), and (Sa4, Sa2) are the complementary switch-ing pairs, i.e., if one is on, the other must be off and

vice versa.

3) Sa1 and Sc1 are complementary.

4) Any two adjacent clamping switching devices Sc1Sc6

are complementary.

IV. REALIZATION OF DC-LIN K CAPACITOR

SEL F-V OLTAGE BALANCING

The self-voltage balancing ability of the proposed topology

is realized through clamping switching devices and auxiliary

capacitors. Its principle is similar to the method used in Fig. 2.

When the multilevel converter switches from one state to an-

other, two different groups of capacitors are connected through

clamping switching devices. The difference between the two

topologies is that there are multiple capacitors in parallel for

the topology in Fig. 2, and only two capacitors in parallel

for the proposed topology. Correspondingly, the number of

clamping switches in the proposed topology is less than thatin the topology of Fig. 2. Also, all the states of the clamping

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Fig. 4. Bidirectional current paths corresponding to each voltage level. (a) U1 = 0Udc. (b) U2 = 1Udc. (c) U3 = 2Udc. (d) U4 = 3Udc. (e) U5 = 4Udc.

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Fig. 5. Carriers and modulation signals in subharmonic PWM.

switching devices can be determined from Sa1. It can be seen

from Table I that there are two switching states for each of the

middle voltage level: In one state, Sa1 is on, and in the other

state, Sa1 is off. For the state that Sa1 is on, Sc2, Sc4, and Sc6

should also be on according to the above switching operation

rules. Then, capacitors C1 and C5, C2 and C6, C3 and C7 are

in parallel, respectively, so the two parallel capacitors will be

charged and discharged to keep their voltages equal: Uc1 =Uc5, Uc2 = Uc6, Uc3 = Uc7; for the other state that Sa1 isoff, capacitors C2 and C5, C3 and C6, C4 and C7 are in parallel,

respectively, so the two parallel capacitors will be charged and

discharged to keep their voltages equal: Uc2 = Uc5, Uc3 =Uc6, Uc4 = Uc7. That is to say, the clamping capacitors canbe charged or discharged according to the voltage difference

between the two parallel capacitors. In addition, the objective

of the clamping capacitor voltage is to be a stable voltage level.

Then, all the dc-link capacitors can keep their voltages balance

through the auxiliary capacitors C4, C5, and C6.This voltage balancing method is different from the one that

utilizes redundant switching states. The redundant-switching-

state method means that by selecting two or more switching

states in one period to produce one neutral-point voltage,

in some switching states, the dc-link capacitors are charged

and in other states are discharged. Then, in one period, the

capacitor voltages can keep their balance by charging and

discharging. The typical application of this method is the phase-

shift pulsewidth modulation (PWM) used in flying-capacitor

multilevel converters [7]. However, it is difficult for the dc-link

capacitor voltages to be balanced in pure reactive applications.

In the proposed topology, the auxiliary capacitors act as inter-media, which are in parallel with different dc-link capacitors in

different switching states. Therefore, the neutral-point voltages

can be kept balance regardless of the load characteristics. In

addition, this topology can be used in real and reactive power

applications with simple control.

When the inverter works at low modulation index, the five-

level PWM may change to three-level PWM. In this case, the

capacitor voltages can also be kept balance. To indicate the

different ranges of modulation index corresponding to different

voltage levels, the subharmonic PWM is taken as an example

(Fig. 5). The four carriers are corresponding to the switching

states of Sa1, Sa2, Sa3, and Sa4, respectively from top to

bottom. This modulation is one of the switching states inTable I.

Fig. 6. Geometrical relationship between carriers and modulation signals.

In an M-level inverter, the amplitude modulation index maand the frequency ratio mf are defined as

ma =Am

(M 1)Ac(1)

mf =fcfm (2)

where Ac is the amplitude peakpeak value of triangle carriers,Am is the amplitude peakpeak value of sinusoidal waveform,fc is the carrier frequency, and fm is the modulation signalfrequency. When fc fm, the turn-on time of Sa1 in onecarrier period can be obtained with average model. Because

fc fm, the sinusoidal signal may approximates to a constantin one carrier period. Then, Fig. 5 can be redrawn as Fig. 6.

Considering the simple geometrical relationship, the following

equation can be obtained:

tc

2Tc

2

=ug 3Ac

Ac=

Am

2 sinmt + 2Ac 3Ac

Ac

=Am sinmt

2Ac 1. (3)

For five-level inverter, ma = (Am/4Ac), then from (3), theturn-on time of Sa1 in one carrier period can be seen as

tcSa1 = (2ma sinmt 1)Tc. (4)

By using the same method, the turn-on time of Sa2, Sa3, and

Sa4 in one carrier period is thus expressed as

tcSa2 = (2ma sinmt)Tc (5)

tcSa3 = (2ma sinmt + 1)Tc (6)

tcSa4 = (2ma sinmt + 2)Tc. (7)

In (4), when sinmt = 1, tcSa1, then ma = 0.5. This showsthat when ma 0.5, Sa1 is off all along and only three voltagelevels can be produced, when ma > 0.5, all the voltage levelscan be produced. This case can be seen in Fig. 5, where

ma = 0.8 is at high modulation index, ma = 0.33 is at low

modulation index, and ma = 0.5 is at critical case. For anM-level inverter, the turn-on time of Sa1 in one carrier period

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Fig. 7. Carriers combined two switching states. (a) Carriers of Sa1. (b) Carriers of Sa2. (c) Carriers of Sa3. (d) Carriers of Sa4.

tc can be obtained according to the same method, and also thecritical value of modulation index

tc =ug (M 2)Ac

Ac Tc

=Am

2sinct +

M12

Ac (M 2)AcAc

Tc

= Am sinct2Ac

M 3

2Tc

=

M 1

2ma sinct

M 3

2

Tc (8)

mac =M 3

M 1. (9)

Up to now, only one switching state is discussed. The other

switching state can also be obtained. According to Table I, the

four carriers in Fig. 5 are corresponding to the switching states

of Sa2, Sa3, Sa4, and Sa1, respectively, from top to bottom.

By combining the two switching states together, the carriers are

arranged as in Fig. 7.

From the above carriers, it can be seen that even at low mod-ulation index, Sa1 can switch from on to off when the inverter

changes from one state to another. According to the above

analysis, the capacitor voltages can be balanced. The simulated

and experimental results in the following part verified the

validity. The method proposed in [8] is also suitable for this

hybrid-clamped multilevel inverter at low modulation index.

V. CLAMPING MECHANISM OF SWITCHING

DEVICES AND DIODES

In the proposed topology, all the main switches are clamped

to the corresponding dc-link capacitors by active clampingswitches and passive clamping diodes, so the hybrid-clamped

multilevel inverter is called in this paper. Not only the main

switches are clamped to 1Udc, but also the clamping switches

and clamping diodes are clamped to 1Udc. For convenient

analysis, the topology is split into two parts, which are the

shadows shown in Fig. 8(a) and (b). The shadow in Fig. 8(a)

is an improved diode-clamped four-level inverter, which has

been analyzed in detail in [3]. Each of the main switches and

clamping diodes are clamped to C5, C6, and C7, and then they

are clamped to the corresponding dc-link capacitors according

to the switching states of clamping switches. For example, ifSc1, Sc3, and Sc5 are on, the main switches and clamping

diodes are clamped to C2, C3, and C4; if Sc2, Sc4, and Sc6

are on, the main switches and clamping diodes are clamped to

C1, C2, and C3. For the whole topology, the devices shown in

Fig. 8(a) are all clamped to the corresponding dc-link capacitors

indirectly. For the devices shown in the shadow of Fig. 8(b),

they are all clamped to the corresponding dc-link capacitors

directly. When Sa1 turns off, it is clamped to C1 directly by Sc1;

when Sc1, Sc3, and Sc5 turn off, they are clamped to C1, C2,

and C3, respectively, by Sa1, Sc2, and Sc4; when Sc2, Sc4, and

Sc6 turn off, they are clamped to C2, C3, and C4, respectively,

by Sc3, Sc5, and Sa1

; when Sa1

turns off, it is clamped to

C4 directly by Sc6. Thus, all the devices are clamped to the

corresponding dc-link capacitors by active switches and passive

diodes.

VI. SIMULATIONS AND EXPERIMENTS

To verify the validity of the proposed topology, both simu-

lations and experiments were carried out based on a five-level

single-phase half-bridge inverter. The circuit configuration of

the experiment is the same as in Fig. 3. The neutral point of

dc-link capacitors is taken as the reference point, and the output

terminal uo connects with load. The dc input voltage is supplied

by a booster/rectifier and set to 200 V. The ac output frequencyis set to 50 Hz. All the capacitors have the same capacitance

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Fig. 8. Split of the hybrid-clamped five-level inverter. (a) Indirect clamping devices. (b) Direct clamping devices.

Fig. 9. PWM generation block diagram.

of 1100 F. All the switching devices and diodes have thesame rated voltage 200 V and rated current 20 A. Subharmonic

PWM is used, and the carriers are set according to Fig. 7. In

practical realization, one switching state is produced first and

then the different signals are selected and combined in different

switching periods. The gate signals are produced by an FPGA

embedded board. The PWM generation block diagram is shown

in Fig. 9.

Fig. 10 shows the simulated waveforms with different loads

and at different modulation indexes. In Fig. 10(a)(d), a 50-resistor was used, and in Fig. 10(e)(h), a 15-mH inductor

in series with a 20- resistor was used. Fig. 11 shows theexperimental results corresponding to the similar load condi-

tions. It can be seen that the simulated and experimental results

are almost identical, which demonstrates the validity of the

topology and its neutral-point voltage balancing ability. Bycombining three similar one-leg circuits, a three-phase topology

can easily be formed. Fig. 12 shows the simulated phase and

line voltages of a three-phase inverter.

VII. DISCUSSION AND CONCLUSION

By far, active switching devices, diodes, and capacitors, all

can be used for clamping. The main functions of the clamping

devices are summarized as follows.

Diodes have the characteristics of unidirectional conduction,

so they can be used for unidirectional clamping.

Active switches are controllable devices, so they are more

flexible than diodes for clamping. A switching device with a

parallel diode can provide a bidirectional path by itself, and it

can realize main switch and flying-capacitor clamping.

Capacitors are electrical energy storage passive components,

so they can participate in voltage synthesizing and sustain themain switch blocking voltage. Also, they can be used for dc-link

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Fig. 10. Simulated results of the hybrid-clamped five-level inverter. (a) Output voltage and current for resistive loads (ma = 0.8). (b) DC-link capacitor voltages

for resistive loads (m

a = 0.

8). (c) Output voltage and current for resistive loads (m

a = 0.

33). (d) DC-link capacitor voltages for resistive loads (m

a = 0.

33).(e) Output voltage and current for inductive loads (ma = 0.8). (f) DC-link capacitor voltages for inductive loads (ma = 0.8). (g) Output voltage and current forinductive loads (ma = 0.33). (h) DC-link capacitor voltages for inductive loads (ma = 0.33).

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Fig. 11. Experimental results of the hybrid-clamped five-level inverter. (a) Output voltage and current for resistive loads (ma = 0.8). (b) DC-link capacitor

voltages for resistive loads (m

a = 0.

8). (c) Output voltage and current for resistive loads (m

a = 0.

33). (d) DC-link capacitor voltages for resistive loads(ma = 0.33). (e) Output voltage and current for inductive loads (ma = 0.8). (f) DC-link capacitor voltages for inductive loads (ma = 0.8). (g) Output voltageand current for inductive loads (ma = 0.33). (h) DC-link capacitor voltages for inductive loads (ma = 0 .33).

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Fig. 12. Simulated results of the three-phase hybrid-clamped five-level in-verter. (a) Phase voltages. (b) Line voltages.

capacitor voltage balancing by charging and discharging or

clamping.

All the three types of devices can be used for clamping.

With the different places in the topology, they may change their

effects correspondingly. Considering the functions replacementamong different clamping devices and based on the concept of

hybrid clamped, a series of novel multilevel converter topolo-

gies can be deduced. The concept of hybrid clamped provides a

new clew for constructing more multilevel converter topologies.

A novel hybrid-clamped multilevel inverter with self-voltage

balancing is proposed and researched in detail in this paper,

which is clamped together by active and passive devices.

Although some clamping switching devices are needed, the

novel topology can be used in real and reactive power con-

versions with easy control and without any additional circuits.

The operating principle and dc-link capacitor voltage-balancing

ability are studied, and the validity is proved by simulated andexperimental results.

ACKNOWLEDGMENT

The authors would like to thank L. Hu for his valuable

suggestions and discussions as well as the help in experimental

work.

REFERENCES

[1] J.-S. Lai and F. Z. Peng, Multilevel convertersA new breed of powerconverters, IEEE Trans. Ind. Appl., vol. 32, no. 3, pp. 509517, May/Jun.1996.

[2] F. Z. Peng, J.-S. Lai, J. McKeever, and J. A. VanCoevering, Multilevelvoltage-source converter system with balanced DC voltages, in Proc.

IEEE PESC, 1995, pp. 11441150.[3] X. Yuan and I. Barbi, Fundamentals of a new diode clamping multi-

level inverter, IEEE Trans. Power Electron., vol. 15, no. 4, pp. 711718,Jul. 2000.

[4] X. Yuan, H. Stemmler, and I. Barbi, Investigation on the clamping volt-age self-balancing of the three-level capacitor clamping inverter, in Proc.

IEEE PESC, 1999, pp. 491496.[5] B.-S. Suh and D.-S. Hyun, A new N-level high voltage inversion system,

IEEE Trans. Ind. Electron., vol. 44, no. 1, pp. 107115, Feb. 1997.[6] F. Z. Peng, A generalized multilevel inverter topology with self voltage

balancing, IEEE Trans. Ind. Appl., vol. 37, no. 2, pp. 611618, Mar./Apr.2001.

[7] T. A. Meynard and H. Foch, Multi-level conversion: High voltagechoppers and voltage-source inverters, in Proc. IEEE PESC, 1992,pp. 397403.

[8] L. M. Tolbert, F. Z Peng, and T. G. Habetler, Multilevel PWM methodsat low modulation indices, IEEE Trans. Power Electron., vol. 15, no. 4,pp. 719725, Jul. 2000.

Alian Chen was born in Shandong Province, China,in 1976. She received the B.Sc. and M.Sc. degreesfrom Shandong University, Jinan, China, in 1998 and2000, respectively. She is currently working towardthe Ph.D. degree in power electronics at ZhejiangUniversity, Hangzhou, China.

Her research interests are in power electronics andtheir industrial applications.

Xiangning He (M96SM96) received the B.Sc.and M.Sc. degrees from Nanjing University of Aero-nautical and Astronautical, Nanjing, China, in 1982and 1985, respectively, and the Ph.D. degree fromZhejiang University, Hangzhou, China, in 1989.

From 1985 to 1986, he was an Assistant Engi-neer with the 608 Institute of Aeronautical IndustrialGeneral Company, China. From 1989 to 1991, hewas a Lecturer with Zhejiang University. In 1991,he obtained a Fellowship from the Royal Societyof U.K., and conducted research in the Department

of Computing and Electrical Engineering, Heriot-Watt University, Edinburgh,U.K., as a Postdoctoral Research Fellow for two years. In 1994, he joinedZhejiang University as an Associate Professor. Since 1996, he has been a Full

Professor with the Department of Electrical Engineering. He is the Directorof the Power Electronics Research Institute, Zhejiang University. His researchinterests are in power electronics and their industrial applications.

Dr. He received the 1989 Excellent Ph.D. Graduate Award, the 1995 ElitePrize Excellence Award, and the 1996 Outstanding Young Staff Member Awardfrom the Zhejiang University for his teaching and research contributions. Hereceived three Scientific and Technological Progress Awards (two in 1998and one in 2002) from the Zhejiang Provincial Government and the StateEducational Ministry of China, respectively, and four Excellent Paper Awards.He is a Fellow of the Institution of Electrical Engineers (IEE), U.K.

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