IEEE EMC Society Distinguished Lecturer Seminar: IEEE EMC Society Distinguished Lecturer Seminar: IEEE EMC Society Distinguished Lecturer Seminar: Power Integrity of SiP (System In Package) IEEE EMC Society Distinguished Lecturer Seminar: Power Integrity of SiP (System In Package) July 21 2010 July 21, 2010 Joungho Kim at KAIST joungho@ee kaist ac kr joungho@ee.kaist.ac.kr http://tera.kaist.ac.kr Terahertz Interconnection and Package Laboratory TERA Terahertz Interconnection and Package Laboratory 1
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IEEE EMC Society Distinguished Lecturer Seminar…web.mst.edu/~jfan/slides/Kim_Power_Integrity_July21_2010_2.pdf · Contents I. Needs of SiP II. Power Integrity of SiP III. PDN Di
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IEEE EMC Society Distinguished Lecturer Seminar:IEEE EMC Society Distinguished Lecturer Seminar:IEEE EMC Society Distinguished Lecturer Seminar:Power Integrity of SiP (System In Package)
IEEE EMC Society Distinguished Lecturer Seminar:Power Integrity of SiP (System In Package)
16 x 100nF Discrete Capacitors TM02/20 ModeResonance (5cm x 5cm)
0
10da
nce
[dB (Thickness : 12μm, DK : 4.6) – “C”
With Thin Film Embedded Capacitor(Thickness : 10μm, DK : 25) – “E”
-20
-10
ound
Impe Significant Improvement over GHz
With Thin Film Embedded Capacitor
-40
-30
Pow
er/G
ro
Improvement at low frequency rangewith High DK Embedded Material
-501 10 100 1000 3000
Frequency [MHz]
P with High-DK Embedded Material
Significant improvement over GHz with Thin Film Embedded Capacitor (Very low ESL of Embedded Capacitor)More improvement at low frequency range with high-DK embedded capacitor (More Capacitance)
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Measured SSN (No De-Cap. Vs. Discrete De-Cap.)Measured SSN (No De-Cap. Vs. Discrete De-Cap.)
3.5
SSN
[V]
Vp-p : 370.2 mV
No Decoupling Capacitor
3.1
3.3M
easu
red
S
0 4 8 12 16 20Time [nsec]
M]
3 3
3.5
ed S
SN [V
]
Vp-p : 123.8 mV
16 x 100nF Discrete Capacitors High-frequency harmonic wasamplified with discrete capacitors
3.1
3.3
Mea
sure
0 4 8 12 16 20Time [nsec]
High frequency harmonic was amplified with discrete decoupling capacitors (as expected with impedance curve)
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Measured SSN (Discrete, Low DK “C” , High DK “E”)Measured SSN (Discrete, Low DK “C” , High DK “E”)
3.5
SSN
[V] With Thin Film Embedded Capacitor
(Thickness : 12μm, DK : 4.6) – “C”Low-Frequency Harmonic was appeared
with Low DK Embedded Capacitor
3.1
3.3M
easu
red
S
Vp-p : 49.4 mV
0 4 8 12 16 20Time [nsec]
M]
3 3
3.5
ed S
SN [V
] With Thin Film Embedded Capacitor(Thickness : 10μm, DK : 25) – “E”
3.1
3.3
Mea
sure
Vp-p : 10.6 mV
SSN was almost suppressed with High-DK thin film embedded capacitor
0 4 8 12 16 20Time [nsec]
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PDN Design Methods
- Frequency dependent capacitance and inductance control
- Increase of decoupling Capacitance depending frequency range- Increase of decoupling Capacitance depending frequency range
(on-chip, on-package, on-PCB, lumped, embedded)
- Decrease of Inductance (line, plane, via, wire, bonds, decoupling
capacitors )
- Control resonances (lumped, planar cavity, on-chip, inter-level):
avoid overlap with clock and harmonic frequencies
- Control ESR to reduce peak resonance impedance
- Evaluate dc ESR for dc voltage drop estimation
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Proposed Modeling Method for Chip-Package-PCB Hierarchical PDNProposed Modeling Method for Chip-Package-PCB Hierarchical PDNx
f
y
f
Bond-wire4
1
Chip-level PDN1
8
Chip-level PDN
Package le el PDN2 P k l l
Bond-wire4
1
Fringing Field
9
Fringing Field 8
Package-level PDN
BallInter-level Coupling
75
2 Package-level PDN2
Fringing
9
9
PCB-level PDNVia
3
Vi
6
Inter-level
7
CouplingBall
5
Field
GroundPower
S t tiPCB-level
Via6
Coupling
Considering all parts in hierarchical PDN and merging them into one using
Ground Segmentation Method
PDN3
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segmentation method
Analysis of Impedance of Test Vehicle at Package SideAnalysis of Impedance of Test Vehicle at Package SidePCB Mode (1 0)&(0 1)
PKG Mode (1 0)&(0 1)
PKG Mode (2 1)&(1 2)
100
(1,0)&(0,1)
PCB Mode (2,0)&(0,2)
PCB Mode (2,1)&(1,2)
(1,0)&(0,1)
PKG Mode (1,1)&(1,1)
PKG Mode
(2,1)&(1,2)
Adjacent PKG&Chip Effect
100
hm)
C kCPkg+CInt+CChip
PKG Mode (2,0)&(0,2)
10
edan
ce (o
h
CPkg+CIntCPkg
CPCB+CPkg+CInt+CChipLPkg+Via
1Impe
LChip+BondwireLPkg+Via+LInt//Ball
LPCB+Via+LPkg+Via+LInt//Ball
0.1
LPCB+Via LPkg+Via LInt//Ball
Frequency (GHz)0.1 1 10 20
A quite complicated impedance characteristic composed of chip-package-PCB
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qu te co p cated peda ce c a acte st c co posed o c p pac age Chierarchical PDN is fully analyzed.
Verification of Proposed Modeling Method (Corner on Chip)Verification of Proposed Modeling Method (Corner on Chip)1000
• Switching noise of output waveform with on-chip decoupling capacitor decreases in 13.5dB a frequency of 900MHz compared to the case without on-chip decoupling capacitor .frequency of 900MHz compared to the case without on chip decoupling capacitor .
-> Verified effect of design on-chip decoupling capacitor in RF or LO frequency band.
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Off-chip Decap. Effect : Transfer Impedance (Simulation)Off-chip Decap. Effect : Transfer Impedance (Simulation)
150MHz
Without Off-Chip Decap. VS With Off-Chip Decap.
dB )
20
30
Off-chip Decap.
Off-Chip Capacitor :
L1= 540pH C1=101nF R1 =17mΩpeda
nce
( d10
20 p pEffect
L1= 540pH , C1=101nF , R1 =17mΩ
ansf
er Im
p
-10
0
Capacitance InductanceTra
-30
-20Without Off-chip decap.With Off-chip decap.
10k 100k 1M 10M 100M 1GFrequency ( Hz )
• When additional off-chip decoupling capacitor is designed , transfer impedance decreases more than the case without additional off-chip decoupling capacitor from 2MHz to 200MHz
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- > Transfer impedance decreases when design on-chip decoupling capacitor in 150MHz.
• Switching noise of output waveform with off-chip decoupling capacitor decreases in 12.2dB a frequency of 150MHz compared to the case without off-chip decoupling capacitor .frequency of 150MHz compared to the case without off chip decoupling capacitor .
-> Verified effect of design off-chip decoupling capacitor in IF frequency band.
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Problem by Power and Ground NoiseProblem by Power and Ground Noise
Digital RF & AnalogDAC
PA
LNA
PLL
BPF
LNA LNALNA
ADC
Key circuitKey circuit
Unwanted DC Offset
SystemFailure!!OPamp
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DC Output Offset with Proposed and Conventional AnalysisDC Output Offset with Proposed and Conventional Analysis
PDigital OP amp
P
DC Output Offset with Conventional Analysis
DigitalP
OP ampP
DC Output Offset with Proposed Analysis
100mV 100mV 100mV
60
_+
G GG
BondingWire
_+
G
Package PDN
ChipPDN
50
t (m
V)
Conventional analysisProposed analysis
30
40
utp
ut
Off
se
10
20DC
O
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20
Frequency (GHz)C id bl Di i i b DC O Off
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Considerable Distinction between DC Output Offsetwith and without Consideration of PDN
SSN Sensitive Circuits in IC
- VCO: Voltage Controlled Oscillator
- LNA: Low Noise Amplifier
PLL Ph L k d L- PLL: Phase Locked Loop
- ADC: Analog to Digital Converter
- DAC: Digital to Analog Converter
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SSN Isolation Methods
- DecouplingDecoupling
- Filtering
- Slot
- SplitSplit
- Shielding
- EBG strictures
- Separated power supply/decoupling/return current pathSeparated power supply/decoupling/return current path
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Unique Research FocusUnique Research Focus
High-performance Mixed Mode System
System on Chip(On Chip Level) Signal Integrity(On-Chip Level)
System in Package
Signal Integrity
Low Noise and High-Integration y g
(On-Package Level) Co-Design
ElectromagneticI t fP I t it
High-Integration Design
Module, PCB, Cabling(System Level)
InterferencePower Integrity
Improvement of Reliability Performance Design Cycle Cost
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Improvement of Reliability, Performance, Design Cycle, Cost
ConclusionConclusion
- Significant noise coupling occurs from digital PDN to noise sensitive RF and analog circuits on a same SiP.
- The clock frequencies and harmonic frequencies should beThe clock frequencies and harmonic frequencies should be placed away from the RF carrier frequencies.
- Low PDN impedance should be maintained.- PDN resonance frequencies should be placed away not only from
the clock frequencies, and their harmonic frequencies, but also from RF carrier frequencies.q
- Via and wire are a major noise coupling path from digital PDN to noise sensitive circuits.Noise coupling reduction methods including using PDN design- Noise coupling reduction methods including using PDN design, frequency control, filtering, separation/isolation, decoupling, shielding, and grounding techniques.
- Case studies: LNA, Clock distribution network- Chip-package co-design can provide optimal and cost-effective
solutions
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