IDEC Star-HSPICE â Welcome To Star-HSPICE Trainingeen.iust.ac.ir/profs/Abrishamifar/Analog Integrated Circuit Design... · Improved both speed and accuracy of transient analysis
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Welcome ToStar-HSPICE Training
DAVAN TECH Co.
IDEC Star-HSPICE â�â�yy
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Contents
θ Day 1
� Session 1 : Overview
� Session 2 : Fundamentals
� Session 3 : Analysis Types
θ Day 2
� Session 1 : Controls & Options
� Session 2 : Simulation Controls & Convergence
� Session 3 : Advanced Input File Elements
� Session 4 : Introduction to Statistical Simulation
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Day 1 : Session 1
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SPICE ? ! !
ν Developed By U.C. Berkeley in the Late 1960’s
ν Originally Christened CANCER by Lawrence Nagel (Ph.D. thesis)
Was limited to C, R, L, Bipolar diodes and transistors. 100 node maximum
ν SPICE 1, 1971
Added MOS, JFET’s, Gummel-Poon, subcircuits
ν SPICE 2, 1975
17,000 lines of FORTRAN coded
Added “E” and “G” elements Improved both speed and accuracy of transient analysis
Released as version G.6 in 1983
ν SPICE 3 A superset of 2G.6, re-written in C to include:
Multiple netlists, poly. caps and inductors, inline resistor TC‘s,
Temp sweep analysis, topology checking, more.
SPICE :== Simulation Program with I ntegrated Circuit Emphasis
A Powerful, general-purpose circuit analysis program
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History of Star-HSPICE 1981 Introduced
1984 Capable of 50,000 node analysis
1985 Labs established
1987 Optimization added
1988 Speed increased by 10 -100 X
capacity increased to 100,000 transistors
1989 Inroduced mixed signal analysis
P.C. version marketed
1990 Included lossy transmission line analysis
1992 Major improvements in speed, accuracy and convergence
1993 Several improvements, including auto-memory allocation
1995 Improvements in speed and versatility
1996 FlexLM, CD install, better speed and convergence,
9 Single or multiple tokens locked to a single hostid.
9 One job per token.
9 FLEXlm license file requred, license.dat.
θ Floating
9 Single or multiple tokens “float” to any workstation within the machine class.
9 One job per token.
9 Requires license server (FLEXlm license).
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How to Use : Common Installation Issues
θ Not using the latest hspice script. (which hspice)θ “command not recognized” (improper installation!)θ User .cshrc files not pointing to the latest release.θ Tokens not being granted.
� Examine: .lis file as well as $installdir/FLEX.log
θ Insufficient system resources (examine .lis file):
� Increase /tmp directory
� Increase swap space
9 (swap must be all on ONE single disk partition).
� Increase “limit ” ( limit datasize unlimited)
θ Out of date permit file.θ Trying to run a product on a machine that is not authorized.
� Examine $installdir/license.dat or run install
� Review Manual Vol. 1, Ch 1.
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HSPICE Input/Output Files & Suffixes
θ HSPICE Input Vol. 1, p. 2-11
� input netlist .sp
� design configuration .cfg
� initialization hspice.ini
θ HSPICE Output Vol 1, p. 3-2
� run status .st0
� output listing .lis
� initial condition .ic
� measure output .m*# (e.g. .mt0,mt1,.)
� Analysis data, transient .tr# (e.g. .tr0,tr1,.)
� Analysis data, dc .sw# (e.g. .sw0,sw1,.)
� Analysis data, ac .ac# (e.g. .ac0,ac1,.)
� Plot file .gr# (e.g. .gr0, gr1,..)
θ AvanWaves/HSPLOT Input
� all Analysis data files
Note: # is either a sweep or a hardcopy file number.
Typical Invocations:
hspice design > design.lis
or...
hspice design.ckt > design.out
.lis file contains results of:
.print & . plot
.op (operating point)
.options (results)
Run time status
Depends on .Option Post
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Files & Suffixes The .ST0 file
� **** H S P I C E -- 95x1 (940924) 20:09:20 94/10/17 pc
� Input File: lab1c.sp
� lic: Attempting to get license from local permit file� lic: local license file path: C:\META\H93A\permit.hsp
� lic: Evaluation expires 941231
� lic: License for hspice granted from local permit file C:\META\H93A\permit.hsp� init: begin read circuit files, cpu clock= 1.43E+00
� option list
� option node� option post
� init: end read circuit files, cpu clock= 1.48E+00 memory= 14 kb
� init: begin check errors, cpu clock= 1.48E+00� init: end check errors, cpu clock= 1.54E+00 memory= 13 kb
� init: begin setup matrix, pivot= 10 cpu clock= 1.54E+00
� Circuit Description : node connection of elements
� Passive elements(R,C,L,H,.), active elements(D,Q,M,J,W,X,U,.. )
θ SUCKT Definition
� .SUBCKT, .MACRO with .ENDS
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Netlist Structure: Common Structure
θ .MODEL libraries
� .MODEL
θ +
� In first column is continuation character
θ ALTERing
� .ALTER
� .DEL LIB
θ .END
� Terminates the simulation
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Netlist Structure : Recommended format
This is a better netlist.options post acct opts node.tran .1 5 $ needs 5 seconds to settle.print v(6) i(r16).plot v(4) v(14) v(data)* Voltage sourcesv4 4 0 dc 0 ac 0 0 pulse 0 1 0 .15 .15 .4 2vdata data 0 sin(1.0 1.0 1.0 0.0 1.0)v6 6 0 exp(1 0 .1 .02 .6 .2)* ComponentsL6 6 16 .05c6 16 0 .05r16 16 0 40c4 4 14 .1L5 data 15 1c5 15 0 .2.model ....end
Title
Controls
Sources
Components
Models & Subckts
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Node Naming Conventions
θ Node and Element Identification Vol. 1, p. 2-20
� Either Names or Numbers (e.g. n1, 33, in1, 100)
� Numbers: 1 to 99999999 (99 million)
� Nodes with number followed by letter are all the same (e.g. 1a=1b)
� 0 is ALWAYS ground
� Global vs Local
θ Allowable Characters & Conventions (DON’T USE)
� Begin with letter or “/”
� Max of 1024 characters (after 1024 ignored)
� May contain: + - * / : ; $ # . [ ] ! < > _ %
� May NOT contain: ( ) , = ‘ <space>
� Ground may be either 0, GND, or !GND
θ Every node must have at least 2 connections (not Tline or MOS substrate)
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Node Naming: Globals
θ .GLOBAL Vol. 1, p. 2-17
� Syntax
9 .GLOBAL node1 node1 node3 ...
9 .GLOBAL VBIAS VCC
� Usage
9 When subcircuits are included in the data file.
9 Assigns common node name to subcircuit nodes.
9 Power supply connection of all subcircuits often done this way
à .GLOBAL VCC
à Connects all nodes named VCC, inc. subcircuits with the internal node named VCC.
à When a .GLOBAL is used, the node name is NOT concatenated with the circuit number for output variablereference. Only assigned the global name. (This allows the exclusion of the power node name in thesubcircuit or macro call).
Don’t specify power pins in subcircuit calls.
Use .GLOBAL VCC
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Units & Scale Factors
θ Units
� R - ohm
� C - Farad
� L - Henry
θ Technology Scaling (Scale = 1u, also SCALM)
� ALL lengths and widths are in METERS Vol. 2, p. 15-7
θ Scale Factors Vol. 1, p. 3-36
F = 1e-15
P = 1e-12
N = 1e-9
U = 1e-6
M = 1e-3
K = 1e3
MEG = X = 1e6
G = 1e9
T = 1e12
MIL(S) = 25.4e-6
FT = .305 (METERS)
DB = 20log10
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Components: Passive Devices
θ Components - Passive Devices
� R - Resistors Vol. 2, p 11-4
9 Rxxx n1 n2 Rval <options>
9 R1 1 0 100
9 Element params: Temp, Scaling, etc.
� L - Inductors
9 LSHUNT 23 51 10U Vol. 2, p 11-14
� C - Capacitors
9 C1 1 2 100p Vol. 2, p 11-10
Same format. Just change the first letter.
Can additionally specify a .MODEL forR & C
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Components: Active Devices
� D - Diodes Vol.2, Chp 12
� M - MOS Transistors Vol.2, Chp 15
� Q - BJTs Vol. 2, Chp 13
� �Í active device� model1 1�IU
� Subcircuits & Macros Vol. 3, Chp 21
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Components: Diodes
θ D - Diodes Vol. 2, Chp 12
� Dxxx nplus nminus mname <options>
9 D1 3 0 DMOD IC=0.2v
à Voltage of 0.2v at time 0. Diode model params contained in a model statement, DMOD.
à IC condition-.TRAN UIC option 1 ��Eí1 ª�½¹ î�a �
� .MODEL mname D <LEVEL=val> <keyname=val>...
à 3 types of models: geometric, non-geometric, Fowler-Nordheim
9 .MODEL DMOD D
� Related Controlling .OPTIONS Vol. 2, p 12-2
9 DCAP, DCCAP
9 GMIN, GMINDC
9 SCALE, SCALM
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Components: MOSFETθ MOSFET defined by: Vol. 2, p. 15-1
� MOSFET Element Statement & MOSFET MODEL
� 2 submodels
9 CAPOP specifies the model for the gate capacitances (recommend =4)
9 ACM, Area Calculation Method, selects the type of diode used for the MOSFET bulk diodes.(0=SPICE 2G6, 1=ASPEC, 2=META, 3=ACM2 extension)
� Different models for gate-drain, gate-source, gate-bulk capacitance.
� Substantial effect on Transient Analysis
� CAPOP=4 selects recommended charge-conserving model for the given DC model.
� H96.1 has a new CAPOP=14 model, improved upon CAPOP=13, for correcting charge-conserving behavior near threshold voltage region, and other improvements ...
θ ACM (Area Calculation Method) Vol. 2, p. 15-19
� Modelling of bulk-source, bulk-drain diodes. Recommend ACM=3
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Components: JFET/MESFET Element Syntax
θ Element Syntax Vol. 2, p. 14-4
� Jxxx nd ng ns <nb> mname <W=val> <L=val> <options>
θ Examples
� J1 7 2 3 JM1
� jmes xload gdrive common jmodel
θ SCALING (See Controls & Options Session)
� Units are controlled by .OPTION SCALE and MODEL param SCALM.
� Controlled by element parameters: M and AREA
� Default L and W: METERS!!!
Jxxx DRAIN GATE SOURCE BULK
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Components: JFET MODEL
θ Syntax Vol. 2, p. 14-9
� .MODEL mname NJF (<level=val> <pname1=val1>...)
� .MODEL mname PJF (<level=val> <pname1=val1>...)
θ Example
.MODEL n j_acmo nj f level=3 capop=1 sat=3 acm=0
+ is=1e-14 cgs=1e-15 cgd=.3e-15
+ rs=100 rd=100 rg=5 nd=1
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Components: BJT vol. 2, p. 13-1 to 13-42
θ Requires a BJT element and a .MODEL statement
θ BJT Syntax Vol. 2, p. 13-2
� Qxxx nc nb ne <ns> mname <aval> <OFF> <IC=vbeval,vceval> <M=val>+<DTEMP=val>
� Qxxx nc nb ne mname
� Q23 10 24 13 QMOD IC=0.6,5.0
θ MODEL Syntax Vol. 2, p. 13-10
� .MODEL mname NPN <pname1=val1>...
� .MODEL mname PNP <pname1=val1>...
9 .MODEL QMOD NPN ISS = 0 XTF=1 NS=1.0 CJS=0...
θ Element Controlling Options: Area, Initialization, Temp
θ .OPTION controls (dcap, dccap, gmin, gmindc)
Qxxx Collector Base Emitter <Substrate>
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Sources: Independent
θ Independent Sources, Voltage or Current Vol. 1, pp. 4-1+
à Damped sinusoidal source connected between nodes 3 and 0. 0v offset, Peak of 1v, freq of 100 MHz, timedelay of 1ns. Damping factor of 1e10. Phase delay (defaulted to 0) of 0 degrees.
θ Composite (Mixed)
� Specify source values for more than 1 type of analysis.
à Calls subckt named “nand3”. Assigns params WN=10 and LN=1 (parameters WN and LN within the.SUBCKT)
9 Xnand2 in1_2 out_1 in3_2 out_2 nand3 wn=8 ln=.8
à Calls subckt named “nand3”. Assigns params WN=8 and LN=.8 (parameters WN and LN within the.SUBCKT)
à ALL subcircuit names begin with an “X”
Vol. 3, p. 21-7
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.SUBCKT Components: Example
θ Inverter Example VCC VCC 0 VCC
.PARAM VCC=5V
.GLOBAL VCC
X1 1 2 invsub Mult=3
...
.SUBCKT invsub IN OUT MULT=1
M1 VCC IN OUT 0 P M=mult
M2 OUT IN 0 0 N M=mult
C1 OUT 99 10pf
R1 99 0 10
.ENDS
Global Reference to VCC
Node 0 not mentioned in CALL
Node 99 is LOCALM gets 3 from Call
Output Variables:.PRINT I(X1.M1).PRINT V(X1.99).PRINT P(X1) $ Power dissipation in subcircuit X1 ( 96.1 onward ).PRINT Tran IPIN(X1.1) $ Probing subcircuit pin current of pin X1.1 (96.1 onward).PRINT V(1) $ Since IN and OUT have been REPLACED by Nodes 1 and 2, respectively!!!
.PARAM substitutionNOT positional
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Day 1 : Session 3
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θ Analysis Types
θ Output & Formatting
� output variables
� .print/.plot
Analysis Types
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Analysis Types: Types and Order
θ Types and Order of Execution
� DC Operating(Bias) Point
9 First and most important job is to determine the DC steady state response (called the DC operatingpoint)
� DC Bias Point & DC Sweep Analysis
9 .DC, .OP, .TF, .SENS
� AC Bias Point & AC Frequency Sweep Analysis
9 .AC, .NET, .Noise, .Distortion
� Transient Bias Point & Transient Sweep Analysis
9 .Trans, .Fourier, .OP <time>
� Temperature Analysis
9 .Temp
θ Advanced Modifiers: Monte Carlo, Optimization
DC Operating Point (Bias Point) is firstcalculated for ALL analysis types.
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Analysis Types: Operating Point Calculation
θ DC Operating Point(Æ~ý,quiescent point)i YE� pa í� þ�
θ DC Operating Point a- transient initial]a1 ��E� transientañ½, DCañ½, å�Í 1 � devicei ñI �A small signal model1 ��E�ACañ½ �ÉÉ ÑvÑ.
� Caps OPEN, Inductors SHORT
� Initialized by .IC, .NODESET, and Voltage Sources (time zero values)
θ Disable with .TRAN UIC option (Use Initial Conditions)
Sweep VDS from 0 to 10v by .5 incr at VGS values of 0, 1, 2, 3, 4, & 5v.
� .DC TEMP -55 125 10
Sweep TEMP from -55C to 125C in 10 degree C increments
� .DC xval 1k 10k .5k SWEEP TEMP LIN 5 25 125
DC analysis performed at each temperature value. Linear TEMP sweep from 25 to 125 (5 points)while sweeping a resistor value called ‘xval’ from 1K to 10K in .5K.
� .DC DcSrc START=0 STOP=srcval STEP=‘srcval/100’
H93a.02 onward. Parameterize start/stop/incr values H93a.02 Rel. Note, p. 5
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Analysis Types: DC Analysis: .TF, .SENS
θ .TF Outvar INSRC
� Small-signal DC gain, input resistance, output resistance±�
� Examples
9.DC V(4) V(1)
à DC Gain : V(4) / V(1)
à Input resistance : node 1é node 0�aE íZ
à Ouput resistance : node 4- node 0 �aE íZ
θ .SENS OV1 <OV2 … >
� �Í circuit parameter½ ía ¦� �� �E DC small signal sensitivityi ��
9Linear Sweep 100 points from 1hz to 100Hz, Ñ 1Hz µÑ ACa
9LIN- éù� �ñí n1 9 ��
� .AC DEC 10 1 10K SWEEP cload LIN 20 1pf 10pf
9AC analysis for each value of cload, with a linear sweep of cload between 1pf and 10pf (20 points).Sweeping frequency 10 points per decade from 1Hz to 10KHz. (41point freq.)
NOTE:‘cload’ is a variable, NOT a capacitor
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Analysis Types: AC Analysis: .NOISE
θ Resistor� semiconductor device� éù� rzE noise Ê, ai aU
θ .NOISEa- .ACaé Au¡ ��
θ ACaÉ î éù�½ %I î �yE noisei ±�EÍ ¦� output node½ía î� iE� î �yE noiseE RMSÿ1 VEÙ ±�
9 Add <plo1,phi1> to set lower and upper plot limits.
θ .PROBE syntax (Only works when .OPTIONS PROBE is used)
� .PROBE antype ov1 <ov2...ov32>
θ Using with Subcircuits (Xnnn) Vol. 1, p. 3-37
� Specify nodes ‘local’ to a subcircuit. (Nodes on ‘calling’ line replace local nodes).
� Concatenate circuit pathname with the node name through the ‘.’
9 X1.XBIAS.M5 or...
� Based on unique number automatically assigned to each subcircuit (.OPTION LIST)
9 56:M5 (in this case Hspice assigned 56 to X1.XBIAS)
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Output & Formatting: .GRAPH, AvanWaves
θ .GRAPH
� Non interactive
� Placed in netlist to automatically generate a printout when HSPICE is run
� Not supported on PC
θ AvanWaves
� Interactive
� For display and analyzing Hspice simulation results
� Opening a design file, e.g. .sp file, will automatically open all the output files under thesame design filename
� On-line help
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Output & Formatting: .PRINT
θ .PRINT syntax Vol. 1, p. 3-34
� .PRINT antype ov1 <ov2...ov32>
9 .PRINT tran v(4) i(vin) par(‘v(out)/v(in)’)
à Print results of transient analysis for nodal voltage named 4, current through voltage source named vin, and theratio of the nodal voltage at node ‘out’ and ‘in’.
9 .PRINT AC VM(4,2) VR(7) VP(8,3) Ii(R1)
à Print AC magnitude of the voltage difference between nodes 4 and 2. Real part of the AC voltage betweennodes 7 and ground. VP is phase difference between nodes 8 and 3. Ii is the imaginary part of the currentthrough element R1.
9 .PRINT LX8(m1)
à Print the drain-source conductance of element m1.
9 SWEEPS
à Appear as multiple, concatenated runs.
Vol. 1, p. 3-32
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Output & Formatting: Analysis Data Format
θ Graph nodal voltages, element currents, circuit response, algebraic expressions fromTransient Analysis, DC Sweeps, AC analysis...
θ Specifying Analysis Data Format Vol. 1, p. 2-35
� .OPTION POST (Creates BINARY file; same as POST=1)
� .OPTION POST=2 (Creates ASCII file)
9 Platform independent
θ Limiting the size of the Analysis Data file
� .OPTION PROBE (HSPICE plots ALL nodes by default)
9 Limit data in Analysis Data file to that specified in .PRINT, .PROBE, .GRAPH...
� .OPTION INTERP
9 Limit the number of points stored. Pre-interpolates the output to the interval specified on the.TRAN statement.
θ .PROBE
� Write directly to the Analysis Data File (without writing to .lis file)
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Output & Formatting: Output Variables
θ 5 Groups of Output Variables
� DC and transient analysis Vol. 1, p. 3-4+
9 display individual nodal voltages, branch currents, element power dissipation
� AC analysis
9 display imaginary & real components of nodal voltage, branch current. Also phase, impedanceparameters..
� Element templates
9 display element specific nodal voltages, branch currents, element parameters, and the derivatives ofelement voltage, current, or charge.
� .MEASURE
9 display user-defined variables as specified in the .MEASURE statement.
Miscellaneous.PRINT : table of values.PLOT : line printer plots.OPTIONS : change defaults.TEMP : assign temperature.END : end of circuit definitionTITLE : first line in netlist* : comment line+ : continuation line
Miscellaneous.PRINT : table of values.PLOT : line printer plots.OPTIONS : change defaults.TEMP : assign temperature.END : end of circuit definitionTITLE : first line in netlist* : comment line+ : continuation line
AC analysis control.AC : AC analysis.NOISE : noise analysis.DISTO : distortion analysis
AC analysis control.AC : AC analysis.NOISE : noise analysis.DISTO : distortion analysis
DC analysis control.DC : DC analysis.TF : Transfer function.SENS : sensitivity
DC analysis control.DC : DC analysis.TF : Transfer function.SENS : sensitivity
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LAB 1Aåõ� �åîe �Æy}e íZ)I aÕ¡± yIE Æ~ý1 YE�õq. Create a netlist nemed “lab1a.sp” which describes the circuit shown at figure. Use LIST, POST, NODE as options, and Request an operating point be calculated.
+
-
VV1
10volt0
1
2
Run HSPICE, eg. Hspice lab1a.sp >! Lab1a.lis
Review the output file ( vi lab1a.lis ) and Search for “operating”
R1
1k ohm
R2
1k ohm
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LAB 1Båõ� �åîe �Æy}e íZé Ñ�É�I aÕ¡± yIE Æ~ýé
éù� ¦�1 YE� õq.
Create a netlist nemed “lab1b.sp” which describes the circuit shown at figure. Use LIST
, POST, NODE as options, and request an operating point be calculated.
And request an ac sweep 10 points per decade from 1kHz to 1MHz, and a print the ACvoltage at nodes 1 and 1, and the AC current through r2 and c1.
+
-
V V1
10v DC 1v AC
0
1
2
Run HSPICE, eg. Hspice lab1b.sp >! Lab1b.lis
Review the output file ( vi lab1b.lis ) and search for “ac analysis”.
After then, run awaves and call up lab1b.sp. Display the voltage at node 2.
Change the X axis to log.
R1
1k
R2
1k
C1
0.001uF
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LAB 1C
åõ� �åîe �Æy}e íZé Ñ�É�I aÕ¡± yI½ pulse trainsourcei eíEÙ transienta1 E� õq.Create a netlist nemed “lab1c.sp” which describes the circuit shown at figure. Add a pulse input to the voltage source as follows(starting voltage = 0v, pulse voltage = 5v, delay = 10ns, rise time = fall time = 20ns, pulse width = 500ns, pulse repetition time = 2us)Use LIST , POST, NODE as options, and request an operating point be calculated.And request an transient analysis util 2usec with 10nsec time step.
+
-
VV1pulse
0
1
2
Run HSPICE, eg. Hspice lab1c.sp >! Lab1c.lisReview the output file ( vi lab1c.lis ) and search for “transient analysis”.After then, run awaves and call up lab1c.sp. Display the voltage at node1 and node 2.And display the currents through r2 and c1.
Create a netlist named “lab1d.sp” which describes the circuit shown at figure.PWL voltage source, 0V at time 0sec, 0V at 1us, 1v at 20us, 0v at 20.1nsAC voltage source, magnitude = 1v phase = 0 degreesAC analysis, 20 points per decade from 100 to 100MegaHzTransient analysis, 2us steps for 40us.View the result of wave form of DB/Phase of voltage at node 3 and transient result ofvoltage at node 3.
+
-
VV1PWL/AC
0
1 2 35
L20.38268U
L11.5772U
C11.5307N
C21.0824N
R11
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LAB 1E
åõ� �åîe �Æy}e DiodeE device modelE rs í yIE DC ¦�½åE� î�1 DC analysisi ¢EÙ í�E� õqCreate a netlist nemed “lab1e.sp” which describes the circuit shown at figure.Set V1’s voltage to a variable, dv, and sweep dv from 800mV to 1V in 5mV steps.And use following diode model.( .model df d is = 2.6615e-16 rs = 0.0 )Use LIST , POST, NODE as options, put in a print control for v(1) I(d1)
+
-
VV1
0
1
Run HSPICE, eg. Hspice lab1e.sp >! Lab1e.lisReview the output file ( vi lab1e.lis ) and search for “dc transfer”.After then, run awaves and call up lab1c.sp. Display I(d1) with dv as the x-axis. You cansee the unrealistic current spikes due to 0 ohm rs.Change the rs of the diode to 0.01ohms in the model and do the same as above.
D1
df
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LAB 1F
åõ� �åîe Peak DetectorE ¦�1 í�E� õq.
Create a netlist named “lab1f.sp” which describes the circuit shown at figure.V1 is a SIN wave source, 0volt offset, 1volt peak amplitude, frequency of 1KHzV2 is a 500mV DC source.Use DN4148 model, print out V(2) and V(1) vs, TIMETransient anlysis, 10us steps for 3ms.Diode model ( .MODEL DN4148 D (CJO=5PF VJ=0.6 M=0.45 RS=0.8 IS=7e-9 + N=2 TT=6e-9 BV=100) )
+
-
VV1SIN
0
1 2
D1DN4148
R11
+
-
V V20.5V
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LAB 1G
åõ� MOSFETE IV ¦�1 YE� õq.
Create a netlist named “lab1g.sp” which describes the circuit shown at figure.VDS and VGS are DC sources swept by DC analysis.Sweep VDS from 0V to 10V in 500mV increments while sweeping VGS from 0V to 5Vin 1V increments. Print out I(VDS) and I(VGS) vs. VDSUse the MOSFET MOD1 model(.MODEL MOD1 NMOS level = 13 )
+
-
VVGS
0
7
1
+
-
V VDS
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LAB 1H
åõ� MOSFET InverterE ¦�1 í�E� õq.
Create a netlist named “lab1h.sp” which describes the circuit shown at figure.The length for both MOS device is 1u, and the width is 20u. The pulse is(vlow=0.2, vhigh=4.8, tdly=2n, tf=fr=1n, pw=5n, trep=20n)The tran is 20n in 200p steps, and use the MOSFET model( .MODEL nch NMOS level = 13 .MODEL pch PMOS level = 13)Sweep VIN from 0V to 5V in 500mV increments. Print out V(out) and V(in).