IDE Controller IDE Controller Feasibility Review Feasibility Review Group Members Group Members Brian Kulig Brian Kulig Graig Plumb Graig Plumb James Pierpont James Pierpont Saif Shaikh Saif Shaikh Advisor Advisor Arun Ramanathan Arun Ramanathan
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IDE Controller Feasibility Review Group Members b Brian Kulig b Graig Plumb b James Pierpont b Saif Shaikh Advisor b Arun Ramanathan.
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IDE ControllerIDE ControllerFeasibility ReviewFeasibility Review
Group MembersGroup Members Brian KuligBrian Kulig Graig PlumbGraig Plumb James PierpontJames Pierpont Saif ShaikhSaif Shaikh
AdvisorAdvisor Arun RamanathanArun Ramanathan
Development of an Ultra DMA Development of an Ultra DMA Module for a Hard Disk ControllerModule for a Hard Disk Controller
Specifications – IDE ATA5 StandardsSpecifications – IDE ATA5 Standards
RTL Description of PIO and Ultra DMA (Direct RTL Description of PIO and Ultra DMA (Direct Memory Access) Module in Verilog HDL Memory Access) Module in Verilog HDL (Support for PIO Modes 0 to 4 & UltraDMA (Support for PIO Modes 0 to 4 & UltraDMA Modes 0 to 4)Modes 0 to 4)
Behavioral description of the Hard Disk Behavioral description of the Hard Disk InterfaceInterface
Functional and Timing Simulations using Functional and Timing Simulations using Cadence VerilogXLCadence VerilogXL
5 Modes 0 - 4, used for control signals5 Modes 0 - 4, used for control signals Timer, begins on start pulseTimer, begins on start pulse
• Signals dependent on rw Signals dependent on rw Timer reset at specific timeTimer reset at specific time
• Example mode 0 resets at 67Example mode 0 resets at 67 IORDY can delay system up to 1250 nsIORDY can delay system up to 1250 ns Databus enabled by data writeDatabus enabled by data write
Test BenchTest Bench
It simulates controller for our It simulates controller for our modulemodule
It produces are varying waveforms It produces are varying waveforms for the different modesfor the different modes
Evolve into a hard disk with the Evolve into a hard disk with the implementation of UDMAimplementation of UDMA
Host Termination of Host Termination of Ultra DMA Data-In BurstUltra DMA Data-In Burst
Device Termination of Device Termination of Ultra DMA Data-in BurstUltra DMA Data-in Burst
Description of the HostDescription of the Host
The Host Has:The Host Has:• A Read Buffer and a Write BufferA Read Buffer and a Write Buffer• Ability to cycle through and request Ability to cycle through and request
all modes of data transferall modes of data transfer• Ability to Calculate CRC Values as well Ability to Calculate CRC Values as well
as periodically send an error to the as periodically send an error to the controller controller
Process:Process:• Both Devices are initialized with 4ABABoth Devices are initialized with 4ABA• Value is modified on every STROBE pulseValue is modified on every STROBE pulse