IC Design of Power Management Circuits (II)

IC Design ofPower Management Circuits (II)

Wing-Hung KiIntegrated Power Electronics Laboratory

ECE Dept., HKUSTClear Water Bay, Hong Kong

www.ee.ust.hk/~eeki

International Symposium on Integrated CircuitsSingapore, Dec. 14, 2009

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Part II

Switching Converters:IC Design

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IC Design: Control LoopBiasingRTCT oscillatorComparators, hysteretic comparatorOperational amplifierCurrent sensorsCompensation ramp

IC Design: Power StagePower transistor and gate driveSynchronous rectificationActive diodes

IC Design: Peripheral CircuitsUnder voltage lockout (UVLO)Over current protection (OCP)Soft start circuit

Content

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Analog IC design is ENGINEERING.Analog IC design is ART.

There is no best design but good and reasonable designs.

Design examples shown are suggestions rather than instructions, and unavoidably opinionated.

Suggestions and corrections are most welcome to make a more relevant and accurate presentation.

Foreword

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Guidelines for Analog IC Design

(1) Length of transistors are at least 4λ

to 8λ

for better matching.

(2) Gate overdrive voltage Vov = (Vgs –Vt ) of a transistor should be at least 150mV for better current mirror matching.

(3) Use 1% rule as initial point for matching, delay and losses.

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PWM Voltage Mode Control (1)

A regulated switching converter consists of the power stage and the feedback circuit.

For a buck converter, if an on-chip charge pump is not available, then the NMOS power switch is replaced by a PMOS power switch.

S

RQ

Q

refVA(s)

EACMP

gV

oV

ckramp

L

CLR

1R

2R

obVav

av

PM

NM

avramp

ck

Q

Q

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Current Mode PWM with Compensation Ramp

In practice, the output of EA (Va ) should not be tempered, and a compensation ramp of +mc is added to m1 instead.

S

RQ

Q

refVA(s)

EACMP

ddV

oV

ck

L

CLR

1R

2R

obVav

i

i /N

fNR

PM

NM

V2I

ramp from OSCav

DT

1 c f(m m )R+ 2 c f(m m )R− −

bvbv

compensationramp

ddV

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Synchronous Rectification

To eliminate loss due to forward diode drop, the power diode is replaced by a power NMOS MN , and the scheme is known as synchronous rectification. To eliminate short-circuit loss of MP and MN , a break-before-make (BBM) buffer is used.

Additional logic is needed for DCM operation. Non-overlapping φ1 and φ2

ddV

L

CLR

iPM

NM

S

RQ

QBBM

Buffer

PV NV

PQ,V

NV

Q(ck) φ1

φ =2 NV

φ1

φ2

φ =1

PV

φ2

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Simple Current Source and Current Mirror

ddV

1M

( ) −⎛ ⎞= μ − =⎜ ⎟⎝ ⎠

2 dd 11 n ox 1 tn

1 1

V V1 WI C V V

2 L R1R

1V

2I1I

2M

n ds222 1

1 n ds1

(1 V )(W / L)I I

(W / L) (1 V )+ λ

=+ λ

21 n ds2 ds1

1

(W / L)I (1 (V V ))

(W / L)≈ + λ −

The simple current source is supply dependent. If the power supply would change considerably, for example, from 5V to 12V, then the simple current source should not be used.

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CMOS Widlar Current Source

The self-biased CMOS Widlar current source appears very often in textbooks. The version with a startup circuit is shown below.

1R

1M2M

1I 2I

ddV

1:41V

2V

3V

6M

5M

4M3M

7M

startup

5

wideW

6

longL

( )⎛ ⎞= μ − −⎜ ⎟⎝ ⎠

2

1 n ox gs1 1 1 tn1

1 WI C V I R V

2 L

( )⎛ ⎞= μ −⎜ ⎟⎝ ⎠

2

2 n ox gs2 tn2

1 WI C V V

2 L

1iv 1ov = = ⇒ =−

1m1 m1 1

1 tn 1

2I 2g g R 2V V R

For (W/L)1 = 4(W/L)2 gives

A positive loop exists:− − −

= = =+

1o m1 m2 m4V1

1i m1 1 m3

v g / g g 2Tv 1 g R g 3

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CMOS Peaking Current Source (1)

1R

1M 2M

1I 2I

ddV

bR

1 : 4

1V

2V

( ) −⎛ ⎞= μ − =⎜ ⎟⎝ ⎠

2 dd 11 n ox 1 tn

1 b

V V1 WI C V V2 L R

( )⎛ ⎞= μ − −⎜ ⎟⎝ ⎠

22 n ox 1 1 1 tn

2

1 WI C V I R V

2 L

−= ⇒ = 1 tn2

1 11

V VdI0 I R

dI 2

For I2 = I1 , set (W/L)2 = 4(W/L)1 .

The original peaking current source was designed in bipolar processes. [Gray 01] gives a CMOS sub-threshold version, while we suggest operating all transistors in the active region [Lo 09]. This current source does not need a start-up circuit.

3M3V

2V

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bRm31 / g

m1 1g v

1R

ddv

1v 3v

2v

m2 2g v

−= =

+2 m1 1

dd m1 b

v 1 g R0

v 1 g R

− −= =

+dd 3 m2 m1 1

dd m3 m1 b

v v g 1 g R0

v g 1 g R

The peaking current source has very good power supply rejection.

From previous analysis,

−= = ⇒ =1 tn

1 m1 11 m1

V V 1R g R 1

2I g

Small signal analysis gives

That means the currents generated by current mirroring using V2 and (Vdd –V3 ) has a very low dependence on the supply voltage.

CMOS Peaking Current Source (2)

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Assuming a 0.25µ CMOS process:µn Cox = 50µA/V2 Vtn = 0.8V λn Ln = 0.05µm/Vµp Cox = 25µA/V2 |Vtp | = 0.8V |λp |Lp = 0.05µm/V

Example: Vdd ranges from 4V to 6V, need I2 = 40μA.

Set ∂I2 /∂I1 = 0 at Vdd = 5V with I1 (5V) = 40μA. (W/L)2 = 40 gives Vgs2 -Vtn = 200mV, and 1mV change in Vtn causes 1% change in I2 (1% rule):

Vtn = 0.799V ⇒

I2 = 40.4μAVtn = 0.800V ⇒

I2 = 40.0μAVtn = 0.801V ⇒

I2 = 39.6μA

Vdd I1 I24V 30μA 38.7μA5V 40μA 40.0μA6V 50μA 38.9μA

μ50 A

μ40 A

μ30 A

4V

1I

ddV

1I

2I

5V 6V

CMOS Peaking Current Source (3)

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1R

1M 2M

1I 2I

ddV

1 : 4

1V

1V

b2V

2V

Self-Biased Peaking Current Source

4M3M

b1V

6M

5M7M

startup

5

wideW

6

longL

A current mirror (M3 , M4 ) can be used to replace the large Rb to reduce silicon area. The peaking current source becomes self-biased and needs a startup circuit (may not be favorable).

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RT CT Oscillator (1)

HV

LV

HV

=ch ref TI V /R

TCV

TCTR

refV

LVck

dchI

hystereticcomparator

ddV

QEA

CMP

CMP

The RT CT oscillator generates a ramp that synchronized with the clock, which fits the requirement of a PWM switching converter.

ramp mV

dchM = sT 1 / f

R

S

currentgenerator

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RT CT Oscillator (2)

The charging current Ich is well-controlled by a bandgap derived voltage Vref and an accurate 1% (external) resistor RT (1% rule).

Ich charges an accurate 1% (external) capacitor CT slowly from the lower bound VL to the upper bound VH . The ramp excursion is Vm .

The hysteretic comparator trips when VCT > VH , and ck = 1.

When ck = 1, the NMOS Mdch is turned on, and discharges CT with a large current Idch that is around 10 times of Ich .

When VCT < VL , the comparator trips again, and ck = 0.

Idch is not well-controlled, but the accuracy of the oscillation (switching) frequency fs is well-controlled because it is dominated by the accurate Ich .

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Current Regulator / Voltage Mirror

The error amplifier for generating the charging current can be realized using a differential amplifier stage.

refV

refch

T

VI

R=

TR

ddV

ref

T

VR

bI

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Comparators

V+

bV

−V

ddV

oV −V V+ oV

ddV

bV

Two-stage comparatorOne-stage comparator

Higher gainRise time longer than fall timeA second V- input may be added to both comparators

Low gainEqual rise and fall timesAdd inverters to increase gain

−2V

V+

−1V−2V

oV

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V+

cC zR

oV

2-Stage Simple Operational Amplifier

supplyindependent bias

1M

7M

6M

5M

4M3M

2M

2-stage op amp

LC

−V

bM

bR

ddV

b2R

bI

The op amp of the PWM compensator should be ground-sensing (common mode voltage close to ground).

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Frequency Response of Op Amp

+=

+ +

= ×

=−

=

=

ω =

= ω φ =

dc 1op

1 2

dc m1 ds2 ds4 m6 ds6 ds7

1c z m6

1c m1 ds2 ds4 ds6 ds7

m62

L

m1t

co

2 t m

A (1 s / z )A (s)

(1 s /p )(1 s /p )

where

A g (r || r ) g (r || r )1z

C (R 1 /g )1p

C g (r || r )(r || r )g

pCgC

choose p 3 for 70

dcA 1p

1z2p

tω ω

ω

o90−

o180−

|A|

/A

mφ

The op amp gain is Aop (s) (but the EA (compensator) gain is A(s)):

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Current Mirror Amplifier

V+

bpV

−V

ddV

oV

bR

LC

1M 2M

6M5M 4M3M

The simple 2-stage op-amp can be modified to be a 1-stage current mirror amplifier.

7M 8M=dc m1 ds6 ds8A g (r || r )

=1L ds6 ds8

1pC (r || r )

ω = m1t

L

gC

=+

dcop

1

AA (s)

(1 s / p )

self-biasedWidlar current source

0M

4 :1

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V+

oV

Folded Cascode Op Amp (1)

supplyindependent bias

1M

7M

6M5M

4M3M

2M

folded cascodegain stage

LC

−V

b5MbR

ddV

b2R

bI

To achieve high DC gain, a folded cascode op amp could be used (assume μn =2μp ).

b2V

b1V

b3V

b4V

b1M

b4M

b3M

b2M

0M 10M9M

8M

b0M

b6M

μ10 Aμ10 Aμ20 A

μ20 Aμ20 A1 : 4 : 4 :1

8 : 8: 2

oR

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Folded Cascode Op Amp (2)

The gain function of the folded cascode op amp is:

where

=+

dcop

1

AA (s)

(1 s / p )

=dc m1 oA g R

=1L o

1pC R

=o m6 ds6 ds4 ds2 m8 ds8 ds10R [g r (r || r )]|| [g r r ]

ω = m1t

L

gC

with

and

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cCzRoV

2-Stage Folded Cascode Op Amp (1)

supplyindependent bias

folded cascodegain stage

LC

To achieve high DC gain, a folded cascode op amp followed by an inverting stage could be used (assume μn =2μp ).

12M

11M

invertinggain stage

μ20 A

μ20 A

o1RV+1M

7M

6M5M

4M3M

2M−V

b5MbR

ddV

b2R

bIb2V

b1V

b3V

b4V

b1M

b4M

b3M

b2M

0M10M9M

8M

b0M

b6M

μ10 Aμ10 Aμ20 A

μ20 Aμ20 A1 : 4 : 4 :1

8 : 8: 2

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2-Stage Folded Cascode Op Amp (2)

The gain function of the folded cascode op amp is:

where

+=

+ +dc 1

op1 2

A (1 s / z )A (s)

(1 s /p )(1 s /p )

= ×dc m1 o1 m11 ds11 ds12A g R g (r || r )

=−

=

=

ω =

1c z m11

1c m1 o1 ds11 ds12

m112

L

m1t

c

1zC (R 1 / g )

1pC g R (r || r )g

pCgC

=o1 m6 ds6 ds4 ds2 m8 ds8 ds10R [g r (r || r )]|| [g r r ]

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R

ddV

bI

V-to-I Conversion for Compensation Ramp

To add a compensation ramp to the inductor current, a V-to-I (V2I) converter could be used. Two versions are shown below.

R

inVR

inV

1V

2V

inVR

inVR

inV=gsn

gsp

(if V| V |)

ddV

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Power Transistor Design

Switch voltage of an ideal switch is 0V when conducting⇒

MOS switch should have small Vds when conducting⇒

MOS switch in triode (linear) region when conducting⇒

For an NMOS power switch MN ,

2d n ox dd tn ds ds

N

dsN

d n ox N dd tn

W 1I C (V V )V VL 2

V 1RI C (W /L) (V V )

⎛ ⎞ ⎡ ⎤= μ − −⎜ ⎟ ⎢ ⎥⎝ ⎠ ⎣ ⎦

= =μ −

1% rule: conduction loss of RN is 1% of the load RL

If RL is 10Ω, 1% is 100mΩ. If duty ratio is 0.5, then MN conducts half of the time, and RN can be 200mΩ.

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Buffer Design

To drive a power switch effectively starting from control logic blocks, buffers (digital inverters) have to be used.

Minimum delay gives a ratio of e (=2.718), but too many stages are then needed:- large transistors give large switching loss;- large buffers give large shoot-through (short-circuit) loss;- last stage buffer should have a ratio of 25 to 40.

1 : 4 : 40 : 600 : 30000

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Eliminate Short-Circuit Loss (1)

nV

pV

For a large inverter, insert a starving resistor Rstarve to limit shoot- through (short-circuit) current, but the most important observation is at Vp and Vn . For input changes from ‘0’ to ‘1’, Vn drops immediately, but Vp drops with a delay due to Rstarve .

nV

pV

starveRstarveR

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Eliminate Short-Circuit Loss (2)

Short circuit loss of the last stage (largest) buffer could be eliminated if driven by a buffer with starving resistor.

40 : 600 40 : 600

Starving resistor can be replaced by transistors operating in the linear region. A rule of the thumb design is 1/10 of the inverter transistors.

=n(W /L)

4

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Power PMOS or Power NMOS?

The PMOS switch may be replaced by an NMOS switch driven from an on-chip step-up charge pump [Sze 08].

PSM

Example: Vdd = 1.2V, and needs a 50mΩ

switch (RPS = RNS = 50mΩ)

P-switch: (W/L)PS = 1/(μp Cox ×(Vdd -|Vtp |)×RPS )= 500,000μ/0.25μ

N-switch: (W/L)NS = 1/(μn Cox ×(3.8-Vtn )×RNS )= 33,300μ/0.25μ

Charge pump (1pF caps) + auxiliary circuits is about the size of MNS⇒

P scheme : N scheme = 7.5 : 1

NSM3.8V

5Xchargepump level

shifter

=ddV 1.2V

+−

PSVNSV

refV⇒

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Simple P-Current Sensor

toPWMCMP

s1M s2M

s3M s4MsbM

PGnd

AGnd

iSW1M

1

PM

PsM

20000 /2

20 /2

SW2M

Q

Q

s5M

ddPV

fR

fi RN

1A

1 Aμ

1mA

0.999mA

NM

L

CLR

oV

:1000

On-chip current sensing can be achieved by a small sensing transistor Mps that is forced to have the same Vd , Vg and Vs as the power transistor MP using a matched current source [Ki 98].

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Symmetrical Matching of CMOS Transistors

When a pair of transistors M1 and M2 of the same type are matched, their W/L ratios are the same, i.e., (W/L)1 = (W/L)2 , and in most cases, W1 =W2 and L1 =L2 . However, their drain currents may not be the same due to channel length modulation.

If in addition to having the same W/L ratio, M1 and M2 are forced (by an additional circuit) to have essentially the same drain, gate and source voltages, then they are called symmetrically matched (SM) [Lam 04b, Lam 07].

The simple current sensor uses the 4T cell to force Mps to be symmetrically matched with MP . However, the accuracy is limited by the 4T cell that itself is not symmetrically matched.

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Symmetrically Matched N-Current Sensor

3M 4M

1M 2M

8M

7M5M

9M 6M

2V

1VxV yV

NMNsM

3V4V

ddV

senseI

Q

1000 : 1

i

M : 1 : 1 : M

Replace 4T cell by 8T cell with internal cross-biasing such that paired transistors (M1 , M2 ), (M3 , M4 ), (M5 , M6 ), (M7 , M8 ) are symmetrically matched, forcing Vy =Vx . Start-up circuit is needed [Lam04b, Lam 07].

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Concept of Active Diode

ddV

L

CLR

PM

NM(active diode)

oVxV (A) (K)

A K

A K

The lossy passive diode may be replaced by an active diode, and eliminate the need to control two switches for synchronous rectification:

An active diode is simply a power transistor controlled by a (current) comparator:

CMP

CMP

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Active Diode Implementation (1)

LV (A) HV (K)

HV

One implementation of the active diode is discussed in [Man 06], and is used in a DCM boost converter. The capacitor C is added to improve transient response.

C

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Active Diode Implementation (2)

LV HVHV

HV

LV HV

bV

1V maxV2V

Active diodes can be used as maximum voltage selector for biasing substrates of PMOS power switches in a multiple-output converter.

Another active diode is used in a regulated charge pump [Lam 06].

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Power Management Peripherals

For a low-voltage system, e.g., Vdd =5V, there is usually only one trimmed voltage reference.

For a system with Vdd = 15V, there are usually two voltage references, one trimmed for accuracy, and a second one untrimmed and could work at very low voltage for start-up, UVLO (under voltage lockout) and OVP (over voltage protection).

untrimBGR

trimmedBGR

15V

BG(untrim)V

5V

+_

functionalblocks

REFV

UVLO OVP

linear regulator

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UVLO Comparator

ddV

LV

inVHV

bpV

oLVoHV

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Soft Start Circuit

ddV

SSV

SSC

1R

bnV

2M1M

Consider the buck converter. When Vo =0, EA drives Va to Vdd , and D=1. SW1 is always on, causing large in-rush current. The soft start circuit uses a very tiny current to charge a large CSS , such that VSS rises very slowly, limiting the duty ratio.

ramp

aV

SSVsoftstart

CMP

S Q

Q

ck

R

M2 is in sub-threshold region, sourcing a current in the range of nA.

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I/O Connections

I / O I / O

Schottkydiodes

largediodes

diode- connected transistors

Different types of ESD (electrostatic discharge) diodes.

ddV

GND

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Continual Fraction Expansion

Consider the continual fraction expansion of π:

π

= 3.14159265359

≈ +

≈ ++

≈ ++ +

13

7.062513313

7 (1 /15.99659)13

7 (1 / [15 (1 /1.0034)])

Now,

+

++

++

137

137 (1 /15)

137 (1 /16)

=227

=333106

=355113

= 3.14285714286

= 3.14159292035

= 3.14150943396

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Resistor String using Unit Resistors

In an analog circuit array (compared with a digital gate array), all components are fixed except for the metal layers for interconnection. Resistors are thus formed using unit resistors.

For example, if the unit resistor is 9.5kΩ

and R1 =10.8kΩ

is needed. Use continual fraction expansion:

= =

= +

= ++

= ++ +

1

unit

R 10.81.136842

R 9.51

17.3077

1 17 (1 /3.25)

1 1

7 (1 /[3 (1 / 4)])

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Parallel/Series Connection of Resistors

For Runit = 9.5kΩ[1+(1/7)]×Runit = 1.14286×Runit = 10.86kΩ

8 Runit[1+(1/[7+(1/3)])]×Runit = 1.13636×Runit = 10.8kΩ

11 Runit[1+(1/[7+(1/[3+(1/4)])])]×Runit = 1.13684×Runit = 10.8kΩ

15 Runit

Use 11 Runit (instead of 15 Runit ) is accurate enough and save components. The structure is:

= + ⇒+

1

unit

R 11

1R 73

unitR

1R

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IC References: Books/Theses

Books / Book Chapters / Thesis:[Gilbert 96] B. Gilbert, "Monolithic voltage and current references: Theme and Variations," in

[Huijsing 96], 1996.

[Gray 01] P. Gray, P. Hurst, S. Lewis and R. Meyer, Analysis and Design of Analog Integrated Circuits, 4th Ed., Wiley, 2001.

[Huijsing 96] J. H. Huijsing, R. van de Plassche and W. Sansen, Analog Circuit Design, Kulwer, 1996.

[Johns 97] D. Johns and K. Martin, Analog Integrated Circuit Design, Wiley, 1997.

[Lam 08] Y. H. Lam, Differential Common-Gate Techniques for High Performance Power Management Integrated Circuits, PhD Thesis, HKUST, Jan. 14, 2008.

[Meijer 96] G. Meijer, "Concepts for bandgap references and voltage measurement systems," in [Huijsing 96], 1996.

[Razavi 01] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw Hill, 2001.

[R-Mora 02] G. A. Rincon-Mora, Voltage References, IEEE Press, 2002.

[Sansen 06] W. Sansen, Analog Design Essentials, Springer, 2006.

[Sze 81] S. M. Sze, Physics of Semiconductor Devices, 2nd Ed., Wiley, 1981.

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IC References: Current Sources

Current Sources and Circuits:[Frederiksen 72] T. M. Frederiksen, "Constant current source," US Patent 3,659,121, Apr. 25,

1972.

[Lam 07] Y. H. Lam, W. H. Ki and C. Y. Tsui, "Symmetrically matched voltage mirrors and applications therefor," US Patent 7,215,187, May 8, 2007.

[Lo 09] A. Lo, W. H. Ki and W. H. Mow, “A 20MHz switched-current sample-and-hold circuit for current mode analog iterative decoders,” IEEE Int’l Symp. on IC, pp. 283-286, 2009.

[Kessel 71] T. van Kessel and R. van der Plaasche, "Integrated linear basic circuits," Philips Tech. Rev., pp.1-12, 1971.

[Smith 68] K. C. Smith and A. Sedra, "The current conveyor: a new circuit building block," Proc. of the IEEE., pp.1368-1369, 1968.

[Widlar 65] R. J. Widlar, "Some circuit design techniques for linear integrated circuits," IEEE Trans. Circ. Theory, pp.586-590, 1965.

Ki 47

On-Chip Current Sensors:[Ki 98] W. H. Ki, "Current sensing technique using MOS transistors scaling with matched

bipolar current sources," U.S. Patent 5,757,174, May 26, 1998.

[Lam 04a] H. Lam, W. H. Ki and D. Ma, "Loop gain analysis and development of high-speed high-accuracy current sensors for switching converters," IEEE Int'l. Symp. on Circ. & Sys., pp.V.828–V.831, May 2004.

[Lam 04b] H. Lam, W. H. Ki, C. Y. Tsui and D. Ma, "Integrated 0.9V charge-control switching converter with self-biased current sensor," IEEE Int'l Midwest Symp. on Circ. & Sys., pp.II.305–II.308, July 2004.

[Lam 07] Y. H. Lam, W. H. Ki and C. Y. Tsui, "Symmetrically matched voltage mirrors and applications therefor," US Patent 7,215,187, May 8, 2007.

IC References: Current Sensors and Active Diodes

Active Diodes:[Lam 06] Y. H. Lam, W. H. Ki and C. Y. Tsui, "An integrated 1.8V to 3.3V regulated voltage

doubler using active diodes and dual-loop voltage follower for switch-capacitive load," VLSI Symp. on Tech. & Circ., pp.104-105, June 2006.

[Man 06] T. Y. Man, P. Mok and M. Chan, "A CMOS-control rectifier for discontinuous- conduction mode switching DC-DC converters," IEEE Int'l Solid-State Circ. Conf., pp.358-359, Jan. 2006.

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Blank