Electric-field tuning of the valley splitting in silicon corner
dotsD. J. Ibberson,1, 2 L. Bourdet,3 J. C. Abadillo-Uriel,4 I.
Ahmed,5 S. Barraud,6 M. J. Calderón,4 Y-M. Niquet,3
and M. F. Gonzalez-Zalba2, a)1)Quantum Engineering Technology
Labs, University of Bristol, Tyndall Avenue, Bristol, BS8
1FD,United Kingdom2)Hitachi Cambridge Laboratory, J. J. Thomson
Ave., Cambridge, CB3 0HE,United Kingdom3)University Grenoble Alpes,
CEA, INAC-MEM, 38000 Grenoble, France4)Materials Science Factory,
Instituto de Ciencia de Materiales de Madrid, ICMM-CSIC,
Cantoblanco,E-28049 Madrid, Spain5)Cavendish Laboratory, University
of Cambridge, J. J. Thomson Ave., Cambridge, CB3 0HE,United
Kingdom6)CEA/LETI-MINATEC, CEA-Grenoble, 38000 Grenoble, France
(Dated: 24 July 2018)
We perform an excited state spectroscopy analysis of a silicon
corner dot in a nanowire field-effect transistorto assess the
electric field tunability of the valley splitting. First, we
demonstrate a back-gate-controlledtransition between a single
quantum dot and a double quantum dot in parallel that allows tuning
the devicein to corner dot formation. We find a linear dependence
of the valley splitting on back-gate voltage, from880 µeV to 610
µeV with a slope of −45 ± 3 µeV/V (or equivalently a slope of −48 ±
3 µeV/(MV/m) withrespect to the effective field). The experimental
results are backed up by tight-binding simulations thatinclude the
effect of surface roughness, remote charges in the gate stack and
discrete dopants in the channel.Our results demonstrate a way to
electrically tune the valley splitting in
silicon-on-insulator-based quantumdots, a requirement to achieve
all-electrical manipulation of silicon spin qubits.
A quantum bit implemented on the spin degree of free-dom of a
single electron in silicon is one of the mostpromising candidates
for large-scale quantum computa-tion due to its long coherence
time1. Nowadays, singleelectrons spins can be confined in quantum
dots (QDs)2
and single and two qubits operation can be performedwith great
accuracy3,4. However, scaling to a large num-ber of qubits remains
a major challenge. Strategies atthe architecture level propose
large-scale quantum cir-cuits5,6, using in particular CMOS
technology for theimplementation of error-correction protocols and
the in-tegration with classical electronics7,8. At the qubit
level,all-electrical control of spins is desired because
manip-ulation can be performed using local oscillating
electricfields on gates that already define the QD. This is as
op-posed to magnetic-field-based qubit control that
requiremicrowave antennas or cavities that deliver less
localizedfields9. All-electrical control of electron spins in
siliconhas been achieved using the extrinsic spin-orbit
inter-action (SOI) induced by magnetic field gradients
frommicromagnets10,11 and recently a much more compactversion has
been demonstrated using the enhanced in-trinsic SOI in silicon QDs
with low-symmetry, such asCMOS corner dots12. Silicon corner dots
are distributedover two Si/SiO2 interfaces and have a single
symmetryplane13,14, as opposed to the more common planar
siliconQDs15 that usually have two symmetry planes. The un-derlying
control mechanism in the aforementioned studyis based on the mixing
of spin and valley degrees of free-dom that allows driving
electrically inter-valley spin ro-
a)[email protected]
tations. A recent proposal suggests that the efficiencyof this
mechanism can be improved by tuning the valleysplitting
electrically to bring the qubit near the valley-mixing point for
manipulation and away to mitigate de-coherence. This opens an
opportunity for compact elec-trical manipulation of spin qubits
while retaining longcoherence times16.
In this Letter, we demonstrate experimental controlof the valley
splitting in a silicon corner dot by meansof static electric
fields. We use a silicon-on-insulatornanowire field-effect
transistor (NWFET) tuned to thecorner dot regime and perform energy
spectroscopy toquantify the valley splitting. We measure an
electric fieldtunability of −48± 3 µeV/(MV/m) compatible with
re-ports on planar silicon QDs9,17,18. The data are in agree-ment
with tight-binding calculations that include the ef-fect of surface
roughness and remote Coulomb scattering.Our results are a basic
ingredient for all-electrical spinqubit manipulation with tunable
spin-valley mixing.
We perform the experiments on a NWFET similar tothe one pictured
in Fig. 1(a) at a refrigerator tempera-ture of 40 mK. The device
channel, oriented in the [110]direction, has a width of 42 nm, a
height of 8 nm, and agate length of 44 nm, and is doped with
phosphorous at aconcentration of 5×1017 cm−3. The gate oxide is
formedof a SiO2(0.8 nm)/HfSiON(1.9 nm) stack followed by aTiN(5
nm)/poly-Si(50 nm) metal gate. The undoped sil-icon substrate is
activated by flashing a surface-mountedblue LED to generate free
carriers, and it can then beused as a back gate. Voltages can be
applied to thetop-gate (VTG) and back-gate (VBG) modifying the
elec-trostatic potential in the channel, confining electrons
inelectrostatically-defined QDs.
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FIG. 3. Simulations of the valley splitting as a function ofVBG.
The red line gives the trend for a perfect device withno defects or
roughness. The blue line and error bars are theaverage and standard
deviation for different SR profiles withrms 0.35 nm (each plotted
as a dashed gray line). Finally,the orange dashed lines are a few
representative simulationswith SR and RCS included (the best match
with the experi-ment being highlighted by the solid orange line
with diamondsymbols). The top axis indicates the effective electric
fieldperpendicular to the substrate (calculated in the
reference,perfect device). The smaller in-plane effective field has
littleeffect the valley splitting.
(RCS33) by charges at the SiO2/HfSiON interface34,35
with apparent densities as large as a few 1013 cm−2. Infact, the
Coulomb disorder in the gate stack likely resultsfrom a combination
of charge traps at this interface, lo-cal band offset fluctuations
(interface dipoles), and pos-sibly from work function fluctuations
in granular metalgates36. The existence of significant disorder is
consis-tent with the fact that the two corner dots are not
fullysymmetric, as revealed by the stability map in Fig. 1(b)and
the Coulomb diamonds in Fig. 1(d).
We have introduced roughness in the TB calcula-tions using a
Gaussian auto-correlation function37 for theSi/SiO2 interface
profile with correlation length Lc =1.5 nm and rms ∆SR = 0.35 nm
adjusted
35 on room-temperature mobility measurements in similar
devices.∆SR lies in the upper range of the values usually re-ported
for Si/SiO2 interfaces, which is not unexpectedfor an etched
device. As discussed above, the SR con-sideraly decreases the
valley splitting (see Fig. 3) andis responsible for a significant
device-to-device variabil-ity – however the present experimental
data are morethan five standard deviations away from the
calculations.The introduction of Coulomb disorder in the gate
stackcan raise the valley splitting back into the
experimentalrange. Here we have modeled this disorder as a
distribu-tion of positive and negative charges at the
SiO2/HfSiON
with total density σ = 1013 cm−2. This large value is,again,
consistent with the mobilities measured in planaras well as
nanowire devices, and with their dependenceon the thickness of the
SiO2 layer
35,36. It must be seen asan effective density of charges
mimicking all high-κ/metalgate-related disorders described above,
which have simi-lar fingerprints on the potential in silicon.
We point out, though, that the magnitude of the val-ley
splitting depends strongly on the position of thesecharges. The
localization is, indeed, much more efficientin a Coulomb than in a
short-range SR potential, but alsomuch more variable. For a given
density of RCS charges,the valley splitting spans about one order
of magnitudedepending on their distribution. A statistical
analysisof both mechanisms shows that 20 out of 20 simulatedrough
devices show well defined corner states at negativeVBG, while only
14 out of 20 simulated devices with RCSincluded still do so.
Coulomb disorder must, therefore,primarily be reduced in order to
mitigate device variabil-ity. As a matter of fact, the valley
splitting has beenmeasured in a similar device with two corner dots
in par-allel but with only SiO2 as the gate dielectrics
38. Thevalley splitting at VBG = −1 V was found to be 145 µeVin
one dot, which is more compatible with the TB valleysplitting
calculated with SR and no RCS. This calls for acareful assessment
of the sources of disorder in silicon de-vices. Removing high-κ
oxides from the gate stack mighthelp to reduce Coulomb disorder and
variability, at theprice of a lower gate coupling.
In conclusion, we have highlighted a transition fromsingle to
double quantum dot (corner dots) in a sili-con NWFET. We have also
demonstrated that the valleysplitting in one of the corner dots
could be tuned from880 µeV to 610 µeV by varying the static gate
voltages(with a gradient of −48 ± 3 µeV/(MV/m) with respectto the
effective field). The magnitude of the valley split-ting and its
dependence on the electric field can be re-produced by a
tight-binding model when accounting forsurface roughness and
charges trapped in the gate oxides.Our results fulfill a milestone
towards all-electrical spinmanipulation using tunable valley-spin
mixing.
This research has received funding from the Euro-pean Union’s
Horizon 2020 Research and Innovation Pro-gramme under grant
agreement No 688539 (http://mos-quito.eu) and the Winton Programme
of the Physics ofSustainability. DJI is supported by the Bristol
QuantumEngineering Centre for Doctoral Training, EPSRC
grantEP/L015730/1. JCAU and MJC acknowledge fundingfrom MINEICO
(Spain) and FEDER via Grant FIS2015-64654-P. JCAU thanks the
support from grant BES-2013-065888. IA is supported by the
Cambridge Trustand the Islamic Development Bank.
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Electric-field tuning of the valley splitting in silicon corner
dotsAbstract