IAY 0600 Digital Systems Design Digitaalsüsteemide disain Course Overview Alexander Sudnitson Tallinn University of Technology
Dec 28, 2015
IAY 0600
Digital Systems Design
Digitaalsüsteemide disain
Course Overview
Alexander Sudnitson
Tallinn University of Technology
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Administrative
Aleksander Sudnitsõn (Alexander Sudnitson)
Department of Computer Engineering (Arvutitehnika instituut)
Associate Professor (dotsent)
ICT-503
Tel. +372 5092356
www.pld.ttu.ee/~alsu
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Course resources
www.pld.ttu.ee/~alsu
IAY0600 Digital Systems Design (LECTURES) Digitaalsüsteemide disain
IAY0600l Digital Systems Design (WORKSHOPS) Digitaalsüsteemide disain (LABS)
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Lectures
Lecture:
Wednesday 14.00 - 15.30
http://ati.ttu.ee/~alsu/IAY0600.html
The first regular Lab time: 16.09.2015, 16.009.09.2015 are lectures only 14.00 – 17.30
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Labs
A. Wednesday 16.00 - 17.30 (19.15)
B. Thursday 17.45 – 19.15 (21.00)
Assistant:
research scientist, Dimitri Mihhajlov, PhD
Technical Assistant:
early stage researcher Artjem Rjabov
The first regular Lab time: 16.09.2015, 16.00
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Grading
To stimulate the student’s activity a project-based evaluation approach is adopted. Grading consists of control of knowledge in examinations (20 points in final grade) and of the demonstration of the projects and the quality of a written reports (40 points in final grade for doing compulsary labs, up to additional 40 points in final grade for doing optional labs).
“LEARN BY DOING”Learning By Example Using VHDL (with FPGA Evaluation Boards)
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Passing a Lab
Every completed experiment (project) must be presented to Assistant (D. Mihhailov), who will evaluate student’s results and effort
Each lab is passed in three steps:Step 1: Visual demonstrationStep 2: Submission of the reportStep 3: Defence/discussion of the report
Labs can be done either individually, or in teams of two.Note, that in case of teamwork Step 2 and Step 3 MUST be done by each team member separately.
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Compulsory Labs
Labs labelled “compulsory” form the basic core of the course. In order to pass the course theselabs MUST be completed within the deadline. Passing all compulsory labs yields the minimumpositive final grade and allows possibility to attend the exam.
• Comparator• Adder• Parameterizable Adder• LFSR• Finite-State Machine
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Optional Labs
Labs labelled “optional” are more advanced labs that are not required to be completed in order to pass the course. However, each successfully passed optional lab increases the final grade (up to the maximum for doing all optional labs).
• Greatest Common Divisor • Creeping Line • RISC Processor
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Labs
Xilinx FPGA ToolsThe laboratory assignments are done using the Xilinx ISE Software.
simulationsynthesisimplementation
Digilent Nexys3 FPGA Board
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Course goals
to elaborate knowledge of the design process from design description in VHDL through functional simulation, synthesis, timing simulation, and PLD (FPGA) programming;
to gain experience in designing and verifying digital systems using synthesis and simulation tools;
to provide students the theory and practice of rapid prototyping of digital systems in a laboratory environment;
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Outcomes
to proceed from a digital system description in VHDL to its implementation in a PLD (FPGA) using of a number of computer-aided design software tools;to understand how to interpret design tool outputs in evaluating alternative system designs for a specific set of requirements, and how to use the knowledge gained to improve the design;to understand and comprehend asynchronous design methods, computational models, design terminology.
Why is this course worth taking?
• VHDL for synthesis: one of the most sought-after skills
• knowledge of state-of-the-art tools used in the industry
• knowledge of the modern FPGA & ASIC technologies
• unique knowledge and practical skills that make you competitive on the job market
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Main topics
The course is based on the development of a real-world projects and case studies
Synthesizable VHDL Digital systems design methodology using
VHDL and PLD (FPGA) FPGAs as means for building reconfigurable
systems Rapid prototyping of digital systems.
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Slides
http://ati.ttu.ee/~alsu/IAY0600.html
Lecture slides (to be published before each lecture).
Auxiliary material:
Digital Systems Modeling and Synthesishttp://www.ati.ttu.ee/IAY0340/
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Textbooks
Short K. L. VHDL for Engineers, Pearson Education, Inc., 2009, 2013.
Chu P.P. FPGA Prototyping Using VHDL Examples: Xilinx Spartan-3 Version, Jonh, Willey & Sons, 2008.
Pedroni V. A. Circuit Design and Simulation with VHDL, Massachusetts Institute of Technology, 2010.
Skljarov V., Skliarova I., Sudnitson A. Design of FPGA-based Circuits using Hierarchical Finite State Machines. TUT Press, Tallinn, 2012, 240 p.
Richard E. Haskell & Darrin M. Hanna, "Digital Design“, 2nd Edition, 2012