I. Structure of AC Plasma Display Panel Schematic of PDP Drive System

I. Structure of AC Plasma Display Panel Schematic of PDP Drive System

II. Driving Method 1. PDP Drive System in brief 2. Principal of Matrix Driver System 3. ADS Drive

III. Driver Board 1. Functions 2. Output of Driver Board (42” single) 3. Power Loss of Sustain Circuit 4. Sustain Circuit : Webber type 5. Sustain Circuit : Sakai type 6. Sustain Circuit : TERES type 7. Example of Driver Board (42” single) 8. Development Trend of Driver board 9. Development Trend of Scan IC 10. Interface (for reference)

Contents

I. Structure of AC Plasma Display Panel

X, Y Electrode

DielectricLayer

MgO Layer

Front Glass

BarrierRib

Phosphor Address Electrode

Rear Glass

PDP TV

Discharge in the PDP cell

ElectronsIONs

+ + + + - - - -

Discharge Structure of PDP

Schematic of PDP Drive System

○ Each cells are selected by switch

“On” of Address Electrodes.

○ Discharge for display is operated

by switch “On” of Y-port(Scan)

and X-port(Sustain) by turns.

D1

D2

D3

D4

D5Y

1Y2Y3Y4Y5

Scan PowerSource

Address PowerSource

Address System

SustainPowerSource

X

I. Structure of AC Plasma Display Panel

X1

X2

X3

Y1Y2

Y3 ON

OFF

1. Principal of Matrix Driver System

II. Driving Method

X1

X2

X3

Y1Y2

Y3 ON

OFF

Principal of Matrix Driver System

2. Driving Method

SF1 SF2 SF3 SF4 SF5 SF6 SF7 SF8

1

.....

2

480

128T64T32T16T8T4T2T1T

1TV field (time)scan

line

address

sustain

sub-field

ResetPeriod

AddressPeriod

SustainPeriod

X

Y1

Y2

Yn

D

2. Structure of ADS Drive Method

Gray scale is displayed by s/w‘On’ of specific SF(sub field)in 1TV frame(field time).

II. Driving Method

3. Feature of ADS Drive Pulse

II. Driving Method

(Terminology)

Reset : Elimination of Sustain discharge /

Formation of Address discharge’s condition

Address : Selection of ON/OFF Cell

• Sustain : Display real picture through Sustain discharge

• Time : In case of Dual Scan (480 scan line), 1 Frame (16.67msec) are

organized

• Reset 15 ~ 20%, Address 40 ~ 50% and Sustain 35 ~ 40%.

Address Operation

In order to display picture,

select the cells.

In order to display picture,

select the cells.

Sustain operation

Display cells through strong

Sustain discharge.

Display cells through strong

Sustain discharge.

Erase / Reset

Elimination for next image

(generate Display discharge)

Elimination for next image

(generate Display discharge)

Address Buffer Board (upper)Address Buffer Board (upper)

Address Buffer Board (Lower)Address Buffer Board (Lower)

PowerPowerSupplySupplyBoardBoard

LogicLogicBoard Board

ImageImageProcessingProcessing

BoardBoard

Y

Y

Electrod

eE

lectrode

X

X

Electrod

eE

lectrode

III. Driver Board

Sustain pulse generation

Reset pulse generationScanning operation

Basic signal protectionShort circuit protectionMain functions = +

Y-B’d X-B’d

Scan-B’d

1. Functions Disposition of Boards

AC Power

Filter

Capacitor

Sustain Volts

Logic Volts

FET Drive Volts

Reset / Scan Volts

SwitchOn / Off

SwitchOn / Off Reset / Scan Wave

Sustain Wave

Logic Signal

Scan Buffer

Logic Board Y - Electrode

Y- Board Power & Signal Flow

III. Driver Board

AC Power

Filter

Capacitor

Sustain Volts

Logic Volts

FET Drive Volts

X-bias Volts

SwitchON/OFF

SwitchON/OFF X-bias

Sustain Wave

Logic SignalLogic Board Y - Electrode

X- Board Power & Signal Flow

III. Driver Board

- 1 -

Y

X

Address

Va : 75V

184V Vs : 150V Ve : 184V 150V

RESET 구간 SCAN 구간 SUSTAIN 구간

150V

Vset : 360V

150V

Vscan : 65V 65V

Vs : 150V

Y rise

Y fall

X rise

Sustain DischargeLuminescence part

Reset Ramp Reset(weak discharge reset) Contrast, operation margin, expanded production rate

Addressing=> Address period is long

2. Output of Driver Board (42” Single)

Current of Discharge

Ipk : 120A-150A

Current of

Resonance

Ipk : 60-70A

Vth

III. Driver Board

Ai

X

Yj

~~ ~~

~~

~~

~~ ~~reset period address period sustain period

time

self-erase pluse

erase pluse

address pulse

scan pulse

sustain pulse

2. Output of Driver Board(42” Dual Scan) : Reference

Dual Scan (Address period is short)LOG Reset Wave in use

• The point of view on Driver board, Dual Scan is same structure with Single Scan except the circuit of Reset Wave output.

III. Driver Board

Vs

00

Xs

XgYg

Ys

Basic sustain circuit

X, Y Electrode

DielectricLayer

MgO Layer

Front Glass

BarrierRib

Phosphor Address Electrode

Rear Glass

PDP Structure

Electrical model = Capacitor

3. Power Loss of Sustain circuit

PDP panel

III. Driver Board

Discharge of Capacity load

PDP

Heat loss

CV f2

Power loss=

C : panel capacitanceV: sustain voltagef: average frequency

About 120 Watts in case of 42inch panel

III. Driver Board

Heat loss

Vs

00 0 0

L1

Xg

XrYs

L2

YfYg

XsYr

Cy

Xf

Cx

Operation performance of this circuit is good. (compatible with most Waves)

Overall efficiency is high.

(On the usage of LC Resonance circuit, switching loss should be small.)

Simple operation and organization. Operation is stable. Production enterprise with Webber type : Matsushita, Fujits, Pioneer, LG, Samsung

Energy’s Recovery circuit Energy’s Recovery circuitSustain circuit

Y-Board X-Board

4. Sustain Circuit : Webber type

III. Driver Board

Panel

Characteristics

Vs

00 0 0

L1

Xg

XrYs

L2

YfYg

XsYr

Cy

Xf

Cx

Vs

00 0 0

L1

Xg

XrYs

L2

YfYg

XsYr

Cy

Xf

Cx

1. Rising period

2. Vs - Sustain period

Yr,Xg Ys,Xg Yf,Xg Yg,Xg

Hard switching generation

Light Wave

Sustain Wave

Y X

Observation Wave

III. Driver Board

Vs

00 0 0

L1

Xg

XrYs

L2

YfYg

XsYr

Cy

Xf

Cx

Vs

00 0 0

L1

Xg

XrYs

L2

YfYg

XsYr

Cy

Xf

Cx

3. Falling period

4. GND period

Yr,Xg Ys,Xg Yf,Xg Yg,Xg

Hard switching generation

Light Wave

Sustain Wave

Y X

Observation Wave

III. Driver Board

Operation performance of this circuit is low.

(It is not proper to recover the energy except Sustain part.)

Overall efficiency is high.

(On the usage of LC Resonance circuit, switching loss should be small.)

Simple operation and organization. Operation is stable.

Production enterprise with Sakai type : NEC

Y-Board

0 0

Vs

Xg

Xs

Yg

L

Ys

Sb

Sa

Energy Recovery circuit

X-Board

5. Sustain Circuit : Sakai type

III. Driver Board

Panel

Characteristics

0 0

Vs

Xg

Xs

Yg

L

Ys

Sb

Sa

0 0

Vs

Xg

Xs

Yg

L

Ys

Sb

Sa

Yr,Xg Ys,Xg Yf,Xg Yg,Xg650us 650us

1.00us~1.70us

2.30us~3.00us

Sa Ys,Xg Sb Xs,Yg

1. Y rising & X falling period

2. Sustain period

Hard switching generation

Sustain Wave

Y

X

Observation Wave

III. Driver Board

0 0

Vs

Xg

Xs

Yg

L

Ys

Sb

Sa

0 0

Vs

Xg

Xs

Yg

L

Ys

Sb

Sa

Ys,Xg650us 650us

1.00us~1.70us

2.30us~3.00us

Sa Ys,Xg Sb Xs,Yg

3. X rising & Y falling period

4. Sustain period

Hard switching generation

Sustain Wave

Y

X

Observation Wave

III. Driver Board

TERES type hold a patent right for the structure of Sustain circuit.

It is advantage of low price. (low voltage part in use)

Complicated operation and organization.

It should be added ERC circuit like Sakai type or Webber type. Production enterprise with TERES type : FHP

0 0

VsVs

Yh

C1

Xh

Yg YL

Xs

C1

Xg

Ys

XL

C2

Charge pump방식

6. Sustain Circuit : TERES type

III. Driver Board

Panel

Characteristics

0 0

VsVs

Yh

C1

Xh

Yg YL

Xs

C1

Xg

Ys

XL

C2

0 0

VsVs

Yh

C1

Xh

Yg YL

Xs

C1

Xg

Ys

XL

C2

Vy

Vx

Ys,Yh, Xg,XL

Xs,Xh, Yg,YL

Vs

- Vs

Vy

Vy

Vx

Vx

Charge pump path

Charge pump path

Sustain path

Sustain path

Internal voltages of Device : ½ comparing with the other typePerformance : same as the other typeCost : profitable comparing with the other typeApplication : It is not compatible with every Waves ( swing +,- by turns)

III. Driver Board

Yr

Yf

Ys

Yg

Yrr

Yfr

Yp

YpYsp

Ysc

Dyr

Dyvs

Dyf

Dyg

ERC circuit (Yr,Yf,Dyys,Dyr,Dyf,Dyg) => Energy recovery

Sustain circuit (Ys, Yg) => Sustain Discharge

Reset circuit (Yrr, Yfr) => Elimination of Panel

Path circuit (Yp, Ysp) => Formation of Main Path

Scan circui t(Ysc) => Scan Bias

7. Example of Driver Board ( 42” single )

Y-Board

III. Driver Board

Xr

Xf

Xs

Xg

Xrr

Dxr

Dxvs

Dyf

Dxg

ERC circuit (Xr, Xf, Dxvs, Dxr, Dxf, Dxg) => Energy recovery

Sustain circuit (Xs, Xg) => Sustain Discharge

Reset circuit (Xrr) => Elimination of Panel

Dxf

X-Board

III. Driver Board

Y-BRD X-BRDScan Buffer

SMPSLogic

Address Buffer

42” single

III. Driver Board

50” Dual

III. Driver Board

Y-BRD X-BRD

Scan Buffer

Logic SMPS

Address Buffer

Address Buffer

* The Load of Driver Board(50”) is about 1.5 times bigger than 42”’s.

50” DualIII. Driver Board

YpYs

Yg

Yr

Yf

Ysp

Yrr Yfr

Blocking Diode

Clamping Diode

Ysc

Xf

Xr

Xs

Xg

Xrr

Clamping Diode

ERC circuit(Yr, Yf, Dyvs, Dyr, Dyf, Dyg)

ERC circuit(Xr, Xf, Dxvs, Dxr, Dxf, Dxg)

Sustain circuit(Xs, Xg) Sustain circuit

(Ys, Yg) Reset circuit(Yrr, Yfr, Xrr)

Path circuit(Yp, Ysp)Scan circuit(Ysc)

0

00

0

0

0

0

0

VsVs

Vset VscanVe

Xrr

Xg

Cvscan

Yr

Xf

Ysc

C1

YgYf

Yrr

Yfr

L2

Ys

L1

Xr

Yp

Cvset

Xs

Ysp

RAMP

RAMP

RAMP

Circuit BlockDiagram

III. Driver Board

0

00

0

0

0

0

0

VsVs

Vset VscanVe

Xrr

Xg

Cvscan

Yr

Xf

Ysc

C1

YgYf

Yrr

Yfr

L2

Ys

L1

Xr

Yp

Cvset

Xs

Ysp

RAMP

RAMP

RAMP

- 1 -

Y

X

Address

Va : 75V

184V Vs : 150V Ve : 184V 150V

RESET 구간 SCAN 구간 SUSTAIN 구간

150V

Vset : 360V

150V

Vscan : 65V 65V

Vs : 150V

Y rise

Y fall

X rise

(1)

(2)

(3)

(4)

Yp, Ysp : ON

Operations(Sustain part) III. Driver Board

0

00

0

0

0

0

0

VsVs

Vset VscanVe

Xrr

Xg

Cvscan

Yr

Xf

Ysc

C1

YgYf

Yrr

Yfr

L2

Ys

L1

Xr

Yp

Cvset

Xs

Ysp

RAMP

RAMP

RAMP

Y

X

Address

Va : 75V

184V Vs : 150V Ve : 184V 150V

RESET 구간 SCAN 구간 SUSTAIN 구간

150V

Vset : 360V

150V

Vscan : 65V 65V

Vs : 150V

Y rise

Y fall

X rise

Regarding rising points and falling points of Ramp Wave, use Sustain operations.

Operations (Reset part)

(1),(4)

(2)

(2)

III. Driver Board

0

00

0

0

0

0

0

VsVs

Vset VscanVe

Xrr

Xg

Cvscan

Yr

Xf

Ysc

C1

YgYf

Yrr

Yfr

L2

Ys

L1

Xr

Yp

Cvset

Xs

Ysp

RAMP

RAMP

RAMP

Y

X

Address

Va : 75V

184V Vs : 150V Ve : 184V 150V

RESET 구간 SCAN 구간 SUSTAIN 구간

150V

Vset : 360V

150V

Vscan : 65V 65V

Vs : 150V

Y rise

Y fall

X rise

Operations (Scan part)III. Driver Board

scan

Address

GND

Operations (Scan part)768 line

480 line

t=t0

t=t1

t=t2

t=t3

t=t0

t=t1

t=t2

t=t3

III. Driver Board

III. Driver Board

Y-BRD

Discharge Current

Ipk : 120A-150A

pulse width : 1us 미만

Resonance Current

Ipk : 60-70A

pulse width : 300-400 ns

Vth

Parallel position of Switch and Diode X-BRD

Sustain & Path S/W

Path Diode

ERC S/W

Path Diode

ERC S/W Sustain S/W

Address기간(가변)

Reset방전 Sustain방전

1Sub- field

Samsung

NEC

Matsushita

Examples ofOperation Wave

Matsushita

III. Driver Board

• Improvement of Board efficiency and Design for radiation of heat

: Decline of Board’s electric power consumption and Operations

of Fanless motor for the radiation.

• Thickness Low depth

: Dignity elivation of the set

• Design for Low Cost

a. Development of new part

b. Change of Circuit Topology

c. Design change in accordance with Operation Wave change

• Application of HIC (Hybrid Intergrated Circuit)

: PCB Size decline, Improvement of Production process ,

Development and Application trend in each PDP’s vendor

• Development for self Operation type except a patent right for Webber

8. Development Trend of Driver board

III. Driver Board

• Scan IC / Address IC a. Low Coat

Development of Low Voltage Address Operation type

through change of Operation Wave

⇒ Application of Low Voltage Driver

b. High Speed

Needs the Data processing quickly for the

reduction of Address Cycle

⇒ Speedy Data Shift Clock

9. Development Trend of Scan IC

III. Driver Board

• Connection of the circuit output and Panel

: usage the FPC (Flexible Printed Circuit)

• Connection of Scan/Address Driver and Panel

: On the usage of FPC, Boards are connected with

Panel electrode.

a. Board + Connector + FPC + Panel

b. COB(FPC) + Panel

c. COF(FPC) + Panel

Trend changes to COB / COF type on overall

PDP manufacturing vendors.

Example :FPC(Flexible Printed Circuit)

III. Driver Board

10. Interface (for reference)