I L D B I m a f o R i a c d p l a e c v a i i t l t n s f H i c a p s i d p N s ISSN 13 Impleme L. F. Rah Department of Bangi, 43600 http:/ Introduction In RFI memories (NV and writing op factors in low- of the EEPRO RFID reading s a key factor affected by th challenges for develop a rob power supply ower, the d amplifier beco At prese extensively im current-compa voltage-type s and steadfastn ncreasing sen ncorrect read this convent imitations ar transponders. necessitate lo sense amplifie A numbe far to accom However, rese ssues at lowe current [6]. Li and highly re process [7]. T supply 3.3V, t s 35ns and during the se power supply Nevertheless, satisfactory low 392 – 1215 entation man, M. f Electrical, E UKM, Selang //dx.doi.org/10. ID transpond VM) like EE perations of E -power RFID OM sense amp space [3]. In r to determine he Sense Am r new generat bust and high y voltage. A design of a omes very crit ent, current-ty mplemented f aring method sense amplifie ness [5]. How nsing time and d out current tional curren re inapplicab Moreover, ower current ers [5, 6]. er of voltage t mplish the re earchers exper er power supp iu et. al. impl liable voltage The research the charging t the highest ense period i voltage requ at present w for RFID tr ELECTRO ELEK T 171 of Sense B. I. Reaz Electronic and gor, Malaysia, .5755/j01.eee.1 ders, embed EPROM are e EEPROM are transponders plifier must be EEPROM, th the read path mplifier (SA). ion non-volat h-speed read c s the power high-speed tical [4]. ype sense amp or EEPROM ds are used ers due to th ever, large po d extra contro are some of nt sensing ble to the voltage-type and power type SA have educed NVM rienced the re ply voltage a emented a low e SA in SMI showed that ime required average cur s 40μA. How uired for the this lowest ransponder. ONICS AND KTRONIKA MICR MIKR e Amplif z, M. A. M d Systems Engi phone: +603 20.4.1466 dded nonvo essential. Rea e usually the [1, 2]. The p e lower to incr he read access , which is stro One of the tile memories circuit with a supply beco low-power s plifiers have sensing. Usu frequently he advanced s ower consump ol logic to pre the drawback method. T low-power R sense ampli than current e been designe sensing cur eading consist and higher rea w cost, low p C 0.35μm CM t with the p for the voltag rrent consump wever, the lo design was 1 t voltage is 113 D ELECTR A IR ELEKT ROELECTRO ROELEKTRO fier in 0. M. Ali, M ineering, Univ 3-89216311, e olatile ading edge power rease time ongly main is to a low omes sense been ually, than speed ption, event ks of These RFID ifiers t-type ed so rrent. tency ading power MOS power ge SA mption owest 1.4V. not mem read meth perf EEP limi best colu EEP gene amp Whe for o of co 1 sh amp Fig. ‘0’ a RICAL ENG TROTECH ONICS ONIKA .18-μm C . Marufu versiti Kebang e-mail: mamun In this rese mories in RF ding current hod has be ormance, and PROM and se Though th tations, but lo solution for R To direct lo umn decoders PROM. On th erate a high v plifiers are u ereas, input/ou output data. Several rese onventional S hows the circ plifier. 1. Conventiona In the conv and ‘1’ are cl GINEERIN HNIKA CMOS P zzaman gsaan Malays n.reaz@gmail earch, a low ID tag is de and power w een used to decreasing se ense amplifie he floating-g w power desi RFID applicat gic operation and high-volt he other hand voltage for wr seful for sen utput (I/O) int earchers [3, 5, SAs by using c cuit diagram al sense amplifi entional SA c assified by us NG 2012. N Process sia, l.com voltage SA esigned to at where low v to achieve ensing time. er gate devices ign on circuit tions [8]. ns, the control tage switches d, the charge riting operatio nsing the ‘0 terfaces are u , 9] demonstr current sensin of the conv ier [3, 5, 9] circuit, the m sing a differen No. 4(120) for EEPROM tain the lowe voltage sensin better circu s has man level is still th l unit, row an are used insid pump used t ons. The sens ’ and ‘1’ bi sed as a carrie ates the desig ng method. Fig ventional sens measurement o ntial circuit fo M er ng uit ny he nd de to se it. er gn g. se of or
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I mpleme ntation of Sense Amplifier in 0.18-µm CMOS Process
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I
LDB
I
mafoRiacdpla
ecvaiitltns
fHicapsidpNs
ISSN 13
Impleme
L. F. RahDepartment ofBangi, 43600
http:/
Introduction
In RFI
memories (NVand writing opfactors in low-of the EEPRORFID reading s a key factor
affected by thchallenges fordevelop a robpower supplyower, the d
current [6]. Liand highly reprocess [7]. Tsupply 3.3V, ts 35ns and
during the sepower supply Nevertheless, satisfactory low
392 – 1215
entation
man, M. f Electrical, EUKM, Selang
//dx.doi.org/10.
ID transpondVM) like EEperations of E-power RFID
OM sense ampspace [3]. In
r to determine he Sense Amr new generatbust and highy voltage. Adesign of a omes very critent, current-tymplemented faring methodsense amplifieness [5]. Hownsing time andd out current tional currenre inapplicab
Moreover, ower current ers [5, 6]. er of voltage t
mplish the reearchers experer power suppiu et. al. implliable voltageThe research the charging t
the highest ense period i
voltage requat present
w for RFID tr
ELECTRO ELEK
T 171
of Sense
B. I. ReazElectronic andgor, Malaysia,
.5755/j01.eee.1
ders, embedEPROM are eEEPROM aretransponders
plifier must beEEPROM, ththe read path
mplifier (SA). ion non-volat
h-speed read cs the power high-speed
tical [4]. ype sense ampfor EEPROM ds are used ers due to thever, large pod extra controare some of nt sensing ble to the voltage-type and power
type SA haveeduced NVMrienced the reply voltage aemented a lowe SA in SMI
showed thatime required average cur
s 40μA. Howuired for the
this lowestransponder.
ONICS AND
KTRONIKA
MICR
MIKR
e Amplif
z, M. A. Md Systems Engi
phone: +603
20.4.1466
dded nonvoessential. Reae usually the
[1, 2]. The pe lower to incrhe read access , which is stroOne of the
tile memories circuit with a
supply becolow-power s
plifiers have sensing. Usufrequently
he advanced sower consumpol logic to prethe drawbackmethod. T
low-power Rsense ampli
than current
e been designe sensing cur
eading consistand higher reaw cost, low pC 0.35μm CMt with the pfor the voltag
rrent consumpwever, the lodesign was 1
t voltage is
113
ND ELECTR
A IR ELEKT
ROELECTRO
ROELEKTRO
fier in 0.
M. Ali, Mineering, Univ
3-89216311, e
olatile ading edge
power rease time ongly main is to
a low omes sense
been ually,
than speed ption, event ks of These RFID ifiers
t-type
ed so rrent. tency ading
power MOS
power ge SA
mption owest 1.4V.
not
memreadmethperf EEP
limibest
coluEEPgeneampWhefor o
of co1 shamp
Fig.
‘0’ a
RICAL ENG
TROTECH
ONICS
ONIKA
.18-µm C
. Marufuversiti Kebang
e-mail: mamun
In this resemories in RFding current hod has beformance, and
PROM and se
Though thtations, but losolution for RTo direct lo
umn decoders PROM. On therate a high vplifiers are uereas, input/ououtput data.
Several reseonventional Shows the circplifier.
1. Conventiona In the conv
and ‘1’ are cl
GINEERIN
HNIKA
CMOS P
zzaman gsaan Malaysn.reaz@gmail
earch, a low ID tag is deand power ween used todecreasing se
ense amplifie
he floating-gw power desi
RFID applicatgic operationand high-volt
he other handvoltage for wrseful for senutput (I/O) int
earchers [3, 5,SAs by using ccuit diagram
al sense amplifi
entional SA cassified by us
NG 2012. N
Process
sia, l.com
voltage SA esigned to atwhere low vto achieve ensing time.
er
gate devicesign on circuit tions [8]. ns, the controltage switches d, the charge riting operationsing the ‘0terfaces are u
, 9] demonstrcurrent sensinof the conv
ier [3, 5, 9]
circuit, the msing a differen
No. 4(120)
for EEPROMtain the lowe
voltage sensinbetter circu
s has manlevel is still th
l unit, row anare used insidpump used t
ons. The sens’ and ‘1’ bised as a carrie
ates the designg method. Figventional sens
measurement ontial circuit fo
M er ng uit
ny he
nd de to se it. er
gn g. se
of or
sc
petvl V
dstlatsewcfnaoacTbarc
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steadiness betcurrent. Howe
1) Highcomlargeconv‘0’ athe curreamourequparaout i
2) Floacurre‘0’ afromThercurreotheresul
3) The manycharcontcurreon k
Howeverpower consumessential for ntag. Moreovervoltage sense ogic circuit.
Voltage type
The Comdevices has bsimulations. Htwo main limiightly or med
are the main athickness is ussource and drexisting transiwith this samcontrol gate nfew couplingneighbor cellsas memory ceother. Based amplifier is decontrol gate nThis method between the trachieve the reading fidelitconventional s
Fig. 2 scomposed of circuits. The transistor MC
tween the reaever, the circuih power consu
mmon probleme reference cventional SA and ‘1’ data, wread out curent is neededunt of read o
uired for the allel data. Whein parallel [7];ating gate tranent levels by aand ‘1’ the pe
m the initial avrefore, a minoent and the rer is producedlts an amplifieconventionaly floating
rge. Hence, ittrol logic circuent and corre
key nodes. r, to reduce th
mption lower, on-volatile mr, to avoid inc
amplifier wi
sense amplifi
mpact Model (been used inHowever, thiitations. First, dium Doped aim of MOS csed as the oxirain junction uistor models mme type of dnode and the g capacitance may be affec
ells are gettingon these limesigned with node and the reduces the
ransistors. Molower sensin
ty without spesense amplifieshows the imf charge con
memory ceC and a select
ad out currenit has some drumption is po
m of the concurrent Iref iscircuit to diff
which is typicarrents. Tens
d for steadineout current: Ir
conventionalere, n is the nu; nsistor changeattribute degenerfect selectionverage of the
or variation beeference curre. This distincted sensing tim SA circuit isgate transistot is importanuit to prevent ectly manage
he sensing tima low voltageemories like E
correct read ouill not require
ier design
(CM) of the Fn conventionas compact mthin gate oxiDrain (LDD
compact modeide of the FGusually abrupmight becomedevices. Secosource, drain
e are exists.cted by the coug closer and
mitations, a voonly one capasource, draineffect of cou
oreover, this mng power/cureed deprivatioer. mproved desntrolling and ll consist oft transistor M
nt and a referrawbacks: ointed as the nventional SAs required byfferentiate betwally the averagof μA refer
ess. Thus, a ef ε (nIref, 3nIr
l SA for reaumber of bits
es the ‘0’ andneration. Thun of Iref is difread out curr
etween the reaent for one levtion of the cur
me [10]; s constructed ors, which s
nt to use an incorrect readthe charge st
me and to make sense amplifEEPROM in Rut current, thee an extra co
Floating Gate al SA for ci
model experiede transistors /MDD) diffuel. More than devices whil
pt. As a resulte essential to aond, betweenn and body no. Moreover, upling capacitsmaller one tooltage-mode sacitor between
n and body noupling capacitmethod is usefrrent and hi
on compared t
igned SA civoltage sen
f a floating MS. To reduce
114
rence
most A. A y the ween
age of rence large ref) is ading s read
d ‘1’ s, for
ffered rents.
ad out vel to rrent,
with stores extra d out tored
ke the fier is RFID e low ontrol
(FG) ircuit enced
with usions
7nm le the t, the adapt n the odes,
two tance o the sense n the odes. tance ful to
higher to the
ircuit nsing
gate e the
couponlyand MC)
pathMC task termthres
Fig. ampl
memthe transthresshowthe t
workstateat loOn tSG a
whe‘0’ s
inputhis Addline)
wheVtmc
Vout
transemp
pling capacitay one capacitothe FG node ).
In the modifh is controlled
and a selectinof the decode
minal CG is dsholds of mem
2. The circuitlifier
For the imp
mory cell implCEDEC 0.18sistor MC is shold voltage ws that the opthree control t
This modifieking state ane, to ensure thow level, all ththe other hanare set as:
ere P is the thrsignal, and Q w
At the beginuts C and B ar
time, Vout=0ditionally, wh) is charged to
=ere Vtms is the
is the threshoThe stored
as long as
In Fig. 2, fosistor MC, th
ploy bidirectio
ance between or has been us
(which is the
fied sense amd by the contrng gate (SG) ers is to contro
determined bymory cells.
diagram of th
proved voltaglemented in 28 μm processset to 1.5V tois set to −1Veration states
terminals: A, Bed voltage sen
nd out-of-worke drain and sohe three inputd, for the wo
= ( = reshold voltagwhen storing nning to turnre set to ‘0’. A
0 when the sten the stored
o = min( −threshold vol
old voltage forsignal '1' wil
or sensing thehe drain and onal diffusion
two adjacentsed between te gate of the M
mplifier, the serol gate (CG)with the tranol this selectin
y a voltage be
he proposed lo
ge-type SA, 27oC operatings. The thresho store a ‘0’
V to store a ‘1of this SA ar
B and C. nse amplifier rk state. In thource of the mts A, B and C
orking state, th
)/2, ,
ge of the MC a ‘1’ signal.
n off N2 and After that, A itored signal
d signal is ‘1
, 1.5 −ltage for MS r transistor MCll be generate
.
e stored voltagsource of M[11]. This vo
t memory celhe control gatMOS transisto
elected sensin) and transistosistor MS. Thng gate and thetween the tw
w voltage sens
the EEPROMg conditions o
hold voltage osignal; and th’ signal. Fig.
re controlled b
has two statehe out-of-wor
memory cell arC are set to ‘1he CG and th
(1
(2
when storing
N3 transistois set to ‘0’. Aof MC is ‘0
1’, the BL (b
), (3transistor, an
C. ed correctly a
(4
ge ‘0’ or ‘1’ aMOS transistoroltage mode SA
ls te or
ng or he he
wo
se
M of of he 2
by
s: rk re
1’. he
1)
2)
a
or, At 0’. bit
3)
nd
at
4)
at rs A
115
enables costs to be reduced; since it has no bias circuit. The parasitic capacitance is utilized as the charging load at the drain of N3 transistor. To decrease the charged voltage, the threshold voltage of the two inverter composed of NMOS transistors N4, N5 and PMOS transistors P2, P3 have been added. This will result a shorter charging time of BL and makes the lower read power dissipation. Additionally, the newly designed voltage type SA is capable of resisting the degeneration features of the floating gate transistor by using a voltage sensing method rather than a current sensing method. The transient current and charges for charging in one read process are described respectively:
( ) = β(V −V − V ) , (5)
β(V −V − V ) dt = C (V −V ), (6)
where VBLT is the transient voltage of the BL,CN3 is the parasitic capacitance at the drain of N3 , and T is the charging time = /(2 ).
Using equation (5) and (6), the average charging time and current can be obtained during one read period.
Results and discussion
The 27oC operating condition for the modified voltage-type sense amplifier and the conventional sense amplifiers have been designed and simulated in CEDEC 0.18-μm CMOS process. Simulations is executed to evaluate the circuit performance of the modified sense amplifiers with the previously reported voltage-type SA [12]. The transistors involved in the sensing circuitry were of equal size W/L= 0.18μ/0.18μ. The significant design factors are C1=0.1pF, SG=3V and CG=1.5V.
By using the critical design parameters listed in above table the output data (Vout) for the modified SA is shown in Fig. 3 under 2.6V power supply voltage. As shown in Fig. 4, the modified voltage type SA reads ‘0’ data at the beginning. At 0.4μS the SA reads ‘1’. The circuit is also able to work >2.6V, but above this operating voltage, the circuit experience noises.
Fig. 3. Simulation results of voltage SA for a 2.6V power supply Furthermore, depending on the principle of the
memory cell, VCG in equation (1) is the best value for voltage sensing and a lower voltage can be set for VCG. Using equation (2) and regulating the threshold voltage of the inverter in Fig. 3, the modified voltage mode SA is
capable of operating at voltages as low as 1V. The Vout data for a 1V power supply voltage are shown in Fig. 4.
The simulation results in Fig. 4 shows that the voltage required by the voltage-type SA can be significantly reduced from 2.6V to 1V, where the voltage was controlled by CG. In order to show the correct behavior of the voltage-type SA, the power supply voltage is set to 1V and the capacitive load to 0.1 pF.
Fig. 4. Simulation results of the average current Icn, Vout and VBL The corresponding current consumption for the
modified voltage-type SA is also shown in Fig. 4. Here the average current consumption during the read period is only 43μA for the maximum clock speed of 20MHz. This feature is useful for some electronic systems focused on low voltage and low power such as RFID transponder.
Fig. 4 also presents a comparison results among the Vout data, the average current consumption during the read period, and the corresponding bit line voltage under 1V power supply voltage. The figure further proves that the SA is capable of operating at a voltage as low as 1V. The circuit is also able to work <1V, but in this operating voltage, the circuit experience noises.
Generally, the required working temperature range of the RFID tag is from −25°C to 85°C. As, the modified voltage-type SA circuit is able to work within the temperature range from −25°C to 125°C. Therefore, this modified circuit has no power differentiation in working temperature of RFID tag.
A comparisons study of voltage-type sense amplifiers between this work and Liu et. al with minimum and maximum voltage level is shown in Table 1. From the study, it is shown that the circuit is able to work within 1V to 2.6V power supply voltages, which is lower than the Liu et. al.
Table 1. Comparison study of voltage-type sa between liu et. al. and this work
Research Vdd (Min)
Vdd (Max)
CMOS Technology
Liu et. al. 1.4V 3.3V 0.35 μm This Work 1V 2.6V 0.18 μm
The modified low voltage-type SA circuit layout is
designed in CEDEC 0.18-μm CMOS process. In Fig. 5, the completed chip layout of the modified low voltage SA is presented. In this layout, the capacitor connected with the control gate transistor is about 0.1pF. This small capacitor
otsts
F C
vpdEcttrwstvsf
LE
Cdevtev Le
singeti
only takes a sthe whole chipsize for each cthat the modifsize designed b
Fig. 5. A layout
Conclusions
An improvoltage SA cpresented in tdesigned by uEEPROM prconduction btransistors is uthe floating gresults, it has working over supply. The retype SA requvoltage-type Ssimulation resfrom the pow
L. F. Rahman, MElectrical Engine
Sense AmplifCMOS process todata. Memory accexperience the lavoltage-type SA iemperature range
voltage-type SA i
L. F. Rahman, Melektrotechnika.
Šuntinis stiprsiekiant sumažintinformacijos išrin
galios, kurios yra esant labai mažaiinkamas mažos įt
mall area of tp. In this resecell of the MOfied SA circuby Liu et. al.
t design of the l
oved design acircuit using this research. using the CEDocess. In th
between the used to sensegate transisto
been provena voltage ra
esults also veuired lower reSA designed sults confirm twer delineatio
M. B. I. Reaz, M.eering. – Kaunasfier is one of the
o achieve both thecess time, power
arger current or pis able to executee from -250C to s appropriate for
M. B. I. Reaz, – Kaunas: Tech
rintuvas (ŠA) yrai skaitymo galią
nkimo trukmė, galnetinkamos žem
i įtampai – nuo 1tampos aplikacijo
the circuit to earch, W/L =
OS transistors, uit size is low
low voltage-typ
and a comparaa voltage seThe modified
DEC 0.18-μm his research,
drain and e the stored vors. Accordingn that, the cirange from 1Verify that the eading curren
by Liu et. that this low on caused by
. A. M. Ali, M. Ms: Technologija,
e major circuits ine lower reading pr dissipation and power dissipatione under a very lo1250C. The comlow-voltage appl
M. A. M. Ali, hnologija, 2012. –a viena iš pagrindir padidinti jutimlios suvartojimas os įtampos RFID1 V iki 2,6 V. ŠAoms kaip RFID E
reduce the co0.18μ/0.18μ iwhich also pr
wer than the ci
pe SA
ative study ofensing method circuit has CMOS embethe bidirectsource of M
voltage (‘0’/‘1g to the resercuit is capabV to 2.6V pmodified vol
nt/ power thanal. Moreovervoltage SA isy the temper
Marufuzzaman.2012. – No. 4(12
n CMOS nonvolapower and superithe reliability of
n problems, whicow power supply
mpact layout desilications like RFI
M. Marufuzzam– Nr. 4(120). – Pdinių CMOS atm
mo operacijos patir EEPROM pati
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EEPROM. Il. 5, bi
116
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Implementation20). – P. 113–116atile memories. Tior reliability for f an EEPROM isch is not suitabley voltage (VDD) ign has been carrID EEPROM. Ill.
man. Šuntinio sP. 113–116. minties grandžių. tikimumą. RFID ikimumas labai paikomosioms sistrtas temperatūrų ibl. 10, lent. 1 (an
nge. Additionausing small tra
erences
Yasin F. M., KIdentification: Microwave Jou56–70. Liu D. S., ZoMemory Achievmemory for RMagazine. – IEEDaga J. M., PaG., GuichaouaEEPROMs embDesign & Test o68–75. Liu J., Wang XM. A low–volembedded flashIOPScience, 20Micheloni R., read path: buildof the IEEE. – IMing L. I., Kasense amplifieScience China I53(8). – P. 1676Liu D. S., Zou amplifier for University ScieHuang R, Zhodouble gate strumemory applicaSciences. – SpriXu F., He X. Q16 K bits embeInternational CSystems (ICCC1516–1520. Canet P., LaReliability in EProceedings of Symposium. – M
n of Sense Ampli6. The aim of this resensing operation
s vigorously influe for low voltagbetween 1V to 2
ried out to evalu 5, bibl. 10, tabl.
tiprintuvo įdieg
Tyrimo tikslas –transponderyje E
priklauso nuo ŠA emoms, išskaidymnuo -25 0C iki 1
nglų kalba; santra
ally, the circuansistors and c
Khaw M. K., REvolution of Trnal. – Horizon
ou X. C., Zhving Lower Pow
RFID tag IC /EE, 2006. – No
apaix C., Meraa J., Auvergnbedded in portaof Computers. –
X., Wang Q., Wltage sense amh memory // 10. – No. 31(10Crippa L., Sa
ding blocks andIEEE, 2003. – Nang J. F., Wanr for low–powInformation Sci6–1681. X. C., Yu Q., EEPROM memnce A., 2009. –ou F. L., Cai uctures for higations // Sciencinger, 2008. – N
Q., Zhang L. Kdded EEPROMonference on
CAS). – Chengd
alande F., RaEEPROM Nonv
the IEEE NonMarseille, Franc
Acc
ifier in 0.18-µm
esearch is to impn. In RFID transpuenced by the fee applications of2.6V VDD. The
uate the efficiency1 (in English; ab
gimas 0,18 µm C
0,18 µm CMOSEEPROM naudoja
savybių. Sroviniomo problemų. Pa
125 0C sričiai. Maukos anglų ir liet
uit size reducecapacitors.
Reaz M. B. I. RTransponder Cn House, 2006.
hang F. Embewer – New des// IEEE Circuio. 22(6). – P. 53andat M., Rechne D. Designtable systems o– IEEE, 2003. –
Wu D., Zhangmplifier for hiJournal of Se0). – P. 1–5. angalli M. Thd critical aspectNo. 91(4). – P. ng Y. Y. A no
ower nonvolaticiences. – Sprin
Zhang F. Newmory // Journ
– No. 10(2). – PY. M. Novel
gh density and ce China SerieNo. 51(6). – P.
Key design technM memory // Pr
Communicatiodu, Sichuan, C
azafindramoravolatile Memorn–volatile Memce, 2004. – P. 6
Rececepted after rev
CMOS Process
plement Sense Amponder, EEPROM
eatures of the SAf RFID transponSA circuit impley of the circuit.
bstracts in English
CMOS procese
S procese įdiegti ama duomenims o tipo ŠA sukelia
asiūlytas įtampos Modifikuotas žemo
tuvių k.).
ed significantl
Radio FrequencCircuit Design
– No. 49(6). – P
edded EEPROMign of EEPROMits and Device
3–59. hard S., Meduln techniques foon chips // IEE– No. 20(1). – P
Z., Pan L., Liigh–performancmiconductors.
he flash memorts // Proceeding537–553. vel voltage–typile memoriesnger, 2010. – N
w design of sensnal of ZhejianP. 179–183.
vertical channlow power flass F: Informatio799–806. niques of a 40 nroceedings of thns, Circuits an
China, 2004. – P
a J. Integratery Cell Design
mory Technolog66–69.
eived 2011 10 0vision 2011 11 2
// Electronics an
mplifier in 0.18µM are used to sto
A. Current type Snder. The proposeemented within thThe modified lo