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Hybrid Plasmonic Waveguides and Devices:
Theory, Modeling and Experimental Demonstration
by
Xiao Sun
A thesis submitted in conformity with the requirements for the degree of Master of Applied Science
Graduate Department of Electrical and Computer Engineering University of Toronto
Chapter 3 Properties of Hybrid Plasmonic Waveguides and Confinement Comparison of Plasmonic Waveguides ..................................................................................................... 20
3.2.1 Introduction to HPWG structure .............................................................. 21 3.2.2 Hybrid mode in one dimensional structure .............................................. 22 3.2.3 Mode transition as a function of dielectric thickness ............................... 25
3.3 Comparison of Sub-wavelength Confinement and Loss of Plasmonic Waveguides ............................................................................................................... 27
3.3.1 Analyzed waveguide structures ............................................................... 28 3.3.2 Method of comparision ............................................................................ 30 3.3.3 Confinement achievable in case of a dielectric waveguide ..................... 31 3.3.4 Properties of DLSPW .............................................................................. 32 3.3.5 Properties of plasmonic slot waveguide .................................................. 34 3.3.6 Properties of HPWG ................................................................................ 36 3.3.7 Comparison of various plasmonic waveguides........................................ 38
Chapter 4 Design and Optimization of the Hybrid Plasmoinc Waveguide as a TE-pass Polarizer ............................................................................................................................ 41
Chaper 7 Conclusion and Future works ............................................................................ 82 7.1 Summary of the Contributions ............................................................................ 82 7.2 Future Works ...................................................................................................... 83
Appendix A Optimizion of Silicon Width for Confinement of HPWG ........................... 84
List of Publications ........................................................................................................... 88
vi
List of Figures
Fig.2.1. (a) Single metal-dielectric interface and field profile of SP mode. (b) Schematic illustration of the electric field decay in both dielectric and metal layers. ................................................................................................................. 6
Fig.2.2. Dispersion relation of SPP at the interface between a Drude metal with negligible damping and a dielectric material. ................................................... 11
Fig.2.3. Prism coupling to SPP in the (a) Otto and (b) Kretschmann configuration. 12 Fig.2.4. Phase-matching of light to SPP using a grating. ......................................... 12 Fig.2.5. Structure of different types of plasmonic waveguide. (a) LRSPP waveguide.
Fig.2.6. Optical devices based on the HPWG. (a) Plasmonic laser. (b) Electro-optical modulator. (c) Light concentrator. (d) Ring resonance biosensor. ................... 18
Fig.3.1. Schematic of the hybrid waveguide. ............................................................ 22 Fig.3.2. Formation of the hybrid plasmonic mode. (a) The hybrid plasmonic
waveguide combines the structure of dielectric waveguide and plasmonic waveguide. (b) TM mode of three waveguides. (c) TE mode of three waveguides ........................................................................................................ 24
Fig.3.3. Field intensity of the TM and TE mode for the HPWG with silicon slab thickness 220 nm, spacer thickness 100 nm. .................................................... 24
Fig.3.4. HPWG structure and field profiles. (a) One-dimensional HPWG structure. (b) Electric filed intensity profile for varying silicon thickness (d). Spacer thickness is fixed at 100 nm. ............................................................................. 26
Fig.3.5. Power confinement and loss for the HPWG. (a) Power confinement for different dielectric layer thickness. (b) Propagation loss for different dielectric layer thickness. .................................................................................................. 27
Fig.3.7. (a) Structure of the silicon waveguide. (b) Guided power distribution in the silicon waveguide. ............................................................................................. 31
Fig.3.8. (a) Confinement factor and (b) power density of the silicon dielectric waveguide ......................................................................................................... 32
Fig.3.9. (a) Structure of the DLSPW structure. (b) Guided power distribution in the DLSPW. ............................................................................................................ 32
Fig.3.10. Confinement factor and power density associated with loss for the DLSPW. (a) Confinement factor. (b) Power density. (c) Propagation loss. (d) Power density vs. propagation loss ................................................................... 33
Fig.3.11. (a) Structure of the plasmonic slot waveguide. (b) Guided power distribution in the plasmonic slot waveguide. ................................................... 34
Fig.3.12. Confinement factor and power density associated with loss for the plasmonic slot waveguide. (a) Confinement factor. (b) Power density. (c) Propagation loss. (d) Power density vs. propagation loss ................................. 35
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Fig.3.13. (a) Structure of the HPWG. (b) Guided power distribution in the HPWG............................................................................................................................ 36
Fig.3.14. Confinement factor and Power Density associated with Loss for the HPWG with w= 200 nm. (a) Confinement factor. (b) Power density. (c) Propagation loss. (d) Power density vs. propagation loss ................................. 37
Fig.3.15. Normalized power density vs. propagation loss for three types of plasmonic waveguides. ..................................................................................... 38
Fig.3.16. Confinement factor vs. propagation loss for three types of plasmonic waveguides. ....................................................................................................... 39
Fig.4.1. (a) Three dimensional schematic of the HPWG TE-pass polarizer with input
and output silicon waveguides. (b) Cross section of the HPWG. (c) Cross section of the input/output silicon waveguide. The final dimensions are H = 220 nm, T = 3 μm, w = 500 nm, w′ = 250 nm, h = 200 nm, t =100 nm. ............... 42
Fig.4.2. Electric field intensity profiles at 1.55 μm for the (a) TE and (b) TM modes of the input/output waveguides for H = 220 nm, T = 3 μm, w = 500 nm, h = 200 nm. The definition of the variables is shown in (c). ......................................... 44
Fig.4.3. Electric field intensity profiles of the (a)TE and (b) TM modes of the HPWG section for H = 220 nm, T = 3 μm, w = 500 nm, w′ = 250 nm, h = 200 nm, t =100 nm. Wavelength of operation is 1.55μm. The definition of the variables is shown in (c). .................................................................................. 45
Fig.4.4. Propagation loss with different chromium cap width (w′) for H = 220 nm, T = 3 μm, w = 500 nm, h = 200 nm, t =100 nm. Wavelength of operation is 1.55μm. For the definition of the variables, see Fig. 4.1. (a) TE mode. (b) TM mode .................................................................................................................. 47
Fig.4.5. Propagation loss with different chromium cap thickness (t) for H = 220 nm, T = 3 μm, w = 500 nm, w′ = 250 nm, h = 200 nm. (a) TE mode. (b) TM mode. ................................................................................................................. 48
Fig.4.6. Propagation loss for the (a) TE mode and (b) TM mode. (c) HPWG length for 30 dB extinction ratio. (d) Propagation loss of the TE mode for length calculated in (c). The plots are with different spacer thickness (h) with other dimensions fixed of H = 220 nm, T = 3 μm, w = 500 nm, w′ = 250 nm, and t = 100 nm. .......................................................................................................... 49
Fig.4.7. Insertion loss of a 30 μm long TE-pass polarizer predicted by FDTD simulation. Device dimensions are as mentioned in the caption of Fig. 1. (a) Variation of insertion loss for the TM mode. (b) Variation of insertion loss for the TE mode with silicon width (w). ................................................................. 52
Fig.4.8. Power in the chromium layer and adjacent regions for the (a) TE mode and (b) TM mode with variation of silicon width (w). ............................................ 53
Fig.4.9. Insertion loss of a 30 μm long TE-pass polarizer predicted by FDTD simulation. Device dimensions are as mentioned in the caption of Fig. 1. (a) Variation of insertion loss for the TM mode. (b) Variation of insertion loss for the TE mode with spacer thickness (h). ............................................................ 54
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Fig.5.1. Fabrication process flow of the HPWG TE-pass polarizer. (a) SOI substrate. (b) Resist spin-coating and EBL for gold markers. (c) Gold deposition. (d) Gold lift-off. (e) Resist spin-coating and EBL for silicon nano waveguide (markers are not shown in this and following steps because they are far from waveguides). (f) RIE etching and resist removal. (g) Silica deposition by PECVD. (h) Resist spin-coating and EBL. (f) Chromium deposition and lift-off............................................................................................................................ 56
Fig.5.2. Design and Layout pattern of the polarizer. (a) Designed device. (b) Layout for one polarizer. ............................................................................................... 57
Fig.5.3. L-Edit Layout pattern of the polarizer. (a) Overview of the pattern; (b) close view of the polarizers in one block. .................................................................. 58
Fig.5.4. Low dose results in resist residues even for large areas. (Resist thickness is 340 nm, and fracture resolution is 10 nm) ........................................................ 60
Fig.5.5. Dose test for the ridge drawn in L-edit as 700 nm wide. (Resist thickness is 340 nm, and fracture resolution is 10 nm) ........................................................ 60
Fig.5.6. Dose test for trench drawn in L-edit as 100 nm wide. (Resist thickness is 340 nm, and fracture resolution is 10 nm) ........................................................ 61
Fig.5.7. dose test for the ridge drawn in L-edit as 700 nm wide. (Resist thickness is 340 nm, and fracture resolution is 25 nm) ........................................................ 62
Fig.5.8. dose test for the ridge drawn in L-edit as 700 nm wide. (Resist thickness is 500 nm, and fracture resolution is 10 nm) ........................................................ 63
Fig.5.9. Fabrication steps for alignment makers. (a) SOI wafer. (b) Spin coat ZEP resist. (c) Define maker shape and dimensions by E-beam writing. (d) Chromium deposition by thermal evaporation. (e) Gold deposition by thermal evaporation. (f) Lift-off process. (g) Top view of SOI wafer with gold markers............................................................................................................................ 64
Fig.5.10 (a) Gold marker covered by ZEP. (b-c) Gold marker after ebeam writing and development. (d) Gold marker covered by silica ....................................... 66
Fig.5.11. Fabrication steps for silicon waveguides. (a) Spin coat ZEP resist. (b) Define silicon waveguide pattern by E-beam writing. (c) RIE etch the uncovered silicon. (d) Resist removal. (e) Top view of silicon waveguides with markers. ............................................................................................................. 67
Fig.5.12. Silicon nano waveguides etched by RIE has slanted sidewalls. ................ 68 Fig.5.13. SEM picture of the 205 nm silica layer deposited over the whole sample by
PECVD. (a) Silicon waveguide under silica cladding. (b) Close view of the surface of the deposited silica. .......................................................................... 70
Fig.5.14. Fabrication steps for hybrid section metal lift-off. (a) Spin coat ZEP resist. (b) Define metal pattern by E-beam writing. (c) Deposit chromium by thermal evaporation. (d) Lift-off ZEP resist. (e) Top view of the final device. ............. 71
Fig.5.15. SEM picture of the rough surface of deposited chromium ........................ 71 Fig.5.16. Fabricated device with silicon reference nano waveguides and TE
polarizers of different HPWG lengths. ............................................................. 72 Fig.5.17. SEM images of (a) the cross section of the input/output/reference silicon
nano waveguides, (b) the cross section of HPWG section, (c) top view of the HPWG section, and (d) a closer top view of the HPWG section. .................... 73
ix
Fig.5.18. A sample with around 70 nm misalignment. SEM images of (a) the cross section of the HPWG section and (b) top view of the HPWG section. ............ 74
Fig.6.1. Experiment setup to measure the power transmission through waveguides.
........................................................................................................................ 76 Fig.6.2. Camera images of mode output profile for TE and TM mode at 1.55 μm
from the reference silicon waveguide and from the polarizer with a 30 μm HPWG section. ................................................................................................. 78
Fig.6.3. Insertion losses of the TE and TM modes for a 30 μm long HPWG TE-pass polarizer. ........................................................................................................... 79
Fig.6.4. Extinction ratios for a 30 μm long HPWG TE-pass polarizer. .................... 80 Fig.A.1. Confinement factor and Power Density for HPWG with w. (a)
Confinement factor. (b) Power density. ............................................................ 84
x
List of Tables
Table 4.1 Effective indices and coupling efficiency for the TE and TM modes at 1.55 μm ........................................................................................................ 51
Table 5.1: RIE etching recipe for silicon waveguides .............................................. 67 Table 5.2: PECVD silica deposition recipe at 300 C ................................................ 69
pattern by E-beam writing. (c) RIE etch the uncovered silicon. (d) Resist removal. (e) Top view of silicon
waveguides with markers.
(b)(a)
Silicon Silica
ZEP 520A
Gold
(c)
(d) (e)
68
The typical etching profile under SEM is shown in Fig. 5.12. The etched waveguides has
slanted sidewalls which are different from design. We have several recipes but were not
able to achieve a vertical wall for the silicon nano waveguides. Fortunately, this shape
change does not significantly affect the porlarizer performance. This will be discussed in
more detail in chapter 6.
Fig.5.12. Silicon nano waveguides etched by RIE has slanted sidewalls.
5.7 Silica Deposition
A 200 nm thick silica layer was deposited by PECVD. In this step, the silica layer
covered the whole sample, including the input/output waveguides.
The deposition system PlasmaLab System 100 PECVD (Oxford Instruments) supplies
silane (SiH4) and nitrous oxide (N2O) for silica deposition. They interact in the chamber
to form silica. The plasma process reaction is [43]
4 2 2 3 23 6 3 4 4SiH N O SiO NH N+ → + + (5.1)
69
According to [43], silanol (Si-OH) incorporation happens at substrate temperatures of
250-290 C and N-H bond formation occurs at substrate temperatures of 350-390 C. To
ensure the purity of silica, the deposition temperature is chosen at 300 C.
Before silica deposition, we opened the chamber and cleaned it with vacuum and IPA.
The physical cleaning process was carried out at a temperature of less than 50 °C. Later
after the deposition temperature and low pressure are reached, we run a plasma clean
recipe on the empty chamber at 300 C.
The PECVD deposition recipe is taken from the user database from ECTI and the steps
are summarized in Table 5.2.
Table 5.2: PECVD silica deposition recipe at 300 C
Steps Chamber condition Time 1 Pump down 2 minutes
2 Preheat Pressure: 1500 mTorr
Gas flow: N2 1000 sccm
3 minutes
3 Plasma clean RF power: 100 watts
Gas flow: N2 1000 sccm
Gas flow: N2 1000 sccm
1 minute
4 Silica deposition RF power: 45 Watt,
Pressure: 400 mTorr,
Gas flow: 30 sccm 5% SiH4/N2, 700 sccm N2O.
26 minutes
5 Pump down 1 minute
The deposition rate for this recipe is about 8 nm/min. After deposition the samples were
checked under SEM. The silica thickness measured under SEM is 205 nm as shown in
Fig. 5.13 (a). The sample has a low surface roughness as shown in Fig. 5.13 (b).
70
(a) (b)
Fig.5.13. SEM picture of the 205 nm silica layer deposited over the whole sample by PECVD. (a) Silicon
waveguide under silica cladding. (b) Close view of the surface of the deposited silica.
5.8 Chromium Deposition and Lift-off
To define the HPWG section, a chromium layer was deposited using thermal evaporation
and the lift-off process was performed. ZEP 520A was spin-coated on the top of the silica
layer as shown in Fig. 5.14 (a). The EBL was used to define a 250 nm wide region as
shown in Fig. 5.14 (b). Thermal evaporation was used to deposit a layer of chromium as
shown in Fig. 5.14 (c). A chromium cap sit on the top of the silica ridge after the lift-off
process as shown in Fig. 5.14 (d). In this step, different lengths (20 μm, 30 μm and 40 μm)
of HPWG sections for the polarizers were defined as shown in Fig. 5.14 (e).
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Fig.5.14. Fabrication steps for hybrid section metal lift-off. (a) Spin coat ZEP resist. (b) Define metal
pattern by E-beam writing. (c) Deposit chromium by thermal evaporation. (d) Lift-off ZEP resist. (e) Top
view of the final device.
The deposition quality was checked under the SEM and Fig. 5.15 shows the surface of
the chromium cap. The top surface is very rough. Fortunately, a smooth chromium top is
not required in our design.
Fig.5.15. SEM picture of the rough surface of deposited chromium
(a) (b) (c)
(d) (e)
Silicon Silica
Chromium
ZEP 520AGold
72
5.9 Final Device
An optical microscope image of the final device is shown in Fig. 5.16. A number of TE-
pass polarizers of various lengths (20, 30 and 40 μm) were fabricated on the same chip.
In addition, a number of reference channels were also fabricated. The reference channels
are identical to the TE-pass polarizer branches with the exception that they have no
HPWG sections.
Fig.5.16. Fabricated device with silicon reference nano waveguides and TE polarizers of different HPWG
lengths.
The sample was cleaved to a length of 4 mm for optical characterization. A SEM image of the
end facet of the input/output silicon nano waveguide is shown in Fig.5.17 (a). Figures 5.17 (b - d)
show the SEM images of the end facet and the top view of the HPWG section. The dimensions
of the silicon core and the silica cladding layer of the HPWG section are the same as the
input/output nano waveguides. A chromium cap is present only on the HPWG section. The
chromium cap is 250 nm wide and 150 nm thick. It is located almost at the middle of the HPWG
section with a small offset from the center (25 nm), which confirms the good alignment achieved
in our fabrication. The RIE etching process produced a trapezoidal shape for the silicon nano
Polarizer
Silicon nano waveguide
73
waveguide with the width of the trapezoid varying from 580 nm at the bottom to 420 nm at the
top. From the simulation results presented later, we shall see that this deviation from the original
design does not significantly affect the device performance.
(a) (b)
(c) (d) Fig.5.17. SEM images of (a) the cross section of the input/output/reference silicon nano waveguides, (b) the
cross section of HPWG section, (c) top view of the HPWG section, and (d) a closer top view of the HPWG
section.
As mentioned earlier, there may be slight misalignment between different layers due to
the fabrication process. We fabricated a second sample which shows a misalignment of
70 nm for the top layer as illustrated in Fig. 5.18. As we already considered the possible
misalignment and designed a narrow chromium cap (250 nm), the chromium cap still sits
74
on the top of the ridge, thus the performance of the final device is not significantly
affected.
(a) (b) Fig.5.18. A sample with around 70 nm misalignment. SEM images of (a) the cross section of the HPWG
section and (b) top view of the HPWG section.
5.10 Conclusion
In this chapter we have described the fabrication steps and presented the images of the
sample. The fabrication is compatible with standard SOI technology. The misalignment
between layers is within an acceptable range. Multiple polarizers and reference
waveguides are fabricated on the sample. In the next chapter we will report the results
from optical characterization of the device.
75
Chapter 6 Optical Characterization
In the previous two chapters we presented the details of the design of a compact HPWG TE-pass
polarizer and outlined the fabrication process. In this chapter we present results on the
characterization of the device. We measured the optical power transmission through the TE-pass
polarizer and compared the value with the power transmission through the reference silicon
waveguides for the TE and the TM modes. The device shows a high extinction ratio over a broad
band for a 30 μm long HPWG section. The results match well with simulations and confirm the
polarization diversity of HPWG.
6.1 Experimental Setup and Measurement Method
The experimental setup used for optical characterization of the HPWG TE-pass polarizer
is shown in Fig. 6.1. We used an end-fire scheme to test the fabricated device. Power
from a continuous wave tunable InGaAsP laser was coupled to free space from a single
mode fiber using a fiber-to-free-space coupler. The polarization of the incident light was
controlled using a combination of half wave plate and polarizing beam cube (PBS). The
sample was mounted on a rig and two 40× microscope objectives were used to couple the
light into and out of the sample. An infrared camera was used at the output to ensure that
light was coupled properly into only one waveguide at a time. The power output from the
waveguide was detected with a Germanium photodiode detector. Another Germanium
photodiode detector was used to detect the reflected power of the incident light from the
76
beam splitter just before the stage. The devices were characterized over a wavelength
range of 1.52 to 1.58 μm.
Fig.6.1. Experiment setup to measure the power transmission through waveguides.
There are various loss mechanisms that contribute to the total power loss between the two
detection points. There are losses from the light coupling in and out of the waveguides,
propagation along the silicon waveguides, coupling between silicon waveguides to the
HPWG section, and propagation along the HPWG section. The typical Fabry-Perot (FP)
loss measurement method is not suitable for this case, because the waveguides are lossy
and formed multiple cavities (two silicon waveguides and the HPWG section). The
insertion loss of the HPWG polarizer can be determined by comparing the transmission
of the waveguides with the HPWG section to that of the reference waveguides. We
fabricated several silicon nano waveguides with and without the HPWG section on the
same sample. The coupling loss from free space is similar for all waveguides because the
facet due to one cleaving is similar for all waveguides on the same sample (though we
haven’t characterized the coupling loss from free space for each waveguides). These
silicon waveguides were fabricated under the same condition, thus the propagation losses
77
from each silicon waveguide are comparable. When the power output of the TE-pass
polarizer waveguide was compared to that of the reference waveguide, the output
difference came from the loss form propagation through the HPWG section and coupling
between the silicon input/output nano waveguides and the HPWG section. Thus the
device insertion loss was measured. We compared the power outputs from a reference
waveguide and a polarizer with a 30 μm long HPWG section. The results are described in
the following.
6.2 Optical Characterization Results
The output mode profiles of both modes of the waveguides were captured with an
infrared camera. Figures 6.2 (a) and (b) show the images of the TE mode output from the
reference waveguide and the polarizer with a 30 μm HPWG section separately. The shape
and brightness of the image for the polarizer is comparable to those of the image for the reference
waveguide. Figures 6.2 (c) and (d) show the images of the TM mode output from the
reference waveguide and the polarizer separately. It is clear that the output from the HPWG is
much less than that from the reference waveguide for the TM polarized light.
(a) T
(c) T
Fig.6.2
waveg
The m
over
from
The e
mode
wave
polar
TE mode outpsilic
TM mode profsilic
2. Camera ima
guide and from
measured ins
a wavelengt
25 dB to 3
extinction ra
e. The exti
elength range
rizers and r
put profile frocon waveguid
file output frocon waveguid
ages of mode o
m the polarizer w
sertion losse
th range of
1 dB and th
atio is the di
inction ratio
e, as shown
reference w
m the referende
om the referende
output profile f
with a 30 μm H
es for both T
1.52 to 1.58
he insertion l
fference of t
o varies fro
n in Fig. 6.4
aveguides;
nce (b) TE
nce (d) TM
for TE and TM
HPWG section
TE and TM m
8 μm. The in
loss for the
the insertion
om 23dB t
. We have c
the perform
E mode outpu
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.
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hown in Fig.
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7
m the polarizer
m the polarize
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6.3 (marker
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rent betwee
78
r
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es
B.
M
a
ss
en
79
different devices. The error bars in the plot reflect such a difference. Although the device
is expected to work well beyond the 1.52 to 1.58 μm wavelength range, the finite
bandwidth of our tunable laser precluded measurement over a wider range. In addition to
the experimentally measured losses, simulated losses for the TM and TE modes of the
designed polarizer (with rectangular cross section) are shown in Fig. 6.3 (solid line). Fig.
6.3 also displays the simulated losses for the fabricated device with trapezoidal cross
section and 25 nm off center chromium layer (dashed lines). Simulation results for the
designed and fabricated device indicate that deviations of dimensions resulting from
fabrication imperfection have little effect on its performance (less than 3 dB for the TM
mode and less than 1 dB for the TE mode).
1.52 1.54 1.56 1.580
5
10
15
20
25
30
35
TE
Designed device (FDTD) Fabricated device (FDTD) Experimental
Inse
rtion
Los
s (dB
)
Wavelength (μm)
TM
Fig.6.3. Insertion losses of the TE and TM modes for a 30 μm long HPWG TE-pass polarizer.
80
1.52 1.54 1.56 1.5810
15
20
25
30
Designed device (FDTD) Fabricated device (FDTD) ExperimentalEx
tinct
ion
ratio
(dB
)
Wavelength (μm) Fig.6.4. Extinction ratios for a 30 μm long HPWG TE-pass polarizer.
From Fig.6.3 and Fig.6.4 we observe that the experimental results agree well with the
predictions from simulations. The slight discrepancy between the simulations and
experimental results is not unexpected. For our simulations, we have taken the material
properties of the chromium from Palik [31]. The permittivity of the chromium, especially
the imaginary part of the permittivity, can vary significantly depending on the deposition
conditions, which will result in some discrepancy [44]. Moreover, in our simulations we
have neglected the losses due to the scattering from surface roughness. When comparing
the TE-pass polarizer with the reference waveguides, the scattering losses from the
silicon nano waveguides is not an issue because both have similar scattering losses, but
there is additional scattering losses between the chromium and silica in the hybrid section.
The precision of the measurement also affects the experimental results; especially since
the output power of the TM mode is very small, making the recoding of the data for this
mode quite sensitive to the noise. All these contribute to the discrepancy between the
simulations and measurements for the polarizer, but as we can see by comparing the plots
in Fig. 6.3, the agreement between the measurement and simulation is still very good.
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6.3 Conclusion
We designed and fabricated a HPWG TE-pass polarizer. The results show it outperforms
previously proposed SOI compatible TE-pass polarizers. Although many different types
of TE-pass polarizers were investigated in the past, the number of experimental
demonstrations of SOI compatible TE-pass polarizer is very few [36, 37]. A silicon rib
waveguide coated with aluminum can act as a TE-pass polarizer [36], but the device
length is more than a millimeter and extinction ratio achieved is relatively low (< 20 dB).
Shallow-etched ridge waveguide TE-pass polarizers reported in [37] are very simple to
fabricate and the insertion loss of the TE and TM modes achieved for the device are
comparable to that of our current work, but the device is 1 mm long. Here, we have
achieved an extinction ratio of 23-28 dB and a moderate loss for the TE mode for a
device length of only 30 μm. Therefore, the device presented in this thesis is a compact,
broadband, SOI compatible TE-pass polarizer.
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Chaper 7 Conclusion and Future works
7.1 Summary of the Contributions We have analyzed the HPWG that consists of a metal plane separated from a high index
slab (silicon) by a low index spacer (silica). To illustrate the features of the HPWG, we
have also analyzed the plasmonic slot waveguide and the DLSPW in terms of
confinement and loss and tried to identify their relative advantages and limitations
compared to HPWG. The results show HPWG can confine the power in a compact region
with moderate propagation loss.
The HPWG also shows polarization diversity for the two fundamental modes. Taking the
advantage of this feature, we can design compact on-chip devices to control and
manipulate the on chip polarization state. A compact on-chip TE-pass polarizer based on
the HPWG concept has been designed, modeled, fabricated and experimentally
characterized. Although many different types of TE-pass polarizers have been
investigated in the past, the number of experimental demonstrations of silicon compatible
TE-pass polarizer is very few. The device is very compact with a low insertion loss, high
extinction ratio. It is highly compatible with standard fabrication techniques. It provides
the possibility to shorten integrated optical circuits.
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7.2 Future Works
We have successfully demonstrated the application of HPWG as a very compact TE-pass
polarizer. The experience gained during the design and experimental demonstration
activities should be useful for implementation of other on-chip HPWG devices like a
TM-pass polarizer [28], a polarization independent hybrid plasmonic coupler [29]. There
are some fabrication challenges that need to be overcome for future devices. In the
HPWG section, the silicon thickness varies for different applications. We need to
optimize the recipe to achieve a smooth surface for partial etching. The slanted silicon
wall is acceptable in the proposed TE-pass polarizer; however, it may be a problem for
other devices. Deep reactive ion etching (DRIE) method could be used instead of RIE to
achieve more vertical sidewalls.
When the waveguides are used in the integrated optical circuit, it is important to consider
the packing density and in particular how close two waveguides can be put without
causing significant power coupling. The HPWG can offer a way for achieving close
packing with the cost of some propagation loss. We would continue to analyze the
properties of HPWG for application for high density interconnection circuits.
With the experience in design, modeling and fabrication optical devices based on the
HPWG, we can continue further research on the integrated optical circuits, and
investigate the possibility of finding an efficient way to integrate optical circuits with
electronic circuits.
84
Appendix A Optimizion of Silicon Width for Confinement of HPWG
For the power density (D) vs. propagation loss analysis, the structure of HPWG is shown
in Fig. 3.13 (a). For the HPWG, the TM mode is coupled between surface plasmonic
mode and dielectric mode. This results a high power density in the gap (g), as shown in
Fig. 3.13 (b). The properties are affected by w, d, and g. In chapter 3 we have analyzed
the confinement for HPWG with w = 200 nm. The relation of confinement factor (Γ) and
power density (D) with w are plotted in Fig. A.1 for a fixed d = 200 nm. As shown in
Fig.A.1 (b), D is high when w = 200 nm. Thus we choose a fixed w = 200 nm and change
other dimensions in the analysis in chapter 3.
100 150 200 2505
10
15
20
25
30
35
w (nm)
g = 10 nm g = 50 nm g = 100 nm
Γ (%
)
(a)
100 150 200 250
20
40
60
80
100
g = 10 nm g = 50 nm g = 100 nm
D (m
w/μ
m2 )
w (nm)
(b) Fig.A.1. Confinement factor and Power Density for HPWG with w. (a) Confinement factor. (b) Power
density.
85
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List of Publications
Journal Contributions [1] X. Sun, M. Z. Alam, S. J. Wagner, J. S. Aitchison, and M. Mojahedi, “Experimental demonstration of a hybrid plasmonic transverse electric pass polarizer for a silicon-on-insulator platform,” Opt. Lett. 37, 4814-4816, 2012.
Conference Contributions [1] X. Sun, M. Z. Alam, S. Wagner, J. S. Aitchison, M. Mojahedi, “Compact hybrid plasmonic TE-pass Polarizer on SOI,” in Conference on Lasers and Electro-optics (CLEO)/Quantum Electronics and Laser Science Conference (QELS), OSA Tech. Digest (OSA, 2012), paper CTu1A.8.
[2] X. Sun, M. Z. Alam, J. S. Aitchison, M. Mojahedi, “Comparison of confinement and loss of plasmonic waveguides,” in Photonics Conference (IPC), 2012 IEEE , paper WX 5. [3] J. S. Aitchison, M. Z. Alam, X. Sun, and M. Mojahedi, “Hybrid Plasmonic Waveguides for On-chip Polarization Control,” in Frontiers in Optics Conference, OSA Tech. Digest (OSA, 2012), paper FTh3A.1.