Hybrid CMOS-SET Devices and Circuits: Modelling, Simulation and Design Santanu Mahapatra.

Hybrid CMOS-SET Devices Hybrid CMOS-SET Devices and Circuits: Modelling, and Circuits: Modelling, Simulation and DesignSimulation and Design

Santanu MahapatraSantanu Mahapatra

OutlineOutline

Introduction: CMOS scaling and emerging devicesIntroduction: CMOS scaling and emerging devices

Single Electron Transistor (SET)Single Electron Transistor (SET)

Compact Modelling of SETCompact Modelling of SET

CMOS - SET Hybrid ArchitecturesCMOS - SET Hybrid Architectures

CMOS - SET co-Simulation CMOS - SET co-Simulation

SETMOS – A Novel Hybrid CMOS-SET Device SETMOS – A Novel Hybrid CMOS-SET Device

Implementation of MV logic and Memory by Implementation of MV logic and Memory by SETMOSSETMOS

SET Technology – CMOS-SET co-FabricationSET Technology – CMOS-SET co-Fabrication

Conclusion Conclusion

IntroductionIntroduction

CMOS

Alternativedevices

CMOSAlternative devices

Feature Size (Feature Size (

μμ)m)m

0.1μm in 2002

CMOS IC evolutionCMOS IC evolution

Transition Region

Quantum devicesAtomic dimensions

YearYear

100

10

1

0.1

0.01

0.001

1960 1980 2000 2020 2040

CMOS

Alternativedevices

CMOSAlternative devices

(Feature Size (Feature Size

μμ)m)m

0.1μm in 2002

CMOS IC evolutionCMOS IC evolution

Transition Region

Quantum devicesAtomic dimensions

YearYear

100

10

1

0.1

0.01

0.001

1960 1980 2000 2020 2040

Aggressive scaling has pushed CMOS device dimensions towards sub-10nm limits

(i) electrostatic limits(ii) source-to-drain tunnelling (iii) carrier mobility(iv) process variations(v) static leakage(vi) Power density

Key problems of for Key problems of for sub-10nm MOSFETsub-10nm MOSFET

Pushing CMOS: Pushing CMOS: the 10 nm wallthe 10 nm wallPushing CMOS: Pushing CMOS: the 10 nm wallthe 10 nm wall

After J.D Plummer , Proc IEEE 2001

Life with and after CMOSLife with and after CMOS(micro(micro --)electronic switch)electronic switch

Aggressively miniaturized CMOS+ emerging devices

Quantum nanoelectronic devices

Solid state nanoelectronic devices

Molecular electronics

Quantum dots

Spin transistor

SETs

SEMs

Carbon nanotubes

Small conductive molecules

RSFQ RTDs

With CMOS After CMOS

HYBRID ICs

(micro(micro --)electronic switch)electronic switch

Aggressively miniaturized CMOS+ emerging devices

Quantum nanoelectronic devices

Solid state nanoelectronic devices

Molecular electronics

Quantum dots

Spin transistor

SETs

SEMs

Carbon nanotubes

Small conductive molecules

RSFQ RTDs

With CMOS After CMOS

HYBRID ICs

Drain Source

Single (Few) Electron Transistor Single (Few) Electron Transistor Gate

Ultra thin dielectric

Gate dielectric

CTD , RD

CTS ,RS CG

Drain (D)

Source (S)

Gate (G)

VGS

VDS

CTD: Drain tunnel junction capacitance

CTS: Source tunnel junction capacitance

RD : Drain tunnel junction resistance

RS : Source tunnel junction resistance

CG : Gate capacitance

CΣ = CG + CTD + CTS

Island

SET vs. MOSFET: Device PerspectiveSET vs. MOSFET: Device Perspective

n+ n+

Gate

p

pn+junctions

Source

conductiven-channel

MOSFET

DrainSource

Gate

tunnelingjunctions

Drain

SET

Source

conductiveisland

• electron conduction is one by oneelectron conduction is one by one• island is conductor, VG only changes the potential and thus controls tunneling

• needs opaque junctions: RT > RQ~26k• drain/gate controls Coulomb blockade

sourcesource

drain

• many electrons simultaneouslymany electrons simultaneously participate to conductionparticipate to conduction• gate potential invert the channel• junctions highly transparent •mainly gate controls the threshold

source

drain

source

drain

Engineers Like Numbers….Engineers Like Numbers….

1. RT > RQ = h/e2 = 26k

2. e2/CΣ > kBT CΣ < e2/ kBT

where = 10 (Memory Application), 40 (Logic Application)

CΣ (aF) T = 10 T = 40 (nm)

10 18K 4.6K 46

5 37K 9K 23

1 195K 46K 4.6

0.5 370K 92K 2.3

0.1 1855K 463K 0.5

Present Tech.

RT = 0.5-1M

CΣ = 2-3 aF

Characteristics of SET (1)Characteristics of SET (1)

-25

-20

-15

-10

-5

0

5

10

15

20

25

-0.08 -0.04 0.00 0.04 0.08

Drain to source voltage, VDS (V)

Drain to source current, I

DS

(nA)

0.02 V

0.0 V

0.04 V

0.06 V

e/CΣ = 0.04V

T = 1K

CCTDTD= C= CTSTS= 1aF, C= 1aF, CGG= 2aF, R= 2aF, RTDTD = R = RTS TS = 1M= 1M

0

2

4

6

8

10

12

14

-0.10 -0.05 0.00 0.05 0.10

Gate to source voltage, VGS (V)

Drain to source current, I

DS

(nA)

0.05V

0.04V0.03V

e/CΣ = 0.04V

T = 1K

e/CG

IIDSDS vs. V vs. VGSGS @ #V @ #VDSDSIIDSDS vs. V vs. VDSDS @ #V @ #VGSGS

Gate to source voltage, VGS (V)

-0.01 0.00 0.01 0.02 0.03 0.04

Drain to source current, I

DS (nA)

10-3

10-2

10-1

100

101

VDS = 0.03V5.8K [80]

11.6K [40]

23.2K [20]

IIDSDS vs. V vs. VGSGS @ #T @ #T

Characteristics of SET (2)Characteristics of SET (2)

Background Charge (BC) effectBackground Charge (BC) effect

When BC is integer (n) there are no change in SET characteristics, however, it experienced a shift of (BCeffe)/CG on VGS axis when BC is fractional.

0

1

2

3

4

5

6

7

8

9

-0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08

Gate to source voltage, VGS (V)

Drain to source current, I

DS

(nA) ne n + 0.25e n - 0.25e

T =1K, VDS = 0.03 V

For proper operation,

BC < n + 0.1e

A second gate with proper bias can compensate the B.C. Effect!

Carrier Transport in SETCarrier Transport in SET

-

2

3

0

D I S

1

5

6

-

2

3

0

D I S

1

2

-

2

3

0

D I S

1

23

4

4

CTD , RD

CTS ,RS

Drain (D)

Source (S)

Gate (G)

CG

VVISIS = (C = (CGG/C/CΣΣ)V)VGSGS + (C + (CTDTD/C/CΣΣ)V)VDSDS

= e/(2CCΣΣ); V); VDD = = ; VS = 0 constant

2

3

OFF (C.B.)ON ON

Tunneling occurs only when lVISl or lVDIl >

SET Simulation TechniquesSET Simulation Techniques

A successful implementation of SET as a A successful implementation of SET as a post-CMOS VLSI Candidate demands spice-post-CMOS VLSI Candidate demands spice-compatible compatible COMPACT analytical modelsCOMPACT analytical models

Monte CarloMonte Carlo

(SIMON, MOSES)(SIMON, MOSES)

+ Accurate+ Accurate

+ Applicable for any SE device+ Applicable for any SE device

- Time Consuming (specially for - Time Consuming (specially for current biased SET, resistance)current biased SET, resistance)

Master EquationMaster Equation

(SETTRAN)(SETTRAN)

+ Faster than MC+ Faster than MC

- Time consuming for big circuits- Time consuming for big circuits

Macro ModelMacro Model + Spice Compatible+ Spice Compatible

- Non Physical- Non Physical

SET Compact Analytical Model- MIB*SET Compact Analytical Model- MIB*• Based on the Orthodox theory, i.e., charge discrete,

energy continuous, etc.

-

0

D I S

IS

ID

VS

VD

IDS =IDIS

ID + IS

ID = VD/RD

IS = VS/RS

At T <<e2/CΣ , VD and VS are either positive or zero

2

ISID

IDS

*S. Mahapatra et al. EDL 02, IEDM 02,TED 04

The Complete MIB ModelThe Complete MIB Model

)1(I

)0(I)1(I

)2(I

)1(I)0(I)1(I)0(I

)0(I)1(I)1(I)0(I)1(I)0(II

S

DD

D

SSDS

DDSSDSDS

−+++

++=λ

⎟⎟⎠

⎞⎜⎜⎝

⎛ +−−−

+−=

T

island

islandS

V

)1n2(Vexp1

)1n2(V)n(I

αλ

αλ

⎟⎟⎠

⎞⎜⎜⎝

⎛ −+−−−

−+−=

T

islandDS

islandDSD

V

)1n2(VVexp1

)1n2(VV)n(I

αλλ

αλλ

where

VT is thermal voltage and λ holds the sign of VDS

and

Model is valid for VDS 3e/CΣ and T < e2/(10kBCΣ)

Model VerificationModel Verification

0

3

6

9

12

15

-40 -20 0 20 40 60 80

Gate to source voltage, VGS (mV)

Drain to source current, I

DS (nA)

10

20

30

40

45

50

55VDS (mV) =

T = 10Ke/CΣ = 40mV

0.00

0.00

0.01

0.10

1.00

10.00

-10 0 10 20 30 40

Gate to source voltage, VGS, (mV)

Drain Current, I

DS, (nA)

5K

10K

15K

20K

VDS = 30 mV

10-4

10-3

10-2

10-1

1

10

CCTDTD= C= CTSTS= 1aF, C= 1aF, CGG= 2aF, R= 2aF, RTDTD = R = RTS TS = 1M= 1M

Symbol: MC Solid Line: Analog MIB Dotted Line: Digital MIB

IIDSDS vs. V vs. VGSGS @ #V @ #VDSDS IIDSDS vs. V vs. VGSGS @ #T @ #T

SET INVERTERSET INVERTER

VVSSSS = = e/2(Ce/2(CGG + C + CTT))

VVinin

VVoutout

CTS = CTD = CT

VVSSSS = e/2(C = e/2(CGG + C + CTT))

-16

-12

-8

-4

0

4

8

12

16

-20 -10 0 10 20

Vin (mV)

Vout

(mV)

CG + CT = 4aFT = 5K

131.67

CG:CT =

RD = RS = 1M

-12.0

-8.0

-4.0

0.0

4.0

8.0

12.0

0 10 20 30 40 50 60

Time (ns)

Input and Output voltage (mV)

T = 5KCL = 1fF

CG : CT = 3:1

Power Dissipation in SET Logic* (1)Power Dissipation in SET Logic* (1)

-15

-10

-5

0

5

10

15

-20 -10 0 10 20

Input,Vin, (mV)

Output, V

out

(mV)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

VDD

to V

SS current, I

static

,(nA)

There is a non-zero static current from VDD to VSS when the SET inverter is in Logic HIGH or LOW, however this static current is zero during logic transition, which is just opposite to the CMOS inverter.

*S. Mahapatra et al. IEDM 02, DAC 02

Power Dissipation in SET Logic (2)Power Dissipation in SET Logic (2)

-15

-10

-5

0

5

10

15

-20 -10 0 10 20Input voltage, Vin (mV)

Output voltage, Vout (mV)

Static Current, I (nA)

T=0.1K

20K

10K

50K 50K

0.1K

+Vdd

-Vdd

Vin Vout

VDD = 20 mV

RTS = RTD = 1M

CG = 3aFCTS = CTD = 1aF

20K

10K 10 -9

10 -10

10 -11

10 -8

10 -7

Power @ 0.1K (W)

Power Dissipation in SET Logic (3)Power Dissipation in SET Logic (3)

1.1. Static Power Dissipation (PStatic Power Dissipation (Pstaticstatic))

2.2. Dynamic Power Dissipation (PDynamic Power Dissipation (Pdynamicdynamic))

3.3. Temperature Induced Leakage Power Temperature Induced Leakage Power Dissipation (PDissipation (Pleakageleakage))

PPtotaltotal = P = Pstaticstatic + P + Pdynamicdynamic + P + Pleakageleakage

In SET logic, power dissipation is essentially static: (~ 10~ 10-8-8 W), which is almost W), which is almost 4-5 decades lower than CMOS!

SET Random Number Generator*SET Random Number Generator*Conventional SET Based

Schematic

Noise Source

Thermal, Shot Noise Single Electron Capture/Emition

Noise (Vrms) ~1μV ~0.1V

Size On Board (10-100 cm2) On Chip (ultra small, ultra low power dissipation)

Noise Source

Random Bit Stream

AMP. COMPARATOR

VOUT

VIN = Const.

Memory Node

Random Bit Stream

*Toshiba, IEDM 02

• Room temp. operation (randomness increases with temp.)• RTS ratio greater than one decade (highest)

CMOS & SET: Competitor/Collaborator?CMOS & SET: Competitor/Collaborator?

SETSET CMOSCMOS Nanoscale deviceNanoscale device Ultra low power dissipationUltra low power dissipation New functionalitiesNew functionalities

High SpeedHigh Speed Very Stable TechnologyVery Stable Technology

–– Lack of room temperature Lack of room temperature operable technologyoperable technology

–– Reproducibility at nanoscaleReproducibility at nanoscaleLow Current drive (~nA)Low Current drive (~nA)Background charge effectBackground charge effect

SCE/DIBLSCE/DIBL Power dissipationPower dissipation Process variations atProcess variations at

nanoscalenanoscale

Concept of Hybrid CMOS-SET Concept of Hybrid CMOS-SET ArchitectureArchitecture

Practical SET digital circuit applications are likely not Practical SET digital circuit applications are likely not feasible with a pure Single Electronics approach, feasible with a pure Single Electronics approach, mainly due to its low current drive mainly due to its low current drive

Combining SET and CMOS, and exploiting the Combining SET and CMOS, and exploiting the Coulomb Blockade oscillation phenomenon of SET Coulomb Blockade oscillation phenomenon of SET and high current drive facility of CMOS, one can and high current drive facility of CMOS, one can bring out new analog functionalities, (neuron cell, bring out new analog functionalities, (neuron cell, Multiple Valued Logic) which are very difficult to Multiple Valued Logic) which are very difficult to implement by pure CMOS approach.implement by pure CMOS approach.

Challenges of Hybrid CMOS-SET Challenges of Hybrid CMOS-SET Architecture DesignArchitecture Design

Enable advanced SET/CMOS co-Enable advanced SET/CMOS co-

simulation and designsimulation and design Development of common technological Development of common technological

platformplatform Innovation on new functionalities of Innovation on new functionalities of

hybrid IC architectures, which are really hybrid IC architectures, which are really

un-paralleled to the pure CMOS circuits. un-paralleled to the pure CMOS circuits.

CMOS-SET Co-simulation* (1)CMOS-SET Co-simulation* (1)

Proposed model MIB is implemented in SMARTSPICE** through its Verilog-A (AHDL) interface

It is assumed that interconnect capacitances at gate, source and drain terminals are much bigger than the SET device capacitances. Therefore SET characteristics depends only on the nodal voltages.

Model parameters are device capacitances (CG,CG2, CTD,CTS), device Resistances (RD,RS) and Background Charge which could be defined through the SPICE MODEL CARD.

* S. Mahapatra et al., ICCAD 03 **SILVACO International

CMOS-SET Co-simulation (2)CMOS-SET Co-simulation (2)

Verilog-A

SET module

VerilogA Compiler

C file

C-compiler

.so file

SPICE NETLIST

SMARTSPICE

SOURCE

RUN

module set(drain, gate1, gate2, source); inout drain, gate1, gate2, source; electrical drain,gate1,gate2,source; // Default value of the model parameters

parameter real CTS = 1e-18, CTD = 1e-18 parameter real CG = 2e-18, CG2 = 0; parameter real RD = 1e6, RS = 1e6; parameter real BC = 0; analog begin ::::::::::::::::::::::::::::::MIB Subroutine end endmodule

SMARTSPICE simulation flowSMARTSPICE simulation flow

Circuit Simulation: Neuron CellCircuit Simulation: Neuron Cell

VIN

VOUT

VOFFSET1 VOFFSET2

VSS

VDD

M1 M2

M3

0.1

0.3

0.5

0.7

0.9

1.1

1.3

1.5

0.0 0.5 1.0 1.5 2.0

Input VIN(V)

Output V

OUT

(V)

VOFFSET1 = 1V

VOFFSET2 = 1V VOFFSET1 = 0.5V

VOFFSET2 = 1V

T = 300 K

* M. Goossens, * M. Goossens, Delft University PressDelft University Press

SET : CG = CG2 = 0.04aF, CTD = CTS = 0.02aF, RD = RS = 1M

PMOS: L = 0.5μm, W = 0.8μm, TOX = 9.74nm, VTH = 0.55

Circuit Simulation: MVL CellCircuit Simulation: MVL Cell

Vin

VGG Vout

Experimental

0

1

2

3

4

5

6

1 2 3 4 5

Vin(V)

Vout

(V)

SimulationMemoryQuantizer

SET: CG = 0.27aF, CTD = CTS = 2.7aF, RD = RS = 200k

NMOS: W = 12μm, L = 14μm, Tox = 90nm, VTH = 0.64V

VGG is set to 1.08V and Vout is hard-limited at 5V

*H. Inokawa*H. Inokawa et al., TED ‘03 et al., TED ‘03

EPFL’S Variable Hysteresis Cell* EPFL’S Variable Hysteresis Cell*

IBIAS

VIN

S1 S2

IINIBIAS

VIN

S1 S2

IIN

0

10

20

30

40

50

60

0.00 0.10 0.20 0.30 0.40

Input Voltage VIN (V)

Input Current I

IN (nA)

T = −1500C

IBIAS = 10 nA

20 nA

30 nA

40 nA

50 nA

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0 10 20 30 40 50 60

Input Current IIN (nA)

Input Voltage V

IN (V)

T = −1500C

IBIAS = 10 nA

20 nA30 nA

40 nA

50 nA

CG = 0.2aF,

CTD = CTS = 0.15aF,

RD = RS = 1M

S. Mahapatra and A.M.Ionescu et al. JJAP’04, IEEE NANO ‘04

SETMOS Device – C.B. at SETMOS Device – C.B. at μμA Range!A Range!

S

D IBIAS

G

Drain (D)

IBIAS

Source (S)

Gate (G)

VGS2

Log10 IDS2

Exponentially amplified drain current

~e/CΣ

e/CG

VGS1

V1DS

VDS1,MAX

IDS1

VDS2 VDS1 VGS2

VGS1

IDS2

Source (S)

Drain (D)

Gate (G)

IBIAS

If VDS1,MAX <= VTH, MOS is operating just

under VTH (subthreshold)

S. Mahapatra et al., IEDM 03, EDL 04

SETMOS Device Characteristics (1)SETMOS Device Characteristics (1)

IIDSDS vs V vs VGSGS @ #V @ #VDSDS

CG = 0.2aF

CTD = 0.15aF

CTS = 0.15aF

RD = 1M

RD = 1M

0.00

0.20

0.40

0.60

0.80

1.00

1.20

-1.00 -0.50 0.00 0.50 1.00

Gate to Source Voltage, VGS (V)

Drain to Source Current, I

DS (μ )A 0.5

0.4

0.30.20.1

VDS ( ) =V

T = −1000CIBIAS = 40nA

e/CG = 0.8V

L = 65nm

W = 100nm

VTH = 0.32V

TOX = 1.7nm

Calibrated 65nm BSIM4

model

[BSIM Web]

CΣ = 0.5aF

Ø ~ 2.5nm

SETMOS Device Characteristics (2)SETMOS Device Characteristics (2)

Gate to Source Voltage VGS (V)

0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

Drain to Source Current I

DS (A)

10-10

10-9

10-8

10-7

10-6

T = 250C

-2250C

VDS = 1VCG = 0.2aF

CTD = 0.15aF

CTS = 0.15aF

RD = 1M

RD = 1M

L = 65nm

W = 100nm

VTH = 0.32V

TOX = 1.7nm

1000C

IDS vs. VGS @ #T

Sub Ambient (00C to –1500C) Operation:

1) Realistic SET (Ø ~ 2.5nm)

2) Improved MOS Characteristics in terms of SS, PDP, leakage [I.Aller et al., ISSCC ‘00 ]

Sub-ambient operation of CMOSSub-ambient operation of CMOS

Roadmap

New Architectures

Sub-ambient operation

BU

LK

Y. Taur and E.J. Nowak, IEDM 97

At sub-ambient temp.1) Mobility increases

2) Static Power dissipation decreases

3) Sub. Slope improves

4) Speed increases

SETMOS NDR DeviceSETMOS NDR Device

IBIAS

Drain (D)

IBIAS

Source (S)

VIN

IIN

Gate (G)

VGS2 = VDS1

Log

10 IDS2

NDR

PDR

VDS2 = VIN

VGS1 = VIN

VDS1

Slope: CG/(CTS+CG)

Slope: − CG/CTD

SETMOS NDR Device Characteristics SETMOS NDR Device Characteristics

0.0

1.0

2.0

3.0

4.0

5.0

6.0

0.00 0.50 1.00 1.50 2.00

Input Voltage, VIN (V)

Input Current, I

IN (μ )A

T = −1000C

50nA

40nA

30nA

20nA

IBIAS (nA)=

ΔVIN

IIN vs. VIN @ #IBIAS

-60

-40

-20

0

0.0 0.5 1.0 1.5 2.0

VIN (V)

IG (nA)

50nA

IBIAS = 20nA

Gate Leakage

Effect

IBIAS

VIN

IG

No impact of leakage

IG < IBIAS/10

Interconnect Issues in Nanoscale ICsInterconnect Issues in Nanoscale ICs

After K. Banerjee et al. Proc. IEEE 2001

Not only the fundamental limitations of the nano-scaled MOSFET, but also the interconnect limits have threaten to decelerate or halt the historical progression of the semiconductor industry because the miniaturization of interconnects, unlike transistors, does not enhance their performance

As larger the chips become, the number of local modules grows as l2 (where l is the chip edge length) and the number of interconnects in a generally connected network grows as (l2!)

Multiple Valued (MV) Logic: MotivationMultiple Valued (MV) Logic: MotivationMV Logic is a logic system where the radix is more than 2.MV Logic is a logic system where the radix is more than 2.

radix (r) = 2 (binary), 3(ternary), 4 (quaternary)radix (r) = 2 (binary), 3(ternary), 4 (quaternary)

Binary AnalogMVMV

The information per line carried by binary system (either 0 or 1) is much less than analog system (infinity). That’s why interconnect complexities have always been a problem in Digital (Binary) ICs than Analog one.

However, digital systems have other advantages compared to the analog counterpart in terms of precision, stability, noise immunity etc.

BUT ARE THOSE ADVANTAGES SOUGHT TO BE FOUND ONLY IN THE BINARY DOMAIN????

MV Logic ApplicationsMV Logic Applications(i)(i) Complete replacement of Binary world by MV logic may Complete replacement of Binary world by MV logic may

not be possible, however a hybrid binary-MV system not be possible, however a hybrid binary-MV system can be used to solve the interconnect complexities.can be used to solve the interconnect complexities.

(ii)(ii) Large scale memories, Content Addressable MemoriesLarge scale memories, Content Addressable Memories

(iii)(iii) Neural Network, Intelligent SystemsNeural Network, Intelligent Systems

(iv)(iv) Advanced systems, e.g., molecular computing systemAdvanced systems, e.g., molecular computing system

Pass Gates0, s1,……..sk

(substrates)

e0, e1,……..ek

(enzymes)

0 (if s=si and e = ei)

s (otherwise)

MV Logic ImplementationsMV Logic ImplementationsConcept of MV logic is NOT AT ALL very new, however its CMOS implementation has always been strugling because:

1. MOSFET is a single threshold device

2. CMOS implementation of MV logic either demands MOSFETs having different threshold voltage on the same wafer or highly asymmetric (like 200:1) device aspect ratio.

However, the Coulomb blockade oscillations (multiple However, the Coulomb blockade oscillations (multiple threshold points) threshold points) could be directly linked to MV operationscould be directly linked to MV operations..

SETMOS, which combines the features from both SET and CMOS could be an attractive candidate for MV logic and memory realization.

SETMOS Quaternary Literal Gate* (1)SETMOS Quaternary Literal Gate* (1)Literal Gate (axb) : f(x) = r –1 when when a x b else 0

Universal Literal Gate (xs): f(x) = xs = r 1 when x = s S else 0

Here, for quaternary logic system, r = 4, S = (0,1,2,3), and a, b, x, s S.

Example: if x = (0,1,2,3) 2x3=(0,0,3,3) and x1,3 = (0,3,0,3)

VGS2

VIN

VOUT

IBIAS IC

VIN

VZ VZ

VOUT

VT

V GS2

VZ

V IN

IBIAS

IC

V Z V OUT

Working Principle:Working Principle:

*S.Mahapatra and A.M.Ionescu, submitted to TNANO

SETMOS Quaternary Literal Gate (2)SETMOS Quaternary Literal Gate (2)

0.00

0.30

0.60

0.90

1.20

0.00 0.30 0.60 0.90

VIN (V)

VOUT

(V)

IC = 0.4uA

IBIAS = 59nA

VGS2 = 0.35V

00C

-500C

-1000C

x1,3

Gate

0.0

0.3

0.6

0.9

1.2

0.0 0.3 0.6 0.9

VIN (V)

VOUT

(V)

IC = 0.4uA

IBIAS = 55nA

VGS2 = 0.123V

00C

-500C

-1000C

2x

3 Gate

Using literal gates one can implement the Transmission Gate (T-Gate) which is a building block of all MV logic functions.

04 = 0V, 14 = 0.3V, 24 = 0.6V, 34 = 0.9V

Binary-to-Quaternary ConverterBinary-to-Quaternary Converter

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0 100 200 300 400 500

Time (ns)

Voltage (V)

LSB

MSB

VOUT

MSB

LSB

VDD

VDD

VDD

VDD

04

14

24

34

VB1 VB2

VB2 VB1

VB1 VB2

VB1 VB2

VOUT (MVL)

MSB

LSB

MSB

LSB

MSB

LSB

2-to-4 binary

MOS

-SET hybrid decoder

04 = 0V, 14 = 0.3V, 24 = 0.6V, 34 = 0.9V 04 = 0V, 14 = 0.9V

Quaternary-to-Binary ConverterQuaternary-to-Binary Converter

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0 100 200 300 400 500

Time (ns)

Voltage (V)

LSB

MSB

VIN 2x3

x1,3

VIN (MVL)

MSB

LSB

Interconnect Reduction SchemeInterconnect Reduction Scheme

Module 1

Module 2

I1

I2

O1

O2

I1

I2

O1

O2

Module 1

Module 2 B2Q

Q2B

O1

O2

I1

I2 Q2B

I1

I2 B2Q

O1

O2

Traditional Binary System

Hybrid Binary-MV System

Global InterconnectsGlobal InterconnectsLocal InterconnectsLocal Interconnects

SETMOS MV SRAM (1)SETMOS MV SRAM (1)

IBIAS

VDS

IDS

VDS

IDS

I0↑ I1↑

I2↑

I2↓ I1↓

I0↓

V0 ≡ 04 V1

≡ 14 V2 ≡ 24 V3

≡ 34

IC

I0↑ > I2↓

IBIAS

VDS

IDS

IK IC

IDS

VDS

IK

V0

V1

V2

V3

I0↑

I1↑

I2↑ I2↓

I1↓

I0↓

IC = (I0↑ + I2↓)/2

NDR

Hysteresis

SETMOS MV SRAM (2)SETMOS MV SRAM (2)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

0 2 4 6 8 10 12

IDS (μA)

VDS ( )V

IBIAS = 80nA

60nA

70nA

T = −500C

T= -1000C @ 70nA

T= 00C @ 70nA

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

0 2 4 6 8 10

IDS (μA)

VDS ( )V

T = −500C

IBIAS = 70nA

BC = 0

BC = -0.1

BC = 0.1

SETMOS MV SRAM (3)SETMOS MV SRAM (3)

WLW

BLR

IC

IBIAS Buffer

WLR

BLW

MW MW

IR

• IR~1μA (100 times larger than some other MOS-SET approaches)

• Writing is ideally instanteneous, Reading time is in the same order of conventional CMOS SRAM

• Minimum Transistors needed to develop one SRAM cell by pure CMOS approach is 12 [U. Cilingiroglu, IEEE CAS II, 2001]

SET TechnologySET Technology Unlike CMOS, there is no fixed, well defined Unlike CMOS, there is no fixed, well defined

technology for SET fabricationtechnology for SET fabrication

SET could be made by Si, Metal, III-V Material or even SET could be made by Si, Metal, III-V Material or even by Carbon Nanotubesby Carbon Nanotubes

PADOX – SD [NTT]

Undulated Film – MD [Toshiba]

Nano-grain PolySi – MD [Hitachi]

Electronic SET – SD [Korea]

MOS-SET – SD [LETI]

Some of the possible Si-SET technologies are:

SD : Single Dot MD: Multiple Dot

EPFL

Single Dot SET Fabrication (1)Single Dot SET Fabrication (1)

8 inch0.4mm ISOLATE 5nm

Si/SOI waferSET island

FEEL THE CHALANGE !!FEEL THE CHALANGE !!

LITHOGHRAPHY IN THREE DIMENTIONS ??LITHOGHRAPHY IN THREE DIMENTIONS ??

Single Dot SET Fabrication (2)Single Dot SET Fabrication (2)PAttern Dipendent OXidation (PADOX)*Idea stressed silicon has a lower oxidation rate

EPFL’s Approach : (i) no e-beam (ii) smaller island size

*NTT Japan

Multi Dot SET Fabrication (1)Multi Dot SET Fabrication (1)

Drain

Source

Gate

nanograin wire

(a)

-5

-4

-3

-2

-1

0

1

2

3

4

5

-0.1 0.0 0.0 0.0 0.0 0.1

Drain to source voltage, V DS (V)

Drain to source current, I

DS

(nA)VGS = 0V

Coulomb Blockade

(b)

0

1

2

3

4

5

6

7

-0.2 -0.1 0.0 0.1 0.2

Gate to source voltage, V GS (V)

Drain to source current, I

DS

(nA)

VDS = 0.045V

(c)

Multi Dot Device: Non-classical SET

Advantage: Easier to fabricate than single dot device

Difficulties: Modelling and Design

Multi Dot SET Fabrication (2)Multi Dot SET Fabrication (2)

EPFL’s nano-grain polysilicon wire technique

= 10-20nm

CMOS-SET Co-Fabrication*CMOS-SET Co-Fabrication*

*S. Ecoffey et al. MNE 04

SummarySummary

• Single Electron Transistor (SET) is an attractive candidate for future ultra low power nano-electronics.

• Due to some of its intrinsic limitations (low current drive, lack of room temperature operable technology) it is unlikely that SET can replace the CMOS world.

• However, the unique properties (e.g., Coulomb blockade oscillations) of SETs can be exploited to increase CMOS functionalities by hybrid CMOS-SET approach.

• SETMOS is one such hybrid CMOS-SET architecture, which combines the virtues of both devices and exhibits many novel functionalities which are very difficult to achieve by either of these technologies.