Recap Exceptions and rollbacks Register renaming Branches and register renaming Summary HY425 Lecture 07: Precise Interrupts, Implementing Speculation Dimitrios S. Nikolopoulos University of Crete and FORTH-ICS October 31, 2011 Dimitrios S. Nikolopoulos Interrupts and Speculation 1 / 47
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HY425 Lecture 07: Precise Interrupts, Implementing Speculationhy425/2012f/lectures/lecture07-handout.pdf · I Program must resume execution I Example: page faults I No speculative
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I Instructions dependent on pending instructions not issuedI Instructions not issued due to hazardsI Other constraints (e.g. on types of instructions issued per
cycle)I Number of instructions issued per cycle variableI CPI, IPC, limited by dependencies, hazards
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RecapExceptions and rollbacks
Register renamingBranches and register renaming
Summary
Speculation basicsI Multiple-issue processors need more independent
instructionsI Wide-issue processors may need to predict one or more
branches per cycleI Hard to maintain high clock rate
I Speculation attempts to overcome problemI Execute program as if all branches were predicted correctlyI Dynamic scheduling waits for branches insteadI Need mechanism to undo instructions from incorrect path
I Three elements in speculationI Dynamic branch predictionI Ability to undo speculative instructions from wrong pathI Dynamic scheduling
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RecapExceptions and rollbacks
Register renamingBranches and register renaming
Summary
Maintaining precise exceptions
Reorder buffer (ROB)
I Instructions generating exceptions do not commit until theyreach the head of the ROB
I In scoreboard, Tomasulo, instructions commit out of order:I Out-of-order instructions modify state (register memory)I Exceptions from in-order instructions are imprecise
I Recoverable memory exceptionsI Program must resume execution
I Example: page faultsI No speculative state should exist when program resumes
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RecapExceptions and rollbacks
Register renamingBranches and register renaming
Summary
Precise exceptions with speculation
Example
I Assume all instructions in the loop have issued twiceI Assume all instructions have completed executionI LD, MULD of first iteration have committed
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RecapExceptions and rollbacks
Register renamingBranches and register renaming
Summary
Multiple issue without speculationAssume separate LD-ST and INT units
MemoryIssues at Executes at access at Write CDB at
Iteration clock cycle clock cycle clock cycle clock cyclenumber Instruction number number number number Comment
1 LD R2,0(R1) 1 2 3 4 First issue1 ADDI R2,R2,1 1 5 6 Wait for LD1 SD R2,0(R1) 2 3 7 Wait for ADDI1 ADDI R1,R1,4 2 3 4 Execute directly1 BNE R2,R3,Loop 3 7 Wait for ADDI2 LD R2,0(R1) 4 8 9 10 Wait for BNE2 ADDI R2,R2,1 4 11 12 Wait for LD2 SD R2,0(R1) 5 9 13 Wait for ADDI2 ADDI R1,R1,4 5 8 9 Execute directly2 BNE R2,R3,Loop 6 13 Wait for ADDI3 LD R2,0(R1) 7 14 15 16 Wait for BNE3 ADDI R2,R2,1 7 17 18 Wait for LD3 SD R2,0(R1) 8 15 19 Wait for ADDI3 ADDI R1,R1,4 8 14 15 Execute directly3 BNE R2,R3,Loop 9 19 Wait for ADDI
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RecapExceptions and rollbacks
Register renamingBranches and register renaming
Summary
Multiple issue with speculationAssume separate LD-ST and INT units
WritesIssues at Executes Read access CDB at Commits
Iteration at clock at clock at clock clock at clocknumber Instruction number number number number number Comment
1 LD R2,0(R1) 1 2 3 4 5 First issue1 ADDI R2,R2,1 1 5 6 7 Wait for LD1 SD R2,0(R1) 2 3 7 Wait for ADDI1 ADDI R1,R1,4 2 3 4 8 Commit in order1 BNE R2,R3,Loop 3 7 8 Wait for ADDI2 LD R2,0(R1) 4 8 9 10 No execute delay2 ADDI R2,R2,1 4 5 6 7 9 No Wait for LD2 SD R2,0(R1) 5 6 10 Wait for ADDI2 ADDI R1,R1,4 5 6 7 11 Commit in order2 BNE R2,R3,Loop 6 10 11 Wait for ADDI3 LD R2,0(R1) 7 8 9 10 12 Earliest possible3 ADDI R2,R2,1 7 11 12 13 Wait for LD3 SD R2,0(R1) 8 9 13 Wait for ADDI3 ADDI R1,R1,4 8 9 10 14 Executes earlier3 BNE R2,R3,Loop 9 13 14 Wait for ADDI
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RecapExceptions and rollbacks
Register renamingBranches and register renaming
Summary
Renaming registers
Alternative renaming mechanisms
I Instruction target renaming done through reservationstations in Tomasulo
I Alternative implementationsI Use ROB entriesI Use a larger set of physical registers
I Separate architecturally visible registers from physicalregisters
I Architecture registers are registers visible to programmersI Physical registers > Architecture registers (e.g. 2×)I Physical registers used for renaming, if available
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RecapExceptions and rollbacks
Register renamingBranches and register renaming
Summary
Renaming registers (cont.)
Implementation
I Register renaming done through renaming mapI Architecture register → physical registerI Status of physical registers
I Free: Register has not been assigned to instructionI Invalid: Register has been assigned to instruction for
renaming, but value has not been computed yetI Valid: Register has been assigned to instruction for
renaming, and value has been computed
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RecapExceptions and rollbacks
Register renamingBranches and register renaming
Summary
Scoreboard with register renaming – Cycle 4I P38 allocated from free list.I P6 (old destination of LD) recycled since first LD commitsI P8 (old physical register of SUBD) moved to old list
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RecapExceptions and rollbacks
Register renamingBranches and register renaming
Summary
Scoreboard with register renaming – Cycle 5I P40 allocated from free listI P2 (old physical register of second LD) recycledI P10 (old physical register of SUBD) moved to old list
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RecapExceptions and rollbacks
Register renamingBranches and register renaming
Summary
Concept of in-order instruction commit
Fixing speculation errors
I Out-of-order execution and speculation boost available ILPI In-order instruction commit helps:
I Resolve WAW, WAR hazardsI Resolve memory hazardsI Speculate past branchesI Preserve precise exceptions
I Various implementations (ROB, register map, reservationstations)
I Used in most modern high-end processors
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RecapExceptions and rollbacks
Register renamingBranches and register renaming
Summary
Implications of out-of-order execution
Complexity
I Expensive hardwareI Large storage structures, associative searchesI Complex issue logicI Complex branch prediction and speculation hardwareI Hard to handle expensive exceptions
I Diminishing performance returnsI Limits of ILP topic of next lectureI Finding more parallelism while reducing complexity topic of
following lectures
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