HW-AFX-SP3-1500_2000_Manua_V1.7

Nu Horizons Electronics Spartan3 1500 / 2000 Evaluation Platform

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HW-AFX-SP3-1500 / 2000


User Guide and Reference Manual Revision 1.7 January 10, 2006

This document describes the HW-AFX-SP3-1500 / 2000 development board provided by Nu Horizons Electronics Corp. No warranty is given for the suitability of this design for

any purpose other than prototyping and functional operation. Nu Horizons Electronics assumes no liability with respect to the use of the board nor liability for the use of the

circuitry inside the Xilinx FPGA. The information contained in this document is subject to change without notice.


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Table of Contents:

1.0 Introduction........................................................................................................... 5

Figure1: Nu Horizons Electronics Spartan3 1500 / 2000 Evaluation Board Block Diagram.......................................................................................................................... 6

2.0 Evaluation Board Contents.................................................................................. 7

3.0 Board Overview .................................................................................................... 7

LEDs................................................................................................................................... 7

Table 1: LED Pin Connections to XC3S1500 / 2000...................................................... 8

Pushbuttons ....................................................................................................................... 8

Table 2: Pushbutton Pin Connections to XC3S1500 / 2000........................................... 8

4x24 Character LCD Display........................................................................................... 8

Table 3: LCD PIN Connections – XC3S1500 / 2000...................................................... 8

4x24 Character LCD Display Read/Write Timing Chart ............................................. 9

Figure 2: 4x24 Character LCD Display Read/Write Waveforms................................... 9

PLL Clock Multiplier ..................................................................................................... 10

Figure 3: ICS511 PLL Clock Multiplier Circuit .......................................................... 10

Figure 4: U54 Oscillator Socket................................................................................... 10

Table 4: Clock PIN Connections – XC3S1500 / 2000 .................................................. 10

Table 5 – Clock Output Table....................................................................................... 11

Programmable Frequency Synthesizer......................................................................... 11

Table 6: M Divide Function Table ............................................................................... 11

Table 7: N Output Divider Function Table .................................................................. 11

Figure4: ICS84021 Frequency Divider........................................................................ 12

Table 8: ICS84201 Clock Signal – XC3S1500 / 2000 .................................................. 12

RS-232-C Interface ......................................................................................................... 12

Table 9: RS-232 Port 1 Pins – XC3S1500 / 2000......................................................... 12

Table 10: RS-232 Port 2 Pins – XC3S1500 / 2000....................................................... 12

Figure 5: RS232 Port 1 & 2.......................................................................................... 13

Table 11: RS232 Speed Select Jumper Settings............................................................ 13


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CAN 2.0B High Speed Transceiver ............................................................................... 13

Figure 6: CAN 2.0B Bus Controller & High-Speed Transceiver ................................. 14

Table 12: L9616 Connections....................................................................................... 14

Table 13:J11 CAN ASC Settings................................................................................... 14

Figure 7: CAN Interface ............................................................................................... 15

PS2 Interface ................................................................................................................... 15

Table14: PS2 Port Interface – XC3S1500 / 2000......................................................... 15

Figure 8: PS2 Port Interface ........................................................................................ 15

14bit Linear CODEC...................................................................................................... 16

Figure9: STw5093 Circuit Diagram............................................................................. 16

Table 15: Audio CODEC FPGA Signal Connections – XC3S1500 / 2000 .................. 16

Analog to Digital Converter........................................................................................... 17

Table16: LTC1865L ADC SPI Interface – XC3S1500 / 2000 ...................................... 17

Table 17: LTC1865L ADC Signal Input Header / Jumper Settings ............................. 17

Digital to Analog Converter........................................................................................... 18

Table18: LTC1654 DAC SPI I/F .................................................................................. 18

Table 19: LTC1654 DAC Signal Input Header ............................................................ 18

SDRAM Interface ........................................................................................................... 19

Table 21: SDRAM PIN I/F............................................................................................ 19

NBT SSRAM Interface (Alternative Memory – Not Included on standard build) .. 20

Table 22: SSRAM PIN I/F ............................................................................................ 20

Flash Interface................................................................................................................. 21

Table 23: Flash PIN I/F – XC3S1500 / 2000 ............................................................... 21

Test Point Headers 3.3V................................................................................................. 22

Table 24: J24 3.3V Test Point Header PIN Connections – XC3S1500 / 2000............. 22



Table 27: PD Test Points Connections......................................................................... 23

LVDS Test Point Header................................................................................................ 24

Table 28: J23 LVDS PIN Connections ......................................................................... 24


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10/100 Ethernet Media Access Controller .................................................................... 25

Table 29: SMSC 91C111 FPGA Pin Connections – XC3S1500 / 2000 ....................... 25

10/100 Ethernet Physical Interface................................................................................ 26

Table 30: ICS1893 Pin Connections – XC3S1500 / 2000 ............................................ 26

Linear Technology High Speed Analog to Digital Interface....................................... 26

Table 31: LTC High Speed ADC Evaluation Board Part Numbers ............................. 26

Figure 12: LTC Evaluation Board................................................................................ 27

Linear Technology High Speed ADC Interface Connections ..................................... 27

Table32: J29 LTC ADC Interface – XC3S1500 / 2000 ................................................ 27

Figure 13: J29 Circuit Diagram................................................................................... 28

Intersil High Speed Digital to Analog Interface........................................................... 29

Table 33: Intersil Evaluation Board Part Numbers ..................................................... 29

Intersil High Speed DAC Interface Connections ......................................................... 29

Table 34: J27 Intersil DAC Interface – XC3S1500 / 2000 ........................................... 29

Figure14: J27 Circuit Diagram.................................................................................... 30

Table 35: J28 Intersil DAC Interface – XC3S1500 / 2000 ........................................... 30


Graphical LCD Interface ............................................................................................... 31


Table 36: J31 LCD I/F Connections – XC3S1500 / 2000 ............................................ 32

Agilent Soft Touch Probe Interface .............................................................................. 33

Figure 17: Agilent E5394A Soft Touch Probe Connector Diagram ............................ 33

Programming Interface .................................................................................................. 34

Table 37: Cable III Interface ........................................................................................ 34

Table 38: Cable IV Interface ........................................................................................ 34

Operating and Storage Environments .......................................................................... 34

Regulatory Compliance (FCC Part 15 Class B, and Part 68)..................................... 34


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Scope This document defines the configuration of jumpers and the function of various components of the baseline board level hardware elements that comprise the HW-AFX-SP3-1500 / 2000 evaluation platform.

1.0 Introduction The Spartan3-1500 / 2000 evaluation platform is a very flexible testing platform that allows the engineer to evaluate the Xilinx XC3S1500 / 2000 FPGA in a typical application. Block diagram is provided, Figure 1. The distinctive features of the board include.

• Based on the Spartan 3 - 1.5 Million Gate FPGA o XC3S1500-4 FG676C

• 2 Channel A/D Converter o Linear Tech LTC1865L

16bit 150Ksps • 2 Channel D/A Converter

o Linear Tech LTC1654 14bit 8us Conversion Time

• 2 - 4M X 16 SDRAM – 128Mb o ISSI42S16400

• 32Mb Flash 2Mb X 16 o ST M29W320DB

• 4 X 24 Character LCD Interface • PS2 Port Interface • 2 - RS232 Serial Ports • CAN 2.0B Physical Layer

o ST L9616 • Graphics LCD Interface

o Logic Product Display Kit Compatible • 10/100 Ethernet Phy.

o ICS1893BF • 10/100 Ethernet MAC

o SMSC 91C111 • 16bit LVDS I/F with Clock & Control • Audio Codec

o STw5093 14bit Linear CODEC • ICS511 PLL Clock Multiplier

o 20MHz Crystal • ICS84021 PLL Clock Multiplier

o 20MHz Clock Crystal • 50 MHz clock Oscillator

o Secondary Oscillator Socket Provided • XCF08 Platform Flash for Configuration • 8 LED’s • 4 Push Buttons • 73 - 3.3V Test/Expansion Pin Headers • Agilent E5404A Soft Touch Pro Probe


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Applications:

• Microblaze Soft Processor Development • DSP System Development • Industrial Systems Development • Universal Prototyping Platform

Figure1: Nu Horizons Electronics Spartan3 1500 / 2000 Evaluation Board Block Diagram


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2.0 Evaluation Board Contents

• HW-AFX-SP3-1500 / 2000 Development Board • Documentation CD • AC Power Supply

3.0 Board Overview Power Supply The HW-AFX-SP3-1500 / 2000 board can be powered from an external power supply, two power connectors are provided. (J17 – DC Barrel Jack, J16 - Vertical Header 0.1’) External power supply must reside between 6 and 9 Volts Regulators on the board supply:

• 5.0V/750mA

• 3.3V/3A

• 2.5V /800mA– LVDS I/F

• 1.2V/2A - VccInt

• 1.8V / 2.5V/ 3.3V – 750mA Adjustable

• +12 & -12V /75mA

Power Status LED There are two power status LEDs that provide status for the 3.3V and 3.3V ANA voltage levels. LED9 – 3.3V ANA – Analog voltage level LED11 – 3.3V Digital supply voltage.

LEDs Eight LEDs are provided for display outputs. LED cathodes are driven directly from the FPGA via 470-ohm resistor, and the anodes are connected directly to 3.3V supply. :


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LED Position XC3S1500 / 2000 PIN

LED 1 M6 LED 2 M7 LED 3 M8 LED 4 N2 LED 5 N3 LED 6 N4 LED 7 N5 LED 8 N6

Table 1: LED Pin Connections to XC3S1500 / 2000

Pushbuttons Four pushbuttons are provided for circuit input. Pushbutton Position XC3S1500 / 2000 PIN

PB_SW1 W22 PB_SW2 W24 PB_SW3 W25 PB_SW4 W26

Table 2: Pushbutton Pin Connections to XC3S1500 / 2000

4x24 Character LCD Display The HW-AFX-SP3-1500 / 2000 board includes a 4x24 Character LCD display. The LCD display has an integrated LCD controller/driver from Microtips Technology (MTC-S20400XFGNSAY). The following chart details the LCD connections to the XC3S1500 / 2000.

LCD PIN XC3S1500 / 2000 LCD_RS T19 LCD_RW T20 LCD_EN T21

LCD_DATA0 T22 LCD_DATA1 T23 LCD_DATA2 T25 LCD_DATA3 T26 LCD_DATA4 U20 LCD_DATA5 U22 LCD_DATA6 U23 LCD_DATA7 U24 BACKL_ON Y25

Table 3: LCD PIN Connections – XC3S1500 / 2000

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4x24 Character LCD Display Read/Write Timing Chart

Figure 2: 4x24 Character LCD Display Read/Write Waveforms


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PLL Clock Multiplier The HW_AFX_SP3-1500 / 2000 Evaluation Platform board provides the user with a 20MHz clock crystal Y1 in conjunction with an ICS511 PLL clock multiplier for circuit evaluation. Also an 8-pin oscillator socket, U9, is also provided for customers to install their own clock oscillator.

Figure 3: ICS511 PLL Clock Multiplier Circuit

Figure 4: U54 Oscillator Socket Clock Signal XC3S1500 / 2000 Pin

PLL_CLK AE14 MAIN_CLK AF14

Table 4: Clock PIN Connections – XC3S1500 / 2000

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Table 5 – Clock Output Table

Programmable Frequency Synthesizer The Spartan 3 – 1500 / 2000 Evaluation Board utilizes the ICS84021 frequency synthesizer to supply the high frequency clock to the Intersil Digital to Analog converter evaluation board and the XC3S1500 / 2000 FPGA. The ICS84021 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A fundamental crystal is used as the input to the on chip oscillator. The output of the oscillator is fed into the phase detector. A 25MHz crystal provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over a range of 620MHz to 780MHz. The output of the M divider is also applied to the phase detector. The programmable features of the ICS84021 support a parallel input to program the M divider and N output divider. The M value and the required values of M0 through M8 are shown in table 6 and N0 – N1 values are shown in table 7. VCO MHz M Divide M8-256 M7-128 M6-64 M5-32 M4-16 M3-8 M2-4 M1-2 M0-1

625 25 0 0 0 0 1 1 0 0 1 - - - - - - - - - - -

700 28 0 0 0 0 1 1 1 0 0 - - - - - - - - - - -

775 31 0 0 0 0 1 1 1 1 1 Table 6: M Divide Function Table N1 N0 N Value Output Min/ MHz Output Max/MHz

0 0 3 206.7 260 0 1 4 155 195 1 0 5 124 156 1 1 6 103.3 130

Table 7: N Output Divider Function Table


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Figure4: ICS84021 Frequency Divider ICS84021 Clock Signal XC3S1500 / 2000 Pin

PLL_CLK_FPGA C14 Table 8: ICS84201 Clock Signal – XC3S1500 / 2000

RS-232-C Interface The Spartan3 - 1500 / 2000 Evaluation Board uses two ST Microelectronics ST3237 level converters to generate the required RS-232-C voltage levels. Both interfaces are wired as DCE ports and have selectable speed jumper, figure 3 details the jumper and circuit. Pin definitions listed bellow in Table 6 & 7. RS232 I/F XC3S1500 / 2000 PIN

LV_RX_DATA V20 LV_TX_DATA U26

LV_RTS U25 LV_DCE_READY V22

LV_CTS V21 Table 9: RS-232 Port 1 Pins – XC3S1500 / 2000 RS232 I/F XC3S1500 / 2000 PIN

LV_RX_DATA2 AB14 LV_TX_DATA2 AA12

LV_RTS2 AF16 LV_DCE_READY2 AD25

LV_CTS2 AD17 Table 10: RS-232 Port 2 Pins – XC3S1500 / 2000

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Figure 5: RS232 Port 1 & 2 RS232 Speed Select Jumper Speed Selected

J1 – 1 & 2 1Mbps J1 – 2 & 3 250Kbps J2 – 1 & 2 1Mbps J2 – 2 & 3 250Kbps

Table 11: RS232 Speed Select Jumper Settings

CAN 2.0B High Speed Transceiver The Spartan3 – 1500 / 2000 Evaluation Board includes the ST Microelectronics L9616 high speed CAN bus transceiver for implementing and designing with the CAN 2.0B bus controller. Nu Horizons offers a BOSCH compliant CAN 2.0B bus controller that connects to the OPB bus of the Xilinx MicroBlaze soft processor is Figure 4 is a block diagram of the implementation of the CAN 2.0B bus controller and the L9616 high speed transceiver.


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Figure 6: CAN 2.0B Bus Controller & High-Speed Transceiver The L9616 is a bidirectional transceiver for signal conditioning and processing in connection with a CAN controller. Data rates of up to 1MEGABAUD are supported using either shielded or non-shielded pair of lines. Table 9 details the physical connections to the XC3S1500 / 2000 FPGA. CAN High Speed Transceiver XC3S1500 / 2000 Pin

1 – CAN_TX0 AB23 4 – CAN_RX0 Y26

Table 12: L9616 Connections J11 ASC Speed Select Jumper Speed Selected

J11 – 1 & 2 <= 250Kbps J11 Open <= 1Mbps

Table 13:J11 CAN ASC Settings


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Figure 7: CAN Interface

PS2 Interface The Spantan3 – 1500 / 2000 Evaluation Board includes the physical interface for the 6 pin mini PS2 port connector JR1. PS2 Pin XC3S1500 / 2000

1 – PS2_DATA V23 5 – PS2_CLK V24

Table14: PS2 Port Interface – XC3S1500 / 2000

Figure 8: PS2 Port Interface


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14bit Linear CODEC The ST Microelectronics STw5093 high performance Audio CODEC is included with the Spartan3 – 1500 / 2000 Evaluation Board. STw5093 offers a number of programmable functions accessed through a serial control channel. The PCM interface supports both non-delayed (normal and reverse) and delayed frame synchronization modes. STw5093 can be configured either as a 14-bit linear or as an 8-bit companded PCM coder. Additionally to the CODEC/FILTER function, STw5093 includes a Tone/Ring/DTMF generator, a side-tone generation, and a buzzer driver output. Figure 6 details the schematic interface.

Figure9: STw5093 Circuit Diagram STw5093 XC3S1500 / 2000 PIN STw5093 XC3S1500 / 2000 PIN

23 – COD_AUXCLK N7 20 – COD_CCLK B15 30 – MCLK N8 25 – COD_CO A15

29 – COD_FS G15 22 – COD_CI H14 28 – COD_DR F15 21 – COD_CS T8 27 - COD_DX E15

Table 15: Audio CODEC FPGA Signal Connections – XC3S1500 / 2000


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Analog to Digital Converter The Spartan3 - 1500 / 2000 Evaluation Board includes Linear Technologies LTC1865L 16 bit 150ksps Analog to Digital Converters (ADCs). The ADC can be used in ratio metric applications or with external references. The high impedance analog inputs and the ability to operate with reduced spans down to 1V full scale allow direct connection to signal sources in many applications, eliminating the need for external gain stages. LTC1865L XC3S1500 / 2000 PIN

SPI_AD_ SDI M3 SPI_AD_ SDO M2 AD_CONV_ST R21 SPI_AD_ SCK M5

Table16: LTC1865L ADC SPI Interface – XC3S1500 / 2000 Analog to Digital Converter Signal Input Header / Jumper Settings LTC1865L Jumper / Connector / Pin

ADC_CH0 J10 1 - 2 Closed / J9 / Pin 1 ADC_CH1 NA / J9 / Pin 2

ADC_CH0 Potentiometer J10 2 – 3 Closed / J9 / Pin 1 Table 17: LTC1865L ADC Signal Input Header / Jumper Settings

Figure 10: Analog to Digital Circuit


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Digital to Analog Converter The Spartan3 - 1500 / 2000 Evaluation Board includes Linear Technologies LTC1654L 14 bit, 8us conversion rate Digital to Analog Converters (DAC). The LTC1654 is a dual, rail-to-rail voltage output, 14-bit digital-to-analog converter (DAC) which includes output buffer amplifiers and a flexible serial interface. The LTC1654 has two programmable speeds: a FAST and SLOW mode with ±1LSB settling times of 3.5ms or 8ms respectively and supply currents of 750mA and 450mA in the two modes. The LTC1654 also has shutdown capability, power-on reset and a clear function to 0V. LTC1654 XC3S1500 / 2000 PIN

SPI_DAC_CLOCK R19 SPI_DAC_MOSI R20 SPI_DAC_MISO H1

DAC_LD D1 Table18: LTC1654 DAC SPI I/F Digital to Analog Converter Signal Input Header / Jumper Settings LTC1654 Connector / Pin

VoutA J5 / Pin 2 VoutB J5 / Pin 3

Table 19: LTC1654 DAC Signal Input Header

Figure 4 –LTC1654 DAC Circuit


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SDRAM Interface The Spartan3 1500 / 2000 Evaluation Board is provided with two ISSI42S16400 4X1MX16 SDRAM that interfaces with the XC3S1500 / 2000 FPGA. The ISSI42S16400 is organized as 1,048,576 bits x 16-bits x 4 bank and is a fully pipelined architecture. Pin connections are listed in table 21. SDRAM PIN 1500 / 2000 PIN SDRAM PIN 1500 / 2000 PIN

SDRAM_D0 L19 SDRAM_D29 P23 SDRAM_D1 L20 SDRAM_D30 P24 SDRAM_D2 L21 SDRAM_D31 P25 SDRAM_D3 L22 SDRAM_A0 J20 SDRAM_D4 L23 SDRAM_ A1 J21 SDRAM_D5 L25 SDRAM_ A2 J22 SDRAM_D6 L26 SDRAM_ A3 J23 SDRAM_D7 M19 SDRAM_A4 J24 SDRAM_D8 M20 SDRAM_A5 J25 SDRAM_D9 M21 SDRAM_A6 K20

SDRAM_D10 M22 SDRAM_A7 K22 SDRAM_D11 M24 SDRAM_A8 K23 SDRAM_D12 M26 SDRAM_A9 K24 SDRAM_D13 N19 SDRAM_A10 K25 SDRAM_D14 N20 SDRAM_A11 K26 SDRAM_D15 N21 CKE H20 SDRAM_D16 N22 CLK H21 SDRAM_D17 N23 UDQM0 AC18 SDRAM_D18 N24 SDRAM BA0 D26 SDRAM_D19 N25 SDRAM BA1 E23 SDRAM_D20 D25 SDRAM BA2 E24 SDRAM_D21 H24 SDRAM BA3 G26 SDRAM_D22 K21 LDQM0 AA19 SDRAM_D23 M25 /WE H26 SDRAM_D24 N26 /CAS H23 SDRAM_D25 P19 /RAS H22 SDRAM_D26 P20 /CS H25 SDRAM_D27 P21 LDQM1 AC19 SDRAM_D28 P22 UDQM1 AD18

Table 21: SDRAM PIN I/F


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NBT SSRAM Interface (Alternative Memory – Not Included on standard build) The Spartan3 – 1500 / 2000 Evaluation Board is available with a GSI GS8320V32 Synchronous 1M x 32 SRAM for high speed memory applications such as DSP. The platform can be order with the SSRAM or the SDRAM. The signals are shared with the SDRAM interface and are called out bellow. SSRAM PIN 1500 / 2000 PIN SSRAM PIN 1500 / 2000 PIN

SSRAM_D0 L19 SSRAM_A0 J20 SSRAM_D1 L20 SSRAM_ A1 J21 SSRAM_D2 L21 SSRAM_ A2 J22 SSRAM_D3 L22 SSRAM_ A3 J23 SSRAM_D4 L23 SSRAM_A4 J24 SSRAM_D5 L25 SSRAM_A5 J25 SSRAM_D6 L26 SSRAM_A6 K20 SSRAM_D7 M19 SSRAM_A7 K22 SSRAM_D8 M20 SSRAM_A8 K23 SSRAM_D9 M21 SSRAM_A9 K24 SSRAM_D10 M22 SSRAM_A10 K25 SSRAM_D11 M24 SSRAM_A11 K26 SSRAM_D12 M26 SSRAM_A12 R25 SSRAM_D13 N19 SSRAM_A13 U21 SSRAM_D14 N20 SSRAM_A14 AB24 SSRAM_D15 N21 SSRAM_A15 C23 SSRAM_D16 N22 SSRAM_A16 B23 SSRAM_D17 N23 SSRAM_A17 F21 SSRAM_D18 N24 SSRAM_A18 E21 SSRAM_D19 N25 SSRAM_A19 C22 SSRAM_D20 D25 FT P26 SSRAM_D21 H24 CLK H21 SSRAM_D22 K21 BA# D26 SSRAM_D23 M25 BB# F23 SSRAM_D24 N26 BC# F24 SSRAM_D25 P19 BD# G26 SSRAM_D26 P20 GW# H26 SSRAM_D27 P21 G# H23 SSRAM_D28 P22 BW# H22 SSRAM_D29 P23 E1# H25 SSRAM_D30 P24 SSRAM_D31 P25

Table 22: SSRAM PIN I/F


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Flash Interface The Spartan3 1500 / 2000 Evaluation Board includes a 32Mb Flash, configurable as x8 or x16 via the Byte Pin, the flash aids in the development of Microblaze soft processor cores from Xilinx. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Each block can be protected independently to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The following table details the pin connections between the Spartan3 1500 / 2000 and the Flash. Flash PIN 1500 / 2000 PIN Flash PIN 1500 / 2000 PIN

1 – A15 AF21 23 – A2 AD15 2 – A14 AF20 24 – A1 AC21 3 – A13 AF19 25 – A0 AC20 4 – A12 AF15 26 - /CE AB20 5 – A11 AE24 28 - /OE AB16 6 – A10 AE23 29 - DQ0 AB22 7 – A9 AE22 30 – DQ8 Y18 8 – A8 AE21 31 – DQ1 AC22 9 – A19 Y17 32 – DQ9 Y19 10 – A20 AD22 33 – DQ2 W14 11 - /WE AC16 34 – DQ10 AA15 12 - /RP AB17 35 – DQ3 Y14 13 – NC 36 – DQ11 AA16 14 – /WP AC17 38 – DQ4 AA14

15 – R/B Flash Ready AB21 39 – DQ12 AA17 16 – A18 AF24 40 – DQ5 W15 17 – A17 AF23 41 – DQ13 AA18 18 – A7 AE20 42 – DQ6 W16 19 - A6 AE19 43 – DQ14 AA20 20 – A5 AE15 44 – DQ7 Y16 21 – A4 AD23 45 – DQ15 AB15 22 – A3 AD21 47 - /BYTE AF17

48 – A16 AF22 Table 23: Flash PIN I/F – XC3S1500 / 2000


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Test Point Headers 3.3V The Spartan3 1500 / 2000 Evaluation Board has 73, 3.3V test point interface for user input, connector J24, J25, J32 & Test Pins PD1 – PD15 interface directly to the XC3S1500 / 2000. J24 Position 1500 / 2000 PIN J24 Position 1500 / 2000 PIN

1 – LV_I/O_0 AB8 2 – LV_I/O_1 AF11 3 – LV_I/O_2 AF10 4 – LV_I/O_3 AE11 5 – LV_I/O_4 AE10 6 – LV_I/O_5 AE9 7 – LV_I/O_6 AD9 8 – LV_I/O_7 AD8 9 – LV_I/O_8 R24 10 – LV_I/O_9 AB18

11 – LV_I/O_10 AB19 12 – LV_I/O_11 AA25 13 – LV_I/O_12 W23 14 – LV_I/O_13 AC26 15 – LV_I/O_14 AC25 16 – LV_I/O_15 AB26 17 – LV_I/O_16 AB25 18 – LV_I/O_17 AA26 19 – LV_I/O_18 W21 20 – LV_I/O_19 W20 21 - LV_I/O_20 V25 22 - LV_I/O_21 Y20 23 - LV_I/O_22 Y21 24 - LV_I/O_23 Y22 25 - LV_I/O_24 Y23 26 - LV_I/O_25 AA23 27 - LV_I/O_26 AA24 28 - LV_I/O_27 G20 29 - LV_I/O_28 G21 30 - LV_I/O_29 G22 31 - LV_I/O_30 G23 32 - LV_I/O_31 G25

33 3.3V 34 GND 35 3.3V 36 GND

Table 24: J24 3.3V Test Point Header PIN Connections – XC3S1500 / 2000 J25 Position 1500 / 2000 PIN J25 Position 1500 / 2000 PIN

1 – LV2_I/O_0 D8 2 – LV2_I/O_1 E8 3 – LV2_I/O_2 D9 4 – LV2_I/O_3 E9 5 – LV2_I/O_4 B9 6 – LV2_I/O_5 C9 7 – LV2_I/O_6 B11 8 – LV2_I/O_7 A11 9 – LV2_I/O_8 A3 10 – LV2_I/O_9 A5

11 – LV2_I/O_10 A6 12 – LV2_I/O_11 C4 13 – LV2_I/O_12 C8 14 – LV2_I/O_13 C12 15 – LV2_I/O_14 E13 16 – LV2_I/O_15 H12 17 – LV2_I/O_16 H11 18 – LV2_I/O_17 B3 19 – LV2_I/O_18 F7 20 – LV2_I/O_19 G10 21 – LV2_I/O_20 G14 22 – LV2_I/O_21 E14 23 – LV2_I/O_22 D14 24 – LV2_I/O_23 A14 25 – LV2_I/O_24 A22 26 – LV2_I/O_25 A23 27 – LV2_I/O_26 D16 28 – LV2_I/O_27 E18 29 – LV2_I/O_28 F14 30 – LV2_I/O_29 F20 31 – LV2_I/O_30 C15 32 – LV2_I/O_31 C17

33 +12V 34 GND 35 -12V 36 GND


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Table 25: J25 3.3V Test Point Header PIN Connections – XC3S1500 / 2000 J32 Position XC3S1500 / 2000 PIN J32 Position XC3S1500 / 2000 PIN

1 – EXP_SLOT_I/O_30 E2 2 – EXP_SLOT_I/O_31 E3 3 – EXP_SLOT_I/O_32 E4 4 – EXP_SLOT_I/O_33 F1 5 – EXP_SLOT_I/O_34 F2 6 – EXP_SLOT_I/O_35 F3 7 – EXP_SLOT_I/O_36 F4 8 – EXP_SLOT_I/O_37 G1 9 – EXP_SLOT_I/O_38 G2 10 – EXP_SLOT_I/O_39 G4 11 - EXP_SLOT_I/O_40 G5 12 - EXP_SLOT_I/O_41 G6 13 - EXP_SLOT_I/O_42 G7 14 - EXP_SLOT_I/O_43 H2 15 - EXP_SLOT_I/O_44 H3 16 - EXP_SLOT_I/O_45 H4 17 - EXP_SLOT_I/O_46 H6 18 - EXP_SLOT_I/O_47 J2 19 - EXP_SLOT_I/O_48 J3 20 - EXP_SLOT_I/O_49 J4 21 - EXP_SLOT_I/O_50 J4 22 - EXP_SLOT_I/O_51 J6

Table 26: J32 3.3V Test Point Header PIN Connections – XC3S1500 / 2000 PD# LOCATION/CONNECTION PD# LOCATION/ CONNECTION

1 J31 – PIN 2 9 1500 / 2000 – AE16 2 J31 – PIN 55 10 GND 3 1500 / 2000 – AA19 11 1500 / 2000 – AE17 4 1500 / 2000 – AC18 12 GND 5 1500 / 2000 – AC19 13 1500 / 2000 – AE18 6 1500 / 2000 – AD18 14 GND 7 1500 / 2000 – AD19 15 1500 / 2000 – AF17 8 GND

Table 27: PD Test Points Connections


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LVDS Test Point Header The Spartan3 1500 / 2000 Evaluation Board has 20 LVDS pairs available for high-speed communications; the arraignment is 8TX pairs, 8RX pairs, 1RX control, 1TX control, 1RX clock and 1TX clock. J23 Position 1500 / 2000 PIN J23 Position 1500 / 2000 PIN

1 – LVDS_CNT_TX0_P E10 2 – LVDS_I/O_RX_0_P C10 3 – LVDS_CNT_TX0_N F10 4 – LVDS_I/O_RX_0_N D10 5 – LVDS_I/O_TX_0_P A4 6 – LVDS_I/O_RX_1_P F11 7 – LVDS_I/O_TX_0_N B4 8 – LVDS_I/O_RX_1_N G11 9 – LVDS_I/O_TX_1_P B5 10 – LVDS_I/O_RX_2_P D11

11 – LVDS_I/O_TX_1_N C5 12 – LVDS_I/O_RX_2_N E11 13 – LVDS_I/O_TX_2_P D6 14 – LVDS_I/O_RX_3_P H13 15 – LVDS_I/O_TX_2_N E6 16 – LVDS_I/O_RX_3_N G12 17 – LVDS_I/O_TX_3_P B6 18 – LVDS_I/O_RX_4_P E12 19 – LVDS_I/O_TX_3_N C6 20 – LVDS_I/O_RX_4_N F12 21 - LVDS_I/O_TX_4_P D7 22 - LVDS_I/O_RX_5_P A12 23 - LVDS_I/O_TX_4_N E7 24 - LVDS_I/O_RX_5_N B12 25 - LVDS_I/O_TX_5_P A7 26 - LVDS_I/O_RX_6_P G13 27 - LVDS_I/O_TX_5_N B7 28 - LVDS_I/O_RX_6_N F13 29 - LVDS_I/O_TX_6_P A8 30 - LVDS_I/O_RX_7_P A10 31 - LVDS_I/O_TX_6_N B8 32 - LVDS_I/O_RX_7_N B10 33 - LVDS_I/O_TX_7_P F9 34 – LVDS_CNT_RX0_P D13 35 - LVDS_I/O_TX_7_N G9 36 - LVDS_CNT_RX0_N C13 37 – LVDS_CN_CLK_P F8 38 – LVDS_CN_CLK2_P A13 39 – LVDS_CN_CLK_N G8 40 – LVDS_CN_CLK2_N B13

Table 28: J23 LVDS PIN Connections


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10/100 Ethernet Media Access Controller The Spartan3 – 1500 / 2000 Evaluation Board includes the SMSC LAN91C111 10/100 Ethernet MAC with integrated 802.3 Physical Layer, for twisted pair applications. The bus interface is accessed as a 32bit I/O slave along with a slave DMA type data path that accepts burst transfers. LAN91C111 1500 / 2000 PIN LAN91C111 1500 / 2000 PIN

SMSC_DATA_0 AB6 SMSC_Addr_0 AF13 SMSC_DATA_1 AB7 SMSC_Addr_1 P2 SMSC_DATA_2 AB9 SMSC_Addr_2 P3 SMSC_DATA_3 AB10 SMSC_Addr_3 P4 SMSC_DATA_4 AB11 SMSC_Addr_4 P5 SMSC_DATA_5 AC6 SMSC_Addr_5 P6 SMSC_DATA_6 AC7 SMSC_Addr_6 P7 SMSC_DATA_7 AC8 SMSC_Addr_7 P8 SMSC_DATA_8 AC9 SMSC_Addr_8 R1 SMSC_DATA_9 AC10 SMSC_Addr_9 R3 SMSC_DATA_10 AC11 SMSC_Addr_10 R5 SMSC_DATA_11 AD4 SMSC_Addr_11 R6 SMSC_DATA_12 AD5 SMSC_Addr_12 R7 SMSC_DATA_13 AD6 SMSC_Addr_13 R8 SMSC_DATA_14 AD10 SMSC_Addr_14 T1 SMSC_DATA_15 AD12 SMSC_nBE0 T2 SMSC_DATA_16 AE4 SMSC_nBE1 T4 SMSC_DATA_17 AE5 SMSC_nBE2 T5 SMSC_DATA_18 AE6 SMSC_nBE3 T6 SMSC_DATA_19 AE8 RESET_N Y12 SMSC_DATA_20 AF4 SMSC_ARDY AA13 SMSC_DATA_21 AF6 SMSC_INTR AF5 SMSC_DATA_22 AF8 SMSC_nLDEV AF12 SMSC_DATA_23 U3 SMSC_nRD AA11 SMSC_DATA_24 U5 SMSC_nWR P4 SMSC_DATA_25 U6 SMSC_nCS AE12 SMSC_DATA_26 U7 SMSC_AEN Y10 SMSC_DATA_27 V2 LCLK R20 SMSC_DATA_28 V3 W/Nr T7 SMSC_DATA_29 V4 RDYRTN U2 SMSC_DATA_30 V5 CYCLE R24 SMSC_DATA_31 V6 nADS R26

Table 29: SMSC 91C111 FPGA Pin Connections – XC3S1500 / 2000

MuthuKumaran

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Pin changed to T4

MuthuKumaran

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10/100 Ethernet Physical Interface The Spartan3 – 1500 / 2000 Evaluation Board includes a 10/100 Ethernet Physical Interface for implementing an on chip Ethernet Media Access Controller. The ICS1893BF incorporates Auto-MDIX feature that automatically corrects crossover errors in plant wiring. ICS1893 Signal 1500 / 2000 Pin ICS1893 Signal 1500 / 2000 Pin

RXD3 AB5 TXD3 Y11 RXD2 AB12 TXD2 Y9 RXD1 AB13 TXD1 Y8 RXD0 AC5 TXD0 W13 RXDV AC13 TXCLK W11

RXCLK AE13 TXEN W12 RXER AA6 MDIO AA10 COL AA7 MDC AA9 CRS AA8 ICS_RESET_n Y13

10/100 H7 Table 30: ICS1893 Pin Connections – XC3S1500 / 2000

Linear Technology High Speed Analog to Digital Interface The Spartan3 – 1500 / 2000 Evaluation Board includes the physical interface to the Linear Technology high-speed A/D evaluation acquisition boards. The family includes the following converter evaluation boards. Eval Board Part # ADC PART # RESOLUTION SAMPLE RATE INPUT FREQUENCY

520B-A LTC1748 14 Bit 80Msps Ain < 40MHz 520B-B LTC1748 14 Bit 80Msps Ain > 40MHz 520B-C LTC1745 12 Bit 25Msps Ain < 40MHz 520B-D LTC1746 14 Bit 25Msps Ain < 40MHz 520B-E LTC1747 12 Bit 80Msps Ain < 40MHz 520B-F LTC1747 12 Bit 65Msps Ain > 40MHz 520B-G LTC1742 14 Bit 65Msps Ain < 40MHz 520B-H LTC1742 14 Bit 65Msps Ain > 40MHz 520B-I LTC1741 12 Bit 65Msps Ain < 40MHz 520B-J LTC1741 12 Bit 65Msps Ain > 40MHz 520B-K LTC1743 12 Bit 50Msps Ain < 40MHz

Table 31: LTC High Speed ADC Evaluation Board Part Numbers


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Figure 12: LTC Evaluation Board

Linear Technology High Speed ADC Interface Connections LTC A/D Interface 1500 / 2000 PIN LTC A/D Interface 1500 / 2000 PIN D0 – EXP SLOT_I/O_66 M1 D8 – EXP SLOT_I/O_58 K6 D1 – EXP SLOT_I/O_65 L7 D9 – EXP SLOT_I/O_57 K5 D2 – EXP SLOT_I/O_64 L6 D10 – EXP SLOT_I/O_56 K4 D3 – EXP SLOT_I/O_63 L5 D11– EXP SLOT_I/O_55 K3 D4 – EXP SLOT_I/O_62 L4 D12 – EXP SLOT_I/O_54 K2 D5 – EXP SLOT_I/O_61 L2 D13 – EXP SLOT_I/O_53 K1 D6 – EXP SLOT_I/O_60 L1 OF – EXP SLOT_I/O_52 J7 D7 – EXP SLOT_I/O_59 K7 CLK_ADC AD13

Table32: J29 LTC ADC Interface – XC3S1500 / 2000


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Figure 13: J29 Circuit Diagram


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Intersil High Speed Digital to Analog Interface The Spartan 3 - 1500 / 2000 Evaluation Board includes the interface to Intersil high speed DACs ISL5x29EVAL1 evaluation cards for developing high performance DSP applications such as Quadrature Transmit with an IF Range 0 – 80MHz and Medical/Test Instrumentation and Equipment. Table 8 details the available evaluation platforms from Intersil. Intersil Part Number Number of bits Clock Speed

ISL5629EVAL1 2x8 210MHz ISL5729EVAL1 2x10 210MHz ISL5829EVAL1 2x12 210MHz ISL5929EVAL1 2x14 210MHz

Table 33: Intersil Evaluation Board Part Numbers

Intersil High Speed DAC Interface Connections

Intersil DAC Signal XC3S1500 / 2000 Pin Q_Data_0 - EXP_SLOT_I/O_29 E1 Q_Data_1 - EXP_SLOT_I/O_28 D2 Q_Data_2 - EXP_SLOT_I/O_27 AC2 Q_Data_3 - EXP_SLOT_I/O_26 AA2 Q_Data_4 - EXP_SLOT_I/O_25 W3 Q_Data_5 - EXP_SLOT_I/O_24 U4 Q_Data_6 - EXP_SLOT_I/O_22 P1 Q_Data_7 - EXP_SLOT_I/O_21 AC1 Q_Data_8 - EXP_SLOT_I/O_20 AB4 Q_Data_9 - EXP_SLOT_I/O_19 AB3 Q_Data_10 - EXP_SLOT_I/O_18 AB2 Q_Data_11 - EXP_SLOT_I/O_17 AB1 Q_Data_12 - EXP_SLOT_I/O_16 AA5 Q_Data_13 - EXP_SLOT_I/O_15 AA4

CLK - EXP_SLOT_I/O_23 R2 Table 34: J27 Intersil DAC Interface – XC3S1500 / 2000


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Figure14: J27 Circuit Diagram

Intersil DAC Signal XC3S1500 / 2000 Pin I_Data_0 - EXP_SLOT_I/O_14 AA3 I_Data_1 - EXP_SLOT_I/O_13 AA1 I_Data_2 - EXP_SLOT_I/O_12 Y7 I_Data_3 - EXP_SLOT_I/O_11 Y6 I_Data_4 - EXP_SLOT_I/O_10 Y5

CLK - EXP_SLOT_I/O_8 Y2 I_Data_6 - EXP_SLOT_I/O_7 Y1 I_Data_7 - EXP_SLOT_I/O_6 W7 I_Data_8 - EXP_SLOT_I/O_5 W6 I_Data_9 - EXP_SLOT_I/O_4 W5 I_Data_10 - EXP_SLOT_I/O_3 W4 I_Data_11 - EXP_SLOT_I/O_2 W2 I_Data_12 - EXP_SLOT_I/O_1 W1 I_Data_13 - EXP_SLOT_I/O_0 V7 I_Data_5 - EXP_SLOT_I/O_9 Y4

Table 35: J28 Intersil DAC Interface – XC3S1500 / 2000


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Figure 15: J28 Circuit Diagram

Graphical LCD Interface The Spartan3 – 1500 / 2000 Evaluation Board interfaces directly to the Logic Product Developments Display Kits, to review the available Display Kits reference http://www.logicpd.com/eps/peripherals.php The Spartan3 – 1500 / 2000 Evaluation Board has a 2x30 pin 0.100" header (J31) that connects all of the LCD signals directly from the evaluation boards FPGA. Depending on your specific display, only a few of the LCD signals may be needed. Table details the physical connections to the XC3S1500 / 2000 FPGA. Figure details the connector circuit.


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Figure 16: J31 Circuit Diagram J31- LCD I/F 1500 / 2000 Pin J31-LCD I/F 1500 / 2000 Pin

LCD_MOD D21 BLUE5 E16 LCD_SPL E20 BLUE4 F16 LCD_SPS B21 BLUE3 G16

LCD_CLK_RETURN G19 BLUE2 H16 LCD_VEEEN B22 BLUE1 A17

LCD_DON B20 BLUE0 B17 LCD_CLK B14 GREEN5 E17

HSYNC G18 GREEN4 F17 VSYNC D17 GREEN3 G17

LCD_REV C21 GREEN2 B18 LCD_HRLP B16 GREEN1 C18

LCD_PSAVE A21 GREEN0 F18 LCD_CLS A16 RED5 A19

LCD_VDDEN RED4 B19 LCD_MDISP D20 RED3 C19 LCD_PWM H15 RED2 D19

RED0 F19 RED1 E19 Table 36: J31 LCD I/F Connections – XC3S1500 / 2000


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Agilent Soft Touch Probe Interface The Spartan3 – 1500 / 2000 Evaluation Board includes the Agilent Soft Touch Probe, E5394A which is a 34-channel single-ended soft touch connectorless probe compatible with all Agilent logic analyzers that have a 40-pin pod connector. It is capable of acquiring data at the maximum rates of the logic analyzer it is connected to.

LV2_I/O_14

AGILENT SOFT TOUCH PROBEFOOTPRINT

LV2_I/O_27

LV2_I/O_28

LV2_I/O_2

LV2_I/O_10LV2_I/O_8

LV2_I/O_24

LV2_I/O_9

GND

U66

AGILENT E5404A

A1A2A3A4A5A6A7A8A9

A10A11A12A13A14A15A16A17A18A19A20A21A22A23A24A25A26A27

B1B2B3B4B5B6B7B8B9B10B11B12B13B14B15B16B17B18B19B20B21B22B23B24B25B26B27

D0D1GNDD4D5GNDCK 1+GND/NCGNDD10D11GNDD14D15GNDD2D3GNDD6D7GNDD8D9GNDD12D13GND

GNDD2D3

GNDD6D7

GNDD8D9

GNDD12D13

GNDD0D1

GNDD4D5

GNDGND/NC

CK2 +GNDD10D11

GNDD14D15

LV2_I/O_0

GND

LV2_I/O_1

LV2_I/O_20

LV2_I/O_3

LV2_I/O_6

LV2_I/O_26

LV2_I/O_15

LV2_I/O_29

LV2_I/O_21

LV2_I/O_7

LV2_I/O_16

LV2_I/O_11LV2_I/O_12

LV2_I/O_30

LV2_I/O_4

LV2_I/O_22

LV2_I/O_31

LV2_I/O_18

LV2_I/O_25

LV2_I/O_5

LV2_I/O_23

LV2_I/O_17

LV2_I/O_13

LV2_I/O_19

Figure 17: Agilent E5394A Soft Touch Probe Connector Diagram


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Programming Interface The Spartan3 1500 / 2000 Evaluation Board supports JTAG configuration by the Xilinx JTAG Cable III (Connector J3) and Cable IV (Connector J4). Table 14 and 15 detail the physical pin connections to the XC3S1500 / 2000 FPGA. Programming Status LED LD10 – Programming status LED – Done Pin going high, confirming configuration of the FPGA.

Cable III – J3 XC3S1500 / 2000 PIN 3 – TCK B24 4 – TDO D24 5 – TDI C1 6 - TMS A24

Table 37: Cable III Interface Cable IV – J4 XC3S1500 / 2000 PIN

6 - TCK B24 8 - TDO D24 10 – TDI C1 4 - TMS A24

Table 38: Cable IV Interface

Operating and Storage Environments Temperature The HW-AFX-SP3-1500 / 2000 development board can be safely stored at temperatures ranging from -20 – 85º C. The HW-AFX-SP3-1500 / 2000 development board will operate reliably in an ambient temperature of 0 - 70º C. Humidity The HW-AFX-SP3-1500 / 2000 development board is reliable in storage and operating in a relative humidity of 10% to 95% non-condensing for the appropriate temperature ranges listed above.

Regulatory Compliance (FCC Part 15 Class B, and Part 68) This product is sold as an evaluation platform only. No EMI testing was performed.

HW-AFX-SP3-1500_2000_Manua_V1.7

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