Huang-Yu Chen † , Mei-Fang Chiang † , Yao-Wen Chang † Lumdo Chen ‡ , and Brian Han ‡ Novel Full-Chip Gridless Routing Considering Double- Via Insertion † The Electronic Design Automation Laboratory Graduate Institute of Electronics Engineering Department of Electrical Engineering National Taiwan University Taiwan ‡ UMC, Taiwan
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Huang-Yu Chen † , Mei-Fang Chiang † , Yao-Wen Chang † Lumdo Chen ‡ , and Brian Han ‡
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Outline Introduction Redundant-Via Aware Two-Pass Routing System Post-Layout Double-Via Insertion Algorithm Experimental Result Conclusion
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Outline Introduction Redundant-Via Aware Two-Pass Routing System Post-Layout Double-Via Insertion Algorithm Experimental Result Conclusion
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Redundant-Via Insertion Via-open defectsVia-open defects are one of the dominant failures due
to the low-k, copper metal process in the nanometer era Redundant-via insertionRedundant-via insertion is highly recommended
by foundries to improve via yield and reliability Double vias have 10X 100X smaller failure rates than single vias
90nm copper interconnect(source: TSMC)
double-via insertion
metal 1metal 2
viaredundant via
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Dead, Alive, and Critical Vias For a via, a redundant-via candidateredundant-via candidate is its adjacent
position where a redundant via can be inserted Via categories:
Dead via:Dead via: the via with no redundant-via candidate Alive via: Alive via: the via with at least one redundant-via candidate Critical via:Critical via: the via with exactly one redundant-via candidate
critical via
dead viaalive vias
metal 1metal 2
viaredundant-via candidate
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SS
TT
SS
TT
Redundant-Via Aware Routing Traditionally, double-via insertion is focused on the
post-layout stage Minimizing dead and critical vias during routingMinimizing dead and critical vias during routing can
increase the post-layout double-via insertion rate by 15 25%
Dead vias cannot be paired with redundant vias Critical vias may not be paired due to competition with others
SS
TT
a bad path a better pathdead via alive via
a routing instance
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Outline Introduction Redundant-Via Aware Two-Pass Routing System Post-Layout Double-Via Insertion Algorithm Experimental Result Conclusion
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Multilevel Routing Billions of transistors may be fabricated in a single chip Multilevel routingMultilevel routing has demonstrated the superior
capability of handling large-scale designs
Already-routed netTo-be-routed net
coarsening uncoarsening
‧global routing ‧detailed routing
‧failed nets rerouting‧refinement
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Observations In the coarsening stage, global and detailed routing global and detailed routing
are intertwined with each otherare intertwined with each other at each level Advantage:
Routing resource estimation is accurate Information of previously routed nets is exactly
known Disadvantage:
Optimization freedom is limited Refinement takes a lot of efforts and the solution
easily falls into local optima
Need more flexibility to address Need more flexibility to address nanometer electrical effectsnanometer electrical effects
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SeparateSeparate global routing and detailed routing Effectively perform global and detailed routing optimization
Pre-analyzePre-analyze congestion congestion to assist resource estimation
Apply bottom-upbottom-up routing approaches to handle local circuit effects
Better for routability, congestion, and via minimization Redundant-via planning is a local effect
Maximize the optimization freedom
Ideas for Improvements
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Our Two-Pass, Bottom-Up Routing FrameworkTo-be-routed net Already-routed net
G0
G1
G2
coarsening
First Pass StageFirst Pass Stage Second Pass StageSecond Pass StagePrerouting StagePrerouting Stage
high
low
coarsening
G0
G1
G2
coarsening
coarsening
Apply global routingglobal routing for local nets and iteratively refine the solution
Use detailed routingdetailed routing for local nets, reroute failed nets, and estimate resources level by level
Identify congestion congestion hot spotshot spots based on the routing topology of each net
The objective is to minimize dead and critical vias Router should select a path that passes through the
fewest redundant-via candidates in the routing graph It may incur more detours and thus more vias
Must consider (1) redundant-via planning and (2) via minimization simultaneously
Take the via countvia count and redundant-via related penaltyredundant-via related penalty as the cost to guide the detailed maze routing
Redundant-Via Aware Detailed Routing
Cost function for a net n: Vn: #via, Pn: redundant-via related penalty.
n n V P
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Redundant-Via Related Penalty Degree of Freedom of via v (DoFv):
# of redundant-via candidates of v Set the cost of redundant-via candidate r as
S
T
1/3
1/3
1/3
1/4
1/4
1/4
1/4
1/2
1/2
metal 1 metal 2 via redundant-via candidate
S
T
penalty = 5/6
penalty = 1/4
?
?
1iv
DoF{ max{ } | vi is the via that shares r }
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Outline Introduction Redundant-Via Aware Two-Pass Routing System Post-Layout Double-Via Insertion Algorithm Experimental Result Conclusion
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Post-Layout Double-Via Insertion Problem Given a post-routing layout, pair each via with one
redundant via as many as possible without incurring any design-rule violation
Different approaches may affect the insertion result
2 vias are paired 3 vias are paired
metal 1metal 2
viaredundant via
Better Yield
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Previous Work Yao et al. [GLSVLSI’05] mentioned that post-layout
double-via insertion can be solved by maximum bipartite matching
Lee and Wang [ASPDAC’06] showed that maximum maximum bipartite matching formulation is incorrect for some bipartite matching formulation is incorrect for some casescases
Lee and Wang used maximum independent set (MIS)maximum independent set (MIS) to solve the problem and applied heuristics to speed up
MIS is NP-complete, MIS is NP-complete, high time complexityhigh time complexity
Optimal Algorithm for up to 3 Routing LayersOptimal Algorithm for up to 3 Routing Layers On-Track/Stack Redundant-Via Enhancement Two-Stage Double-Via Insertion (TDVI) Algorithm
Experimental Result Conclusion
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Our Bipartite Formulation If stack via is treated as one unit viastack via is treated as one unit via, the double-via
insertion for designs with up to 3 layersup to 3 layers can be optimally solved by maximum bipartite matchingmaximum bipartite matching A polynomial-time optimal algorithm for the restricted case
The troublesome example can be accurately formulated
v1 v2
routing layout redundant-via candidate
metal 1metal 2
via12metal 3
via13
r2
v2
v3r
v1
v2
v1v2
cross-section view
v2
v1r2
v2
v3r
v1
v2 v2
v1
v2 is pairedv1 is paired
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r4,5
v1
v2
r1
r2
r3
r6
Alive Vias
Redundant-ViaCandidates
v3 r9
r7,8
final bipartite graph
Optimal Algorithm for up to 3 Layers
metal 3metal 1 metal 2 via23 redundant-via candidatevia12
Optimal Algorithm for up to 3 Routing Layers On-Track/Stack Redundant-Via Enhancement Two-Stage Double-Via Insertion (TDVI) AlgorithmTwo-Stage Double-Via Insertion (TDVI) Algorithm
Experimental Result Conclusion
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Lb
Lt
Two-Stage Double-Via Insertion Algorithm1. Partition the layout into sublayouts with at most 3 layers,
s.t. # of design-rule conflicts between sublayouts is minimized
v1 v2
v3
v4
r3 r7
v6
r4
r8
metal 1 metal 2metal 3 metal 4
viaredundant-via candidate
r1 r2
r6r5
v5
conflict
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criticality = 2
criticality = 0
Two-Stage Double-Via Insertion Algorithm2. Decide the priority of each sublayout by criticalitycriticality
For redundant-via candidate r that has design-rule conflicts with the different sublayout, criticality cr = # of induced dead vias after inserting r; otherwise, cr = 0
Criticality of sublayout L = Σ cr, where r is inside L
v1 r1
r4
v5
v2
v3
v4
r7
r5 v6r8
metal 1 metal 2metal 3 metal 4
viaredundant-via candidate
Criticality: 0r2
r3
r6
conflict
Criticality: 2Lb
Lt
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Two-Stage Double-Via Insertion Algorithm3. Solve sublayouts in the non-decreasing order of criticality
If one sublayout is solved, update its adjacent sublayouts by removing the infeasible redundant-via candidates
v1 r1
r4
v3
r3
r6r5
metal 1 metal 2metal 3 metal 4
viaredundant-via candidate
Criticality: 0
Criticality: 2Lb
r1
r2
v1
v2
v3
v4
v5
v6
r7,8
r4,5
r3
v5
conflict
Lt
v2
v4
r7
v6r8
r2
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Outline Introduction Redundant-Via Aware Two-Pass Routing System Post-Layout Double-Via Insertion Algorithm Experimental Result Conclusion