Yafit Snir Arindam Guha Cadence Design Systems, Inc. Accelerating System level Verification of SOC Designs with MIPI Interfaces
Yafit SnirArindam GuhaCadence Design Systems, Inc.
Accelerating System level Verification of SOC Designs with MIPI Interfaces
©2017MIPIAlliance,Inc.
• Overview:MIPIVerificationapproachesandchallenges• Accelerationmethodologyoverviewandadvantages• AcceleratedverificationIPArchitecture• Migrationguidelines:fromsimulationtoacceleration• VirtualemulationusingMIPIvirtualdevicemodels• Demonstration
2
CadenceDesignSystems
Agenda
©2017MIPIAlliance,Inc.
Agenda
• Overview:MIPIVerificationapproachesandchallenges• Accelerationmethodologyoverviewandadvantages• AcceleratedverificationIPArchitecture• Migrationguidelines:fromsimulationtoacceleration• VirtualemulationusingMIPIvirtualdevicemodels• Demonstration
3
CadenceDesignSystems
©2017MIPIAlliance,Inc.
MIPICSI-2℠&MIPIDSI℠
• Widelyadoptedserialhigh-speedprotocols.• Implementedincomplexsystems,foravarietyof
applicationsindifferentmarkets:– Mobile– Automotive– Multimedia– Virtualreality,augmentedrealityandothers
4
CadenceDesignSystems
©2017MIPIAlliance,Inc.
MIPIInterfacesusageexampleinComplex/LargeSOC’sCustomer’sApplicationSpecificComponents
SoCInterconnect
ARMCPUSubsystem
3DGraphicsCore
DSPA/V
Highspeed,wiredinterfaceperipherals
LPDDR3
PHY
Storage&Memory
SAS
SD
SATA
MIPIUFS
OtherMemory
Low-speedperipheralsubsystem
MIPIhighspeedperipheralinterfaces,andother.
MIPISLIMbus®
MIPILLI℠
MIPIUniPro℠
MIPID-PHY℠
MIPIM-PHY®
I2C
JTAG
MIPICSI-2
MIPIDSI
MIPIDigRF℠
ApplicationAccelerators
…
AES
…
A15
L2cache
USB3.0
3.0PHY
2.0PHY
PCIeGen2,3
PHY
Ether-net
PHY
A15 A7
L2cache
A7
CacheCoherentFabric
Software
Furthercomplicatedbyhardware/software
interactions
©2017MIPIAlliance,Inc.
SystemLevelVerificationChallenges
• ComplexandLargeDesigns.– Longsimulationtime– NeedtoreachsystemcoveragegoalspriortoRTLfreeze.
• Timetomarket:Requiresparalleldevelopmentofhardwareandsoftwaredesign,earlyindevelopmentcycle..
• Validatingsoftwareandhardwareintegration.• Createandvalidaterealworldscenariosinapre-silicon
environment.
6
CadenceDesignSystems
©2017MIPIAlliance,Inc.
• PureSimulationverification– Fullcontrollabilityandcoveragecollection.– Acceptableperformanceformodule/subsystem.
• Hardwareassistedverification– EnablesHighperformanceforsubsystem/systemverification.– Enablespre-siliconHW/SWverification.– Enablesrunninglongertests,withhighthroughputtoreach
interestingsystemscenarios,andvalidateperformance.
7
CadenceDesignSystems
OverviewofCurrentverificationapproaches
©2017MIPIAlliance,Inc. 8
CadenceDesignSystems
Overviewofhardwareassistedverificationmethods
• SimulationAcceleration– Acceleratinghardwareverification.
• VirtualEmulation– SWDrivenHWVerification,SW/HWValidation
• In-CircuitEmulation– Enablesrealdeviceconnection
• FPGAPrototyping
©2017MIPIAlliance,Inc.
CadenceDesignSystems
Block/IPVerification
Sub-system/SoCVerification
SoClevelHW/FWIntegration
SoftwareSimulation
Signal-BasedAcceleration
Transaction-BasedAcceleration
In-CircuitEmulation
SynthesizableTestbench(STB)
Performance
SoftwareSimulationEmulatorSimulator
TB
DUT
SignalBasedAccelerationEmulatorSimulator
TB
DUT
TransactionBasedAccelerationEmulatorSimulator
TB
DUT
FullSystemValidationw.AppSW
10x
100x
1,000x
10,000x
1x
VirtualEmulation
Hybrid
VirtualEmulation(usingVirtualDeviceModels)EmulatorWorkstation
VirtualDeviceModels
DUTVirtualInterface
SynthesizableTestbenchEmulatorSimulator
TB
DUT
In-CircuitEmulationEmulator
DUT
Simulator
Hybrid
EmulatorVirtualPlatform
DUTProcessorModel
EmulatorUseModes
9
©2017MIPIAlliance,Inc.
Agenda
• Overview:MIPIVerificationapproachesandchallenges• Accelerationmethodologyoverviewandadvantages• AcceleratedverificationIPArchitecture• Migrationguidelines:fromsimulationtoacceleration• VirtualemulationusingMIPIvirtualdevicemodels• Demonstration
10
CadenceDesignSystems
©2017MIPIAlliance,Inc.
Simulationvs.Acceleration
Testbench
DesignUnder Test
Workstation
Testbench
DesignUnder Test
TBA
TBA
PROXY
BFM
Workstation Emulator
Simulation
Acceleration
DesignSize
Performance
Performancegapincreasesformorecomplexdesigns
ForsmalldesignsorIPlevelverification,simulation
performanceis“good-enough”
IP Sub-system System
Simulation-Accelerationmode• DUTrunsathigherspeedsthaningeneralpurposeCPU
• AccelerationfactordeterminedbyTBtimeandsynchronizationsbetweenTBandEmulator
11
©2017MIPIAlliance,Inc.
SignalBasedAcceleration• Bit-by-bitsignallevelexchangebetweentestbenchandDUT
• Performancebottleneckcanbethecommunicationchannelortestbenchtime
TransactionBasedAcceleration(TBA)• Reducescommunicationchanneloverheadfromsignalbasedtotransactionbased
• LeveragesfasthardwareforDUTexecution
Workstation Emulator
CommunicationChannel
Testbench DesignUnder Test
AccelerationSignalBasedAcceleration&TransactionBasedAcceleration
Testbench DesignUnder Test
TBAI/F
TBAI/F
PROXY
BFM
EmulatorWorkstation
12
©2017MIPIAlliance,Inc.
Workstation Emulator
Testbench DesignUnder Test
AcceleratedVerificationIP(AVIP)
TestbenchDesignUnder Test
TBAI/F
TBAI/F
OptimizedCore
EmulatorWorkstation
Drv
Mon
Seq
Accelerated Verification IPs optimized for performance
AVIP
13
©2017MIPIAlliance,Inc.
AccelerationMethodologyAdvantages
• Enablesorders-of-magnitudegainsinthroughputoverSimulation• Enablesreusingselectedpartsofyoursimulationverification
environment• Enablesadvancedtechnologieswithvirtualemulation,like:
– HybridoperationforoptimalpartitionofthedesignbetweenHWandSWtoachievemaximumspeedup
– ConnectiontoVirtualDevices,Virtualmachines,etc.
• EnablesOS-levelbenchmarksanddriverbring-up
14
CadenceDesignSystems
©2017MIPIAlliance,Inc.
Agenda
• Overview:MIPIVerificationapproachesandchallenges• Accelerationmethodologyoverviewandadvantages• AcceleratedverificationIPArchitecture• Migrationguidelines:fromsimulationtoacceleration• VirtualemulationusingMIPIvirtualdevicemodels• Demonstration
15
CadenceDesignSystems
©2017MIPIAlliance,Inc.
ArchitectureofAcceleratedVerificationIP(AVIP)Host (SW)
Emulator (HW)
SW Proxy
AccelerationOptimizedCore
DUT
Transactionsend/receivechannels
control/statuschannel
memrd/wrchannels
UserAPI(C/CPP/TLM2/UVM-SV)
FunctionsCallBacks
Optimizetransfertypesusingvariousstandardsforsimulator/emulator
communication.
Dynamic batching/reactive user controltooptimizeperformance
16
©2017MIPIAlliance,Inc.
Agenda
• Overview:MIPIVerificationapproachesandchallenges• Accelerationmethodologyoverviewandadvantages• AcceleratedverificationIPArchitecture• Migrationguidelines:fromsimulationtoacceleration• VirtualemulationusingMIPIvirtualdevicemodels• Demonstration
17
CadenceDesignSystems
©2017MIPIAlliance,Inc. 18
CadenceDesignSystems
OptimizingAccelerationperformance Color Legend % of time spent in testbench
% of time spent in DUT% of time spent in channel
Signal Based AccelerationWith DUT running in HW
Introduces channel overhead
SimulationTB DUT
• Profile simulation runs to identify acceleration candidates
• Select runs that are long & spend large amount of time in DUT
• Quickest path to acceleration• Maximize re-use of testbench
• Increase acceleration factor• Reduce communication overhead• Transactor may need modeling effort
Transaction Based AccelerationWith optimized channelTB
Transaction Based AccelerationWith optimized testbench
• Optimize testbench by removing verification redundancies from IP-level -stimulus generation.
• High level of acceleration• Focus on sub-system & system level
verification
Testbench optimization
Hig
her a
ccel
erat
ion
perfo
rman
ce
TB CH
©2017MIPIAlliance,Inc.
AccelerationFriendlyUVC(attheSimulationStage)
SVInterfaceAgent
BFMWrapper
VirtualInterface BFM
SWDomain SWDomain
DUT
CLK
SVInterface
BFM DUT
CLK
19
©2017MIPIAlliance,Inc.
AccelerationReady– UVC(attheEmulationStage)
Agent
Data(DPI-C)
Events
Callbacks
SWDomain HWDomain
ProxyTasks
SVInterface
SynthesizableBFM DUT
CLK
20
©2017MIPIAlliance,Inc.
Agenda
• Overview:MIPIVerificationapproachesandchallenges• Accelerationmethodologyoverviewandadvantages• AcceleratedverificationIPArchitecture• Migrationguidelines:fromsimulationtoacceleration• VirtualemulationusingMIPIvirtualdevicemodels• Demonstration
21
CadenceDesignSystems
©2017MIPIAlliance,Inc.
CadenceDesignSystems
Workstation
DSIVirtualDevice
22
Emulator
SOC Design
DSI Host Controller
Frame buffer
SW stack/drivers
GPUImage
processor
DSI AVIP BFM
DSI AVIP SW Proxy
DSI AVIP DSI Virtual Device Model
DSI ModelLogic
Virtual Display
Enables you to visualize the HW/SW operation of your video/image processing subsystem in real time
DSI Virtual Device
©2017MIPIAlliance,Inc.
CadenceDesignSystems
Workstation
23
Emulator
SOC Design
CSI-2 Host
Controller
Enables you to visualize the HW/SW operation of your video/image processing subsystem in real time
Frame buffer
SW stack/drivers
GPUImage
processor
CSI-2 AVIP BFM
CSI-2 AVIP SW
Proxy
CSI-2 AVIP CSI-2 Virtual Device Model
CSI-2 ModelLogic
Image filesCSI-2 Virtual Device
CSI-2VirtualDevice
©2017MIPIAlliance,Inc.
CadenceDesignSystems
VirtualDeviceModelsusageexample
24
LPDDRDRAM NANDFLASH
NANDFlash
Cellularmodem
WiFi
LLI
DigRF
LPDD
R 2
eMM
C4.
5
UFS
LPDD
R 3
SD 3
.0SD
4.0
UFS
SLIMbus
DSI
CSI2CSI3
Bluetooth
SDIO3
FMreceiver
GPSreceiver
RFF
E
SLIM
bus
Motionsensors
cJTAG
GBT
SPM
I
Powercontrol
Multimediaprocessor
I2C
USB
2.0
Memorycard
HDMI 1.4
Touch screencontroller
Displaydriver
Audiointerface
Applicationsprocessor
AMBA®4 ACE™
Camerainterface
USB 3.0 OTG
AMBA AXI™, AHB™OCP 2.0
OCP 3.0SSIC Emulator Simulator
Application/firmware code running to capture image file on camera and route image to display
Image files
CSI-2VirtualDevice
CSIAVIP
CSIVirtualDeviceModel
DSIVirtualDevice
DSIAVIP
DSIVirtualDeviceModel
©2017MIPIAlliance,Inc.
Agenda
• Overview:MIPIVerificationapproachesandchallenges• Accelerationmethodologyoverviewandadvantages• AcceleratedverificationIPArchitecture• Migrationguidelines:fromsimulationtoacceleration• VirtualemulationusingMIPIvirtualdevicemodels• Demonstration
25
CadenceDesignSystems
©2017MIPIAlliance,Inc.
TodiscussCadenceMIPIAcceleratedVIPsavailability,Pleasecontact:[email protected]
D-PHYDSIDeviceController
C-PHY
C-PHYDSI2DeviceController
D-PHYCSI2
DeviceController
D-PHY
C-PHY
C-PHY
D-PHY
DSIHostController
DSI2HostController
CSI2HostController
I2CController I2CController
VDMCamera
SoC
VDMDisplay
26