How does microprocessor differentiate between data and instruction and code? - As soon as µp is turned on it begins execution of code in the memory sequentially - Both opcode and data are in binary numbers, so how to differentiate? - The µp interprets the first byte it fetches as opcode and second as data - Eg. We tell the processor that our program begins at 2000h. The first code it fetches is 3Eh, when it decodes it knows that it is a 2 byte instruction, hence the second code i.e. 32h is a data byte. If we enter 06h instead of 32h then it will load 06 in the accumulator instead of 32
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How Does Microprocessor Differentiate Between Data and Instruction
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How does microprocessor differentiate between data and instruction and code?
- As soon as µp is turned on it begins execution of code in the memory sequentially
- Both opcode and data are in binary numbers, so how to differentiate?
- The µp interprets the first byte it fetches as opcode and second as data
- Eg. We tell the processor that our program begins at 2000h. The first code it fetches is 3Eh, when it decodes it knows that it is a 2 byte instruction, hence the second code i.e. 32h is a data byte. If
we enter 06h instead of 32h then it will load 06 in the accumulator instead of 32
O n e b y t e i n s t r u c ti o n s
TASK OPCODE OPERAND BINARY CODE HEX CODE
Copy contents of accumulator in
register C
MOV C,A 0100 1111 4FH
Complement each bit in the
accumulator
CMA - 0010 1111 2FH
As soon as µp decodes this it understands that it is a 1 byte instruction
Tw o b y t e i n s t r u c ti o n sTASK OPCODE OPERAND BINARY CODE HEX CODE
Load an 8 bit data byte in the
accumulator
MVI A,32H 0011 11100011 0010
3E(first byte)32(second byte)
Load an 8 bit data byte in register B
MVI B,F2H 0000 01101111 0010
06F2
2 memory locations required
As soon as µp decodes this it understands that it is a 2 byte instruction
T h r e e b y t e i n s t r u c ti o n sTASK OPCODE OPERAND BINARY CODE HEX CODE
Load of contents of memory location
2050H into A
LDA 2050H 0011 10100101 00000010 0000
3A(first byte)50(second byte)
20(third byte)Transfer the
program sequence to memory location
2085H
JMP 2085H 1100 00111000 01010010 0000
C385 20
As soon as µp decodes this it understands that it is a 3 byte instruction
C L A S S I F I C AT I O N O F I N S T R U C T I O N S E T
1.Data transfer(copy) instructions
2.Arithmetic instructions
3.Logical instructions
4. Branching instructions
5.Machine control instructions
D a t a t r a n s fe r i n s t r u c ti o n s
Definition : Copies data from source to destination, retaining the contents in the source.Note:
NOTATIONS MEANING
M Memory location pointed by HL register pair
r 8 bit register
rp 16 bit register pair
rs Source register
rd Destination register
addr 8 bit/16 bit address
The various data transfer instructions are• MOV rd,rs• MVI rd,data(8bit)• MVI M, data (8 bit)• MOV M ,rs• MOV rd, M• LXI rp , data (16 bit)• STA, addr( 16 bit)• LDA addr (16 bit)• SHLD addr(16 bit)• LHLD addr (16 bit)• STAX, rp• LDAX rp• XCHG
Instruction Description Example details
MVI r,8 bit data Loads specified register with 8 bit data Addressing mode : Immediate No. of bytes: 2 bytes Example: MVI C,30H
C 30H
MVI M,8 bit data Loads 8 bit data into a memory location whose address is specified by contents of HL register pair
Assume HL = 2055Contents of memory location 2055 = 30H
B 30H
LXI rp,16 bit data Loads 16 bit data into the register pair specified Addressing mode : immediate No. of bytes: 3 bytes Example: LXI B,6051H
B 60H
C 51H
LDA addr It loads the content specified by the memory location into the accumulator
Addressing mode : direct No. of bytes: 3 bytes Example: LDA 3500H
Assume [3500H] = 54H
A 54H
STA addr Contents of accumulator are copied to the specified memory location
Addressing mode : direct No. of bytes: 3 bytes Example: STA 3800H
A = 54H
(3800) 54H
Only higher order register is mentioned
Instruction Description Example details
LDAX rp Instruction copies content of memory location whose address is specified by register pair in the accumulator only BC or DE register pair is used
Addressing mode : Immediate No. of bytes: 1 byte Example: LDAX D
Assume DE = [4515H] = FFH
A FFH
STAX rp Copies the content of accumulator in the memory location specified by register pair
Addressing mode : register indirect No. of bytes: 1 byte Example: STAX B
Assume A = 10HBC = 4324H
[4324] 10H
LHLD addr Copies the content from the memory(address specified) into register L and content of next memory location in register H
Addressing mode : direct No. of bytes: 3 bytes Example: LHLD 2500H
Assume[2500] = 35H[2501] = 60HH 60HL 35H
SHLD addr Copies the contents of the L register in the memory(address specified) and contents of H register in the next memory location
Addressing mode : direct No. of bytes: 3 bytes Example: SHLD 2500H
AssumeL = 30H H = 55H
[2500] = 30H[2501] = 55H
Instruction Description Example details
XCHG Exchange contents of H with D register and L with E register
Assume HL = 2060HDE = 3055HH = 30H L = 55HD = 20H E = 60H
MOV rd , rs
• MOV rd,rs• this is the one byte instruction use to transfer the
the contents of source register to destination register.
• Operation : rd <----rs• It is one byte instruction• Register addressing mode• No flag is affected• eg. MOV E,B MOV D,A etc
MVI rd, data (8 bit)
• MVI rd,data (8 bit)• The eight bit data is copied immidiatly in to
the destination register.• Operation : rd <---- 8 bit data• 2 byte instruction• Immidiate addressing mode• No flags are affected• Eg : MVI A ,40 MVI C, CD
MVI M data (8 bit)
• MVI M ,data (8 bit)• This instruction copies the the 8 bit data
immidiatly to the memory location of which the address is given by HL register.
• Operation: M <--- 8bit data• Two byte instruction• Indirect addressing mode• No flags are affected• eg. MVI M 4D, MVIM ,D0
MOV rd, M
• MOV rd, M• This instruction copy the content of memory
location of which address is given by HL register pair.
• Operation: rd <---- M• One byte instruction• Indirect adrressing mode.• No flags are affected.• eg. MOV C,M MOV E , M
LXI rp , data (16 bit)
• LXI rp , data (16 bit)• This instruction copy the 16 bit data immidiatly into the
register pair specified in the instruction.The register pair may be BC , DE ,
• HL etc.• Operation : rp <--- 16 bit data• 3 byte instruction• Immidiate addressing mode• No flags are affected.• eg. LXIH 49D1 , LXID 3O7A etc.
STA , addr (16 bit)
• This instruction will copy th contents of accumulator to the address specified in the instruction.
• Operation : addr <--- A• 3 bye instruction• Direct addressing mode• No flag affected• eg. STA 40FO STA 3000.
LDA , addr(16)
• This instruction copy the content of the memory location specified in the instruction ,in to acuumulator.
• Operation : A <----addr• 3 byte instruction• Direct addressing mode• No flag affected• Eg . LDA 4800 LDA 27F7
SHLD , addr
• This insruction copy the content of H and L register to the memory address given in the instruction such that contents of H will copy to higher address and contents of L will copy to lower address.
• Operation : (addr) <---L and (addr+1) <---H• 3 byte instruction• Direct addressing mode.• No flag affected.• Eg . SHLD 3000 SHLD 30FF
LHLD , addr
• This insruction copy the conents of memory address, given in the instruction to H and L register such that lower address contents will copy in L and higher address contents will copy to H register.
• Operation : L <---- addr and H <--- addr + 1• 3 byte instruction• Direct addressing mode.• No flag affected• Eg . LHLD 3000 LHLD 93FF
STAX rp
• this instruction will copy the contents of accumulator to the memory address give by the register pair in the instruction.
• Operation : rp <-----A• 1 byte instruction.• Register indirect addrssing mode.• No flags are affected.• Eg . STAX B STAX D .
LDAX rp
• This instruction will copy the contents of memory address given by the register pair in the instruction in to accumulator.
• Operation : A <---rp• 1 byte instruction.• Register indirect addressing mode.• No flag affected.• Eg . LDAX D LDAX B.
XCHG
• This instruction will exchange the contents of HL and DE register pair .
• Operation : H <----> D and L <----> E• 1 byte instruction• Register addressing mode.• No flag affected.
ARITHMETIC GROUP
• This group contains the instructions which are responsible for arithmatical operation such as addition ,substraction, increament or decreament the data in the register.
• This group consist of following instruction• ADD r• ADD M• ADI data (8 bit)• ADC r• ADC M• ACI data (8)• DAD rp
ADD r
• This instruction add the content of register specified in instruction with contents of accumulator.Result will be stored in the accumulator.
• Operation : A <----- A + r .• 1 Byte instruction.• Register addressing mode• All flags are affected.• Eg . ADD B ,ADD C ADDM etc
ADD M
• This instruction will add the data of memory(memory address in HL REG.) with the data in accumulator .
• Operation : A <--- A + M• 1 Byte instruction.• Indirect addressing mode.• All flags are affected.• Eg . ADDM
ADI data (8 bit)
• This insruction add the 8 bit data given in the instruction with the accumulator.result will be stored in the accumulator.
• Operation : A <---- A + data 8 bit.• 2 byte instruction.• Immidiate addressing mode.• All flags are affected.• Eg . ADI 5D , ADI F9.
ADC r
• This instruction add the conents of register along with carry with register A. Result is stored in A.
• Operation : A <--- A + r + CY• 1byte instruction.• Register addressing mode.• All flags are affected.• Eg . ADC B ADCH
ADC M
• This instruction add the data in A with memory along with carry flag.result will be stored in A.
• Operation : A <---- A + M + CY• 1 byte instruction• Indirect addressing mode.• All flags are affected.• Eg . ADC M
ACI data (8 bit)
• This instruction add the 8 bit data along with carry with A .Result will be stored in A .
• Operation : A <------ A + data (8 bit) + CY.• 2 byte instruction.• Immidiate addressing mode.• All flags are affected.• Eg . ACI 87 ACI F3
DAD rp
• This instruction add the 16 bit data in the register pair with the 16 bit data in HL register.
• Result is stored in HL pair.• Operation : HL <---- HL + rp.• 1 byte instruction.• Register addressing mode.• Only carry flag is affected.• Eg .DAD B , DAD D
SUBSTRACTION
• SUB r• SUB M• SUI data (8 bit)• SBB r• SBB M• SBI data (8 bit)
SUB r
• This instruction substracts the data in register from accumulator.Result is stored in accumulator.
• Operation : A <--- A – r• 1 byte instruction.• Register addressing mode.• All flags are affected.• Eg . SUB B SUB D
SUB M
• This instruction substracts the contents of memory (address given by HL) from accumulator.Result is stored in accumulator,
• Operation : A <---- A - M.• 1 byte instruction.• Indirect addressing mode.• All flags are affected.• Eg . SUBM
SUI data (8 bit)
• This instruction substracts the 8 bit data immidiatly from A .Result is stored in accumulator.
• Operation : A <----- A- data (8 bit).• 2 byte instruction.• Immidiate addressing mode.• All flags are affected.• Eg . SUI 7A SUI 40
SBB r
• This instruction substracts the data in the register from A along with carry .Result is stored in A.
• Operation : A<----- A – r - CY.• one byte instruction.• register addrssing mode• All flags are affected.• Eg . SBB D SBB C .
SBBM
• This instruction will substracts the contents of memory (address given by HL ) from A along with carry flag.
• Operation : A <----- A – M- CY.• 1 byte instruction.• Indirect addressing mode.• All flags are affected.• Eg .SBB M
SBI data (8 bit)
• This instruction immidiatly substracts the 8 bit data from A along with carry. Result is stored in A .
• Operation : A <----- A – data (8 bit) – CY.• 2 byte instruction.• Immidiate adressing mode.• All flags are affected.• Eg . SBI 74 SBI 3B
DECIMAL ADJUST ACCUMULATOR (DAA)
• This instruction adjust the result in accumulator to valid BCD. This instruction add the no. 06 to MSB or LSB if it is greator than 9 or auxillary carry and carry flag is set.
• I byte instruction.• All flags are affected.
INCREMENT AND DECREMENTINSTRUCTION
• INR r• INR M• INX rp• DCR r• DCR M• DCX rp
INR r
• Increments the conents of specified register by one.
• Operation : r <--- r + 1.• 1 byte instruction.• Register addressing.• All flags except carry are affected.• Eg . INR D INR B
DCR r
• Decrements the contents of register by one• Operation : r <---- r + 1• One byte instruction.• Register addressing mode.• All flags except carry are affected.
INX rp
• This instruction increaments the contents of register pair by one.
• Operation : rp <---- rp + 1.• 1 byte instruction.• Register addrssing mode.• All flags are affected.• Eg .INX B INX H INX SP
INR M
• This instruction will increment the content of memory location (address given by HL) by one.
• Operation : M <----- M+ 1.• 1 Byte instruction.• Indirect addressing mode.• All flags are affected.• Eg . INR M
DCX rp
• This instruction decrement the content of the specified register pair by one.
• Operation : rp <------ rp – 1• 1 byte instruction• Register addressing mode.• All flagsd are affected.• Eg . DCX B DCX H.
DCR M
• This instruction decrements the content of memory location (address given by HL )by one.
• Operation : M<---- M - 1• 1 byte instruction.• Indirect addressing mode.• All flags are affected.• Eg . DCR M
LOGIC GROUP
• These instructions perform the logical operation on the oprand. The various logical instructions are AND , OR , XOR , NOT etc. The instructions are
• ANA r• ANA M• XRA r• XRA M• XRI data (8 bit)
• ORA r• ORA M• ORI data (8 bit)• CMP r• CMP M• CPI data(8 bit)• STC• CMC• CMA
ANAr
• This instruction AND the contents of specified register with accumulator.
• Operation : A <---- A ^ r.• 1 byte instruction.• Register addressing mode.• All flags are affected.• ANA B ANA H
ANA M
• This instruction AND the content of memory locationwith the content with acccumulator.
• Operation : A<---- A ^ M.• 1 byte instruction.• Indirect addressing mode.• All flags are affected.• Eg . ANA M
ANI data (8bit)
• This instruction AND the 8 bit data immidiatly with accumulator.
• Operation : A <----- A ^ data (8 bit)• 2 byte instruction• Immidiate addressing mode.• All flags are affected.• Eg ANI 4D ANI 5B
XRA r
• This instruction logically XOR the contents with the contents in accumulator.
• Operation : A <------ A xor r.• 1 byte instruction.• Register addressing mode.• All flags are affected with CY and AC zero• Eg . XRA B XRA H
XRA M
• This instruction logically XOR the content of memory (address given by HL ) with the contents of accumulator.
• Operation : A <---- A xor M.• 1 Byte instruction.• Indirected addressing mode.• All flags are affected with CY and AC zero.• Eg . XRAM
XRI data (8 bit)
• This instruction logically XORS the 8 bit data with contents of accumulator.
• Operation : A <----- A XOR data (8 bit) .• 2 byte instruction.• Immidiate addressing mode.• All flags are affected with CY and AC zero.• Eg .XRI D5 XRI 59
ORA r
• This instruction logically OR the contents of register with the contents of accumulator.
• Operation : A <----- A U r.• 1 byte instruction.• Register addrssing mode.• All flags are affected with CY and AC zero.• Eg . ORA B ORA D
ORA M
• this instruction logically or the content of memory (address given by hl)with the contents of accumulator.
• operation : A <---- A U M.• 1 byte instruction.• indirect addressing mode.• all flags are affected with ACand CY zero.• eg . ORA M
ORI data (8 bit)
• This instruction logically or the 8 bit data with contents of accumulator.
• Operation : A <----- A U data (8 bit).• 2 byte instruction.• Immidiate addressing mode.• All flags are affected with AC and CY zero• Eg . ORI 4D ORI C6
CMP r
• This instruction compares the contents of register with the contents of accumulator .result is not stored anywhere only flags are affected.the comparison is carried by substraction process.
• Operation : A- r.• 1 byte instruction.• Register addressing mode.• Flags are affected as 1. if A=r then Z=1• 2.If A> r then CY=0 and Z=0• 3.If A< r then CY =1 and Z=0
CMP M
• Compare the contents of A with memory.• Operation : A- M• 1 byte instruction• Indirect addressing mode• Flags affected as :• If A< M Then CY= 1 Z=0• If A > M Then CY = O Z=O• If A= M Then CY= O Z= 1
CPI data (8)
• This instruction compares the 8 bit data with A• Operation : A – data• 2 byte instruction.• Immidiate addressing mode.• Flags affected as if A< data then CY=1 Z=0• If A > data then CY= 0 Z= 0• If A = data then CY= 0 Z=1